analog.com user axi_fmcadc5_sync 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW rx_clk CLK rx_clk delay_clk CLK delay_clk ASSOCIATED_RESET delay_rst delay_rst RST delay_rst s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_fmcadc5_sync xilinx_anylanguagesynthesis_view_fileset viewChecksum b70ee2ab xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_fmcadc5_sync xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 0cbad76f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 804b322e xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset rx_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sysref out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sync_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_sync_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_sysref_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sysref_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sync_0_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sync_0_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sync_1_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sync_1_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_enable_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_data_0 in 255 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_enable_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_data_1 in 255 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_data out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation vcal out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation psync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation delay_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_csn_o in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_clk_o in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_sdo_o in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_csn out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_mosi out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_miso in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_a6e6e044 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 choice_pairs_a897e79d 0 1 2 3 4 5 6 7 xilinx_anylanguagesynthesis_view_fileset axi_fmcadc5_sync_constr.xdc xdc ../xilinx/common/ad_data_out.v verilogSource ../xilinx/common/ad_mul.v verilogSource axi_fmcadc5_sync_calcor.v verilogSource ../common/up_axi.v verilogSource axi_fmcadc5_sync.v verilogSource CHECKSUM_c6ee4d90 xilinx_anylanguagebehavioralsimulation_view_fileset ../xilinx/common/ad_data_out.v verilogSource ../xilinx/common/ad_mul.v verilogSource axi_fmcadc5_sync_calcor.v verilogSource ../common/up_axi.v verilogSource axi_fmcadc5_sync.v verilogSource xilinx_xpgui_view_fileset xgui/axi_fmcadc5_sync_v1_0.tcl tclSource CHECKSUM_243d7c29 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_fmcadc5_sync_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 Component_Name axi_fmcadc5_sync_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_fmcadc5_sync_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:02:39Z 2024.1