analog.com user axi_pulsar_lvds 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW fifo_wr EN adc_valid DATA adc_data OVERFLOW adc_dovf fifo_wr_signal_clock fifo_wr_signal_clock CLK fifo_wr_clk ASSOCIATED_BUSIF fifo_wr ref_clk CLK ref_clk dco_p CLK dco_p dco_n CLK dco_n s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_pulsar_lvds xilinx_anylanguagesynthesis_view_fileset viewChecksum 75862dd0 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_pulsar_lvds xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 2284fd30 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 747879b0 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ref_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clk_gate in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dco_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dco_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation d_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation d_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_dovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 IO_DELAY_GROUP Io Delay Group adc_if_delay_group IODELAY_CTRL Iodelay Ctrl 1 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 USERPORTS_DISABLE Userports Disable 0 DATAFORMAT_DISABLE Dataformat Disable 0 ADC_INIT_DELAY Adc Init Delay 0 ADC_DATA_WIDTH Adc Data Width 16 BITS_PER_SAMPLE Bits Per Sample 32 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_a6e6e044 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 choice_pairs_a897e79d 0 1 2 3 4 5 6 7 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/ad_data_in.v verilogSource ../common/ad_datafmt.v verilogSource ../common/ad_rst.v verilogSource axi_pulsar_lvds_channel.v verilogSource axi_pulsar_lvds_if.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_pulsar_lvds.v verilogSource CHECKSUM_a103d085 xilinx_anylanguagebehavioralsimulation_view_fileset ../xilinx/common/ad_data_in.v verilogSource ../common/ad_datafmt.v verilogSource ../common/ad_rst.v verilogSource axi_pulsar_lvds_channel.v verilogSource axi_pulsar_lvds_if.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_pulsar_lvds.v verilogSource xilinx_xpgui_view_fileset xgui/axi_pulsar_lvds_v1_0.tcl tclSource CHECKSUM_7cc27ce2 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_pulsar_lvds_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 IO_DELAY_GROUP Io Delay Group adc_if_delay_group IODELAY_CTRL Iodelay Ctrl 1 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 USERPORTS_DISABLE Userports Disable 0 DATAFORMAT_DISABLE Dataformat Disable 0 ADC_INIT_DELAY Adc Init Delay 0 ADC_DATA_WIDTH Adc Data Width 16 BITS_PER_SAMPLE Bits Per Sample 32 Component_Name axi_pulsar_lvds_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_pulsar_lvds_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:05:12Z 2024.1