analog.com user axi_rd_wr_combiner 1.0 m_axi AWADDR m_axi_awaddr AWLEN m_axi_awlen AWSIZE m_axi_awsize AWBURST m_axi_awburst AWCACHE m_axi_awcache AWPROT m_axi_awprot AWVALID m_axi_awvalid AWREADY m_axi_awready WDATA m_axi_wdata WSTRB m_axi_wstrb WLAST m_axi_wlast WVALID m_axi_wvalid WREADY m_axi_wready BRESP m_axi_bresp BVALID m_axi_bvalid BREADY m_axi_bready ARADDR m_axi_araddr ARLEN m_axi_arlen ARSIZE m_axi_arsize ARBURST m_axi_arburst ARCACHE m_axi_arcache ARPROT m_axi_arprot ARVALID m_axi_arvalid ARREADY m_axi_arready RDATA m_axi_rdata RRESP m_axi_rresp RLAST m_axi_rlast RVALID m_axi_rvalid RREADY m_axi_rready s_rd_axi ARADDR s_rd_axi_araddr ARLEN s_rd_axi_arlen ARSIZE s_rd_axi_arsize ARBURST s_rd_axi_arburst ARCACHE s_rd_axi_arcache ARPROT s_rd_axi_arprot ARVALID s_rd_axi_arvalid ARREADY s_rd_axi_arready RDATA s_rd_axi_rdata RRESP s_rd_axi_rresp RLAST s_rd_axi_rlast RVALID s_rd_axi_rvalid RREADY s_rd_axi_rready s_wr_axi AWADDR s_wr_axi_awaddr AWLEN s_wr_axi_awlen AWSIZE s_wr_axi_awsize AWBURST s_wr_axi_awburst AWCACHE s_wr_axi_awcache AWPROT s_wr_axi_awprot AWVALID s_wr_axi_awvalid AWREADY s_wr_axi_awready WDATA s_wr_axi_wdata WSTRB s_wr_axi_wstrb WLAST s_wr_axi_wlast WVALID s_wr_axi_wvalid WREADY s_wr_axi_wready BRESP s_wr_axi_bresp BVALID s_wr_axi_bvalid BREADY s_wr_axi_bready clk CLK clk ASSOCIATED_BUSIF m_axi:s_rd_axi:s_wr_axi m_axi_s_wr_axi_s_rd_axi_signal_clock m_axi_s_wr_axi_s_rd_axi_signal_clock CLK clk ASSOCIATED_BUSIF m_axi:s_wr_axi:s_rd_axi m_axi m_axi 0x100000000 64 s_rd_axi s_rd_axi reg0 reg0 0x0 0x100000000 64 register s_wr_axi s_wr_axi reg0 reg0 0x0 0x100000000 64 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_rd_wr_combiner xilinx_anylanguagesynthesis_view_fileset viewChecksum 48eca2d4 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_rd_wr_combiner xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 48eca2d4 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awaddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awlen out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wstrb out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_araddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arlen out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_wr_axi_awaddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_awlen in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_awsize in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_wr_axi_awburst in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_wr_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_awcache in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 3 s_wr_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_wr_axi_wdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_wstrb in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_wr_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_wr_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_wlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_wr_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_wr_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_wr_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_rd_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_rd_axi_araddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_rd_axi_arlen in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_rd_axi_arsize in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_rd_axi_arburst in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_rd_axi_arcache in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 3 s_rd_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_rd_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_rd_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_rd_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_rd_axi_rdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_rd_axi_rlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_rd_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 xilinx_anylanguagesynthesis_view_fileset axi_rd_wr_combiner.v verilogSource CHECKSUM_48eca2d4 xilinx_anylanguagebehavioralsimulation_view_fileset axi_rd_wr_combiner.v verilogSource xilinx_xpgui_view_fileset xgui/axi_rd_wr_combiner_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 axi_rd_wr_combiner_v1_0 Component_Name axi_rd_wr_combiner_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_rd_wr_combiner_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:05:31Z 2024.1