analog.com user spi_engine_offload 1.0 spi_engine_ctrl cmd_ready cmd_ready cmd_valid cmd_valid cmd_data cmd sdo_ready sdo_data_ready sdo_valid sdo_data_valid sdo_data sdo_data sdi_ready sdi_data_ready sdi_valid sdi_data_valid sdi_data sdi_data sync_ready sync_ready sync_valid sync_valid sync_data sync_data spi_engine_offload_ctrl cmd_wr_en ctrl_cmd_wr_en cmd_wr_data ctrl_cmd_wr_data sdo_wr_en ctrl_sdo_wr_en sdo_wr_data ctrl_sdo_wr_data enable ctrl_enable enabled ctrl_enabled mem_reset ctrl_mem_reset sync_ready status_sync_ready sync_valid status_sync_valid sync_data status_sync_data offload_sdi TVALID offload_sdi_valid TREADY offload_sdi_ready TDATA offload_sdi_data spi_engine_ctrl_offload_sdi_signal_clock spi_engine_ctrl_offload_sdi_signal_clock CLK spi_clk ASSOCIATED_BUSIF spi_engine_ctrl:offload_sdi ASSOCIATED_RESET spi_resetn spi_engine_ctrl_offload_sdi_signal_reset spi_engine_ctrl_offload_sdi_signal_reset RST spi_resetn POLARITY ACTIVE_LOW spi_engine_offload_ctrl_signal_clock spi_engine_offload_ctrl_signal_clock CLK ctrl_clk ASSOCIATED_BUSIF spi_engine_offload_ctrl xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog spi_engine_offload xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 415947b9 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog spi_engine_offload xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 415947b9 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 9caa5391 ctrl_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_cmd_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_cmd_wr_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_sdo_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_sdo_wr_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_enabled out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_mem_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_sync_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 status_sync_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdo_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sync_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 offload_sdi_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload_sdi_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload_sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ASYNC_SPI_CLK Async Spi Clk false ASYNC_TRIG Async Trig false CMD_MEM_ADDRESS_WIDTH Cmd Mem Address Width 4 SDO_MEM_ADDRESS_WIDTH Sdo Mem Address Width 4 DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 xilinx_anylanguagesynthesis_view_fileset spi_engine_offload_constr.ttcl ttcl spi_engine_offload.v verilogSource CHECKSUM_415947b9 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset spi_engine_offload.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/spi_engine_offload_v1_0.tcl tclSource CHECKSUM_1ce3c7e4 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset spi_engine_offload_v1_0 ASYNC_SPI_CLK Asynchronous core clock false ASYNC_TRIG Asynchronous trigger false CMD_MEM_ADDRESS_WIDTH Command FIFO address width 4 SDO_MEM_ADDRESS_WIDTH MOSI FIFO address width 4 DATA_WIDTH Shift register's data width 8 NUM_OF_SDI Number of MISO lines 1 Component_Name spi_engine_offload_v1_0 virtex7 /Analog_Devices spi_engine_offload_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload 1 2024-06-06T03:10:45Z 2024.1