analog.com user axi_ad3552r 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW dac_clk CLK dac_clk s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad3552r xilinx_anylanguagesynthesis_view_fileset viewChecksum b9a68d5c xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad3552r xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum a36d9abe xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 681786b0 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset dac_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dma_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 valid_in_dma in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 valid_in_dma_sec in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_data_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 data_in_a in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 data_in_b in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 valid_in_a in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 valid_in_b in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_sclk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_csn out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdio_i in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdio_o out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdio_t out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation external_sync in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sync_ext_device out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 DDS_DISABLE Dds Disable 0 DDS_TYPE Dds Type 1 DDS_CORDIC_DW Dds Cordic Dw 16 DDS_CORDIC_PHASE_DW Dds Cordic Phase Dw 16 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_a6e6e044 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 choice_pairs_a897e79d 0 1 2 3 4 5 6 7 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_rst.v verilogSource axi_ad3552r_channel.v verilogSource axi_ad3552r_core.v verilogSource axi_ad3552r_if.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad3552r.v verilogSource CHECKSUM_ab80c037 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_rst.v verilogSource axi_ad3552r_channel.v verilogSource axi_ad3552r_core.v verilogSource axi_ad3552r_if.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad3552r.v verilogSource xilinx_xpgui_view_fileset xgui/axi_ad3552r_v1_0.tcl tclSource CHECKSUM_fd1c12bb XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_ad3552r_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 DDS_DISABLE Dds Disable 0 DDS_TYPE Dds Type 1 DDS_CORDIC_DW Dds Cordic Dw 16 DDS_CORDIC_PHASE_DW Dds Cordic Phase Dw 16 Component_Name axi_ad3552r_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_ad3552r_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_ad3552r 1 2024-06-06T02:53:18Z 2024.1