analog.com
user
data_offload
1.0
s_axi
AWADDR
s_axi_awaddr
AWPROT
s_axi_awprot
AWVALID
s_axi_awvalid
AWREADY
s_axi_awready
WDATA
s_axi_wdata
WSTRB
s_axi_wstrb
WVALID
s_axi_wvalid
WREADY
s_axi_wready
BRESP
s_axi_bresp
BVALID
s_axi_bvalid
BREADY
s_axi_bready
ARADDR
s_axi_araddr
ARPROT
s_axi_arprot
ARVALID
s_axi_arvalid
ARREADY
s_axi_arready
RDATA
s_axi_rdata
RRESP
s_axi_rresp
RVALID
s_axi_rvalid
RREADY
s_axi_rready
s_axi_aclk
CLK
s_axi_aclk
ASSOCIATED_BUSIF
s_axi
ASSOCIATED_RESET
s_axi_aresetn
s_axi_aresetn
RST
s_axi_aresetn
POLARITY
ACTIVE_LOW
m_axis
TREADY
m_axis_ready
TVALID
m_axis_valid
TDATA
m_axis_data
TLAST
m_axis_last
TKEEP
m_axis_tkeep
s_axis
TREADY
s_axis_ready
TVALID
s_axis_valid
TDATA
s_axis_data
TLAST
s_axis_last
TKEEP
s_axis_tkeep
wr_ctrl
request_enable
wr_request_enable
request_valid
wr_request_valid
request_ready
wr_request_ready
request_length
wr_request_length
response_measured_length
wr_response_measured_length
response_eot
wr_response_eot
status_overflow
wr_overflow
rd_ctrl
request_enable
rd_request_enable
request_valid
rd_request_valid
request_ready
rd_request_ready
request_length
rd_request_length
response_eot
rd_response_eot
status_underflow
rd_underflow
s_storage_axis
TREADY
s_storage_axis_ready
TVALID
s_storage_axis_valid
TDATA
s_storage_axis_data
TKEEP
s_storage_axis_tkeep
TLAST
s_storage_axis_last
m_storage_axis
TREADY
m_storage_axis_ready
TVALID
m_storage_axis_valid
TDATA
m_storage_axis_data
TKEEP
m_storage_axis_tkeep
TLAST
m_storage_axis_last
s_storage_axis_m_axis_signal_clock
s_storage_axis_m_axis_signal_clock
CLK
m_axis_aclk
ASSOCIATED_BUSIF
s_storage_axis:m_axis
ASSOCIATED_RESET
m_axis_aresetn
s_storage_axis_m_axis_signal_reset
s_storage_axis_m_axis_signal_reset
RST
m_axis_aresetn
POLARITY
ACTIVE_LOW
m_storage_axis_s_axis_signal_clock
m_storage_axis_s_axis_signal_clock
CLK
s_axis_aclk
ASSOCIATED_BUSIF
m_storage_axis:s_axis
ASSOCIATED_RESET
s_axis_aresetn
m_storage_axis_s_axis_signal_reset
m_storage_axis_s_axis_signal_reset
RST
s_axis_aresetn
POLARITY
ACTIVE_LOW
s_axi
axi_lite
0
65536
0
xilinx_anylanguagesynthesis
Synthesis
:vivado.xilinx.com:synthesis
Verilog
data_offload
xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_view_fileset
viewChecksum
d9849bc7
xilinx_anylanguagebehavioralsimulation
Simulation
:vivado.xilinx.com:simulation
Verilog
data_offload
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
viewChecksum
d9849bc7
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_xpgui_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
viewChecksum
68aed832
xilinx_utilityxitfiles
Utility XIT/TTCL
:vivado.xilinx.com:xit.util
xilinx_utilityxitfiles_view_fileset
s_axi_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_awvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awaddr
in
15
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_wvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_wdata
in
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_wstrb
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
1
s_axi_wready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_araddr
in
15
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_rresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rdata
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_ready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_valid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_data
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axis_last
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_tkeep
in
7
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_ready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_valid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_data
out
127
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_last
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_tkeep
out
15
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
init_req
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
sync_ext
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_storage_axis_ready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_storage_axis_valid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_storage_axis_data
out
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_storage_axis_last
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_storage_axis_tkeep
out
7
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_storage_axis_ready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_storage_axis_valid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_storage_axis_data
in
127
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_storage_axis_last
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_storage_axis_tkeep
in
15
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_request_enable
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_request_valid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_request_ready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_request_length
out
9
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_response_measured_length
in
9
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_response_eot
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
wr_overflow
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
rd_request_enable
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rd_request_valid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rd_request_ready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rd_request_length
out
9
0
reg
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rd_response_eot
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rd_underflow
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
ddr_calib_done
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
false
ID
Id
0
MEM_TYPE
Mem Type
0
MEM_SIZE_LOG2
Mem Size Log2
10
TX_OR_RXN_PATH
Tx Or Rxn Path
0
SRC_DATA_WIDTH
Src Data Width
64
DST_DATA_WIDTH
Dst Data Width
128
DST_CYCLIC_EN
Dst Cyclic En
true
false
AUTO_BRINGUP
Auto Bringup
1
SYNC_EXT_ADD_INTERNAL_CDC
Sync Ext Add Internal Cdc
true
HAS_BYPASS
Has Bypass
true
choice_list_74b5137e
ACTIVE_HIGH
ACTIVE_LOW
choice_pairs_42f127d3
0
1
choice_pairs_68d17ab3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
choice_pairs_f3e4b7dc
0
1
xilinx_anylanguagesynthesis_view_fileset
data_offload_constr.ttcl
ttcl
data_offload_fsm.v
verilogSource
data_offload_regmap.v
verilogSource
../common/up_axi.v
verilogSource
data_offload.v
verilogSource
CHECKSUM_030b0371
xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
data_offload_sv.ttcl
ttcl
data_offload_fsm.v
verilogSource
data_offload_regmap.v
verilogSource
../common/up_axi.v
verilogSource
data_offload.v
verilogSource
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
xgui/data_offload_v1_0.tcl
tclSource
CHECKSUM_9dc0c6aa
XGUI_VERSION_2
xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_xpgui_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset
xilinx_utilityxitfiles_view_fileset
gui/data_offload_v1_0.gtcl
GTCL
ADI Data Offload Controller
ID
Core ID
0
MEM_TYPE
Storage Type
0
MEM_SIZE_LOG2
Storage Size
10
TX_OR_RXN_PATH
Data path type
0
SRC_DATA_WIDTH
Source Interface data width
64
DST_DATA_WIDTH
Destination Interface data width
128
DST_CYCLIC_EN
Destination Cyclic Mode Enabled
true
false
AUTO_BRINGUP
Auto Bringup
1
SYNC_EXT_ADD_INTERNAL_CDC
Generate CDC Circuit for sync_ext
true
HAS_BYPASS
Internal Bypass Data Path Enabled
true
Component_Name
data_offload_v1_0
virtex7
/Analog_Devices
ADI Data Offload Controller
level_2
package_project
Analog Devices
http://www.analog.com
1
2024-06-06T03:07:11Z
2024.1