analog.com
user
util_axis_fifo_asym
1.0
s_axis
TVALID
s_axis_valid
TREADY
s_axis_ready
TDATA
s_axis_data
TLAST
s_axis_tlast
m_axis
TVALID
m_axis_valid
TREADY
m_axis_ready
TDATA
m_axis_data
TLAST
m_axis_tlast
m_axis_signal_clock
m_axis_signal_clock
CLK
m_axis_aclk
ASSOCIATED_BUSIF
m_axis
ASSOCIATED_RESET
m_axis_aresetn
m_axis_signal_reset
m_axis_signal_reset
RST
m_axis_aresetn
POLARITY
ACTIVE_LOW
s_axis_signal_clock
s_axis_signal_clock
CLK
s_axis_aclk
ASSOCIATED_BUSIF
s_axis
ASSOCIATED_RESET
s_axis_aresetn
s_axis_signal_reset
s_axis_signal_reset
RST
s_axis_aresetn
POLARITY
ACTIVE_LOW
xilinx_anylanguagesynthesis
Synthesis
:vivado.xilinx.com:synthesis
Verilog
util_axis_fifo_asym
xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_view_fileset
viewChecksum
6da388ea
xilinx_anylanguagebehavioralsimulation
Simulation
:vivado.xilinx.com:simulation
Verilog
util_axis_fifo_asym
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
viewChecksum
6da388ea
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
viewChecksum
02216b5c
m_axis_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_ready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_valid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_data
out
127
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_tkeep
out
15
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_tlast
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_empty
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_almost_empty
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
m_axis_level
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_ready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_valid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_data
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axis_tkeep
in
7
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_tlast
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_full
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_almost_full
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axis_room
out
4
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
ASYNC_CLK
Async Clk
1
S_DATA_WIDTH
S Data Width
64
S_ADDRESS_WIDTH
S Address Width
5
M_DATA_WIDTH
M Data Width
128
M_AXIS_REGISTERED
M Axis Registered
1
ALMOST_EMPTY_THRESHOLD
Almost Empty Threshold
4
ALMOST_FULL_THRESHOLD
Almost Full Threshold
4
TLAST_EN
Tlast En
0
TKEEP_EN
Tkeep En
0
xilinx_anylanguagesynthesis_view_fileset
util_axis_fifo_asym.v
verilogSource
CHECKSUM_6da388ea
xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
util_axis_fifo_asym.v
verilogSource
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
xgui/util_axis_fifo_asym_v1_0.tcl
tclSource
CHECKSUM_02216b5c
XGUI_VERSION_2
xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset
xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset
util_axis_fifo_asym_v1_0
ASYNC_CLK
Async Clk
1
S_DATA_WIDTH
S Data Width
64
S_ADDRESS_WIDTH
S Address Width
5
M_DATA_WIDTH
M Data Width
128
M_AXIS_REGISTERED
M Axis Registered
1
ALMOST_EMPTY_THRESHOLD
Almost Empty Threshold
4
ALMOST_FULL_THRESHOLD
Almost Full Threshold
4
TLAST_EN
Tlast En
0
TKEEP_EN
Tkeep En
0
Component_Name
util_axis_fifo_asym_v1_0
virtex7
qvirtex7
versal
kintex7
kintex7l
qkintex7
qkintex7l
akintex7
artix7
artix7l
aartix7
qartix7
zynq
qzynq
azynq
spartan7
aspartan7
virtexu
zynquplus
virtexuplus
virtexuplusHBM
virtexuplus58g
kintexuplus
artixuplus
kintexu
/Analog_Devices
util_axis_fifo_asym_v1_0
level_2
package_project
Analog Devices
https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym
1
2024-06-06T03:06:59Z
2024.1