894 lines
37 KiB
XML
894 lines
37 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>axi_ad7616</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>s_axi</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:slave>
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<spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
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</spirit:slave>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_awaddr</spirit:name>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_awprot</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_awvalid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_awready</spirit:name>
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<spirit:name>WDATA</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_wdata</spirit:name>
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<spirit:name>WSTRB</spirit:name>
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<spirit:name>s_axi_wstrb</spirit:name>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_wvalid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_wready</spirit:name>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_bresp</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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<spirit:name>s_axi_bvalid</spirit:name>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_bready</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_araddr</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_arprot</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_arvalid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_arready</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rdata</spirit:name>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rresp</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rvalid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rready</spirit:name>
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<spirit:busInterface>
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<spirit:name>s_axi_aclk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_aclk</spirit:name>
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<spirit:parameters>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
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<spirit:busInterface>
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<spirit:name>s_axi_aresetn</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_aresetn</spirit:name>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
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<spirit:name>s_axi</spirit:name>
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<spirit:name>axi_lite</spirit:name>
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<spirit:model>
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<spirit:view>
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>axi_ad7616</spirit:modelName>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>a15f1752</spirit:value>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>axi_ad7616</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>a15f1752</spirit:value>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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<spirit:parameters>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>6a7455d5</spirit:value>
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<spirit:name>rx_cs_n</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>rx_db_o</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>rx_db_t</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>rx_rd_n</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>rx_trigger</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>s_axi_aclk</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>s_axi_awvalid</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>s_axi_awaddr</spirit:name>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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|
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>axi_ad7616_v1_0</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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|
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad7616</xilinx:vendorURL>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2024-06-06T02:54:34Z</xilinx:coreCreationDateTime>
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|
</xilinx:coreExtensions>
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|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
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|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ed2489c8"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="6614b440"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="3313f287"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="1d0290c9"/>
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</xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>
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