96 lines
4.3 KiB
Systemverilog
96 lines
4.3 KiB
Systemverilog
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of AMD and is protected under U.S. and international copyright
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// and other intellectual property laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// AMD, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) AMD shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or AMD had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// AMD products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of AMD products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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`ifndef if_do_ctrl_v1_0
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`define if_do_ctrl_v1_0
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package parameter_structs;
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typedef struct packed {
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bit portEnabled;
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integer portWidth;
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}portConfig;
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typedef struct packed {
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// <typeName> <LogicalName> = {<enablement>, <width>}
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portConfig request_length;
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portConfig response_measured_length;
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}if_do_ctrl_v1_0_port_configuration;
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parameter if_do_ctrl_v1_0_port_configuration if_do_ctrl_v1_0_default_port_configuration = '{request_length:'{1, -1}, response_measured_length:'{1, -1}};
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endpackage
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interface if_do_ctrl_v1_0 #(parameter_structs::if_do_ctrl_v1_0_port_configuration port_configuration)();
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logic request_enable; //
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logic request_valid; //
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logic request_ready; //
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logic [port_configuration.request_length.portWidth-1:0] request_length; //
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logic [port_configuration.response_measured_length.portWidth-1:0] response_measured_length; //
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logic response_eot; //
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logic status_underflow; //
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logic status_overflow; //
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modport MASTER (
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input request_ready, response_eot, status_underflow, status_overflow,
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output request_enable, request_valid, request_length, response_measured_length
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);
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modport SLAVE (
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input request_enable, request_valid, request_length, response_measured_length,
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output request_ready, response_eot, status_underflow, status_overflow
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);
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modport MONITOR (
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input request_enable, request_valid, request_ready, request_length, response_measured_length, response_eot, status_underflow, status_overflow
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);
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endinterface // if_do_ctrl_v1_0
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`endif |