148 lines
3.8 KiB
Verilog
148 lines
3.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/15 20:02:47
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// Design Name:
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// Module Name: ApproxAbs
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ApproxAbs(
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input clk,
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input Nd,
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input [27:0] Dini,
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input [27:0] Dinq,
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output reg Abs_Rdy = 1'b0,
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output reg [28:0] Abs_Dout= 29'd0
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);
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// 第一级延迟：把输入变负值：
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//===============================================================
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reg [27:0] Din_I_neg;
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always @(posedge clk)begin
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if(Dini==28'b1000_0000_0000_0000_0000_0000_0000)begin
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Din_I_neg <= 28'b0111_1111_1111_1111_1111_1111_1111;
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end else begin
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Din_I_neg <= -Dini;
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end
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end
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reg [27:0] Din_Q_neg;
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always @(posedge clk)begin
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if(Dinq==28'b1000_0000_0000_0000_0000_0000_0000)begin
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Din_Q_neg <= 28'b0111_1111_1111_1111_1111_1111_1111;
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end else begin
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Din_Q_neg <= -Dinq;
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end
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end
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// 第二级延迟：求绝对值：
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//===============================================================
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reg [27:0] Din_I_D1;
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reg [27:0] Din_Q_D1;
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always @(posedge clk)begin
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Din_I_D1 <= Dini;
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Din_Q_D1 <= Dinq;
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end
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reg [27:0] Abs_Din_I;
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reg [27:0] Abs_Din_Q;
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always @(posedge clk)begin
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if(Din_I_D1[27]==1'b1)
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Abs_Din_I <= Din_I_neg;
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else
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Abs_Din_I <= Din_I_D1;
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if(Din_Q_D1[27]==1'b1)
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Abs_Din_Q <= Din_Q_neg;
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else
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Abs_Din_Q <= Din_Q_D1;
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end
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// 第三级延迟：确定I/Q两路绝对值的大小关系：
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//===============================================================
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reg [27:0] AbsIQ_max;
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reg [27:0] AbsIQ_min;
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always @(posedge clk)begin
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if (Abs_Din_I>=Abs_Din_Q) begin
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AbsIQ_max <= Abs_Din_I;
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AbsIQ_min <= Abs_Din_Q;
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end else begin
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AbsIQ_max <= Abs_Din_Q;
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AbsIQ_min <= Abs_Din_I;
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end
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end
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// 第四级延迟：MXQ选择的系数：7/8和1/2：
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//===============================================================
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reg [27:0] AbsIQ_max_7by8;
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reg [27:0] AbsIQ_min_1by2;
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always @ (posedge clk) begin
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AbsIQ_max_7by8[27:0] <= AbsIQ_max[27:0]-{3'b000,AbsIQ_max[27:3]};
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AbsIQ_min_1by2[27:0] <= {AbsIQ_min[27],AbsIQ_min[27:1]};
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end
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// 第五级延迟：1bit位扩展求和：
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// (MXQ)中间将最大延迟一个clk赋给 Dout_Temp2,使 Dout_Temp2与 Dout_Temp在同一个clk下进行比较。
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//===============================================================
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reg [28:0] Dout_Temp;
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reg [28:0] Dout_Temp1;
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reg [28:0] Dout_Temp2;
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always @(posedge clk) begin
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Dout_Temp <= {1'b0,AbsIQ_max_7by8[27:0]}+{1'b0,AbsIQ_min_1by2[27:0]};
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Dout_Temp1 <= {1'b0,AbsIQ_max[27:0]};
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Dout_Temp2 <= Dout_Temp1[28:0];
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end
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// (MXQ)第六级延迟：输出求和值与I/Q两路绝对值最大值比较之后的最大值：
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reg [28:0] Dout;
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always @(posedge clk) begin
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if(Dout_Temp[28:0]>=Dout_Temp2[27:0])
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Dout[28:0] <= Dout_Temp[28:0];
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else
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Dout[28:0] <= Dout_Temp2[28:0];
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end
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// 产生Dout_valid，与Din_valid有七级延迟：
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reg Dout_valid_b6;
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reg Dout_valid_b5;
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reg Dout_valid_b4;
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reg Dout_valid_b3;
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reg Dout_valid_b2;
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reg Dout_valid_b1;
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always@(posedge clk) begin //(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
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Dout_valid_b6 <= Nd;
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Dout_valid_b5 <= Dout_valid_b6;
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Dout_valid_b4 <= Dout_valid_b5;
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Dout_valid_b3 <= Dout_valid_b4;
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Dout_valid_b2 <= Dout_valid_b3;
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Dout_valid_b1 <= Dout_valid_b2;
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Abs_Rdy <= Dout_valid_b1;
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end
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always @ (posedge clk) begin
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if(Dout_valid_b1)
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Abs_Dout <= Dout;
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else
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Abs_Dout <= 29'd0;
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end
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endmodule
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