130 lines
3.1 KiB
Verilog
130 lines
3.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020/12/16 14:26:28
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// Design Name:
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// Module Name: ApproxModuli_26bit
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ApproxModuli_26bit(
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input clk,
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input din_valid,
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input [25:0] din_I,
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input [25:0] din_Q,
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output reg dout_valid = 0,
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output reg [25:0] dout = 0
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);
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reg [25:0] din_I_D1 = 0, din_Q_D1 = 0, din_I_D2 = 0, din_Q_D2 = 0;
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reg [25:0] Sub1_s = 0;
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reg [25:0] Xmax = 0, Xmin = 0;
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always @(posedge clk)
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begin
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if(din_valid)
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din_I_D1[25:0] <= (din_I[25]==1'b0)? din_I[25:0]:-din_I[25:0];
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else
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din_I_D1[25:0] <= 26'd0;
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din_I_D2[25:0] <= din_I_D1[25:0];
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if(din_valid)
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din_Q_D1[25:0] <= (din_Q[25]==1'b0)? din_Q[25:0]:-din_Q[25:0];
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else
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din_Q_D1[25:0] <= 26'd0;
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din_Q_D2[25:0] <= din_Q_D1[25:0];
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Sub1_s[25:0] <= din_I_D1[25:0] - din_Q_D1[25:0];
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if(Sub1_s[25])
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Xmax[25:0] <= din_Q_D2[25:0];
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else
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Xmax[25:0] <= din_I_D2[25:0];
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if(Sub1_s[25])
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Xmin[25:0] <= din_I_D2[25:0];
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else
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Xmin[25:0] <= din_Q_D2[25:0];
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end
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reg [25:0] Xmax_D1 = 0, Xmax_31by32 = 0, Xmax_13by16 = 0;
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reg [25:0] Xmin_9by32 = 0, Xmin_19by32 = 0;
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always @(posedge clk)
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begin
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Xmax_D1[25:0] <= Xmax[25:0];
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Xmax_31by32[25:0] <= Xmax[25:0] - {5'd0, Xmax[25:5]};
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Xmax_13by16[25:0] <= Xmax[25:0] - {3'd0, Xmax[25:3]} - {4'd0, Xmax[25:4]};
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Xmin_9by32[25:0] <= {2'd0, Xmin[25:2]} + {5'd0, Xmin[25:5]};
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Xmin_19by32[25:0] <= {1'd0, Xmin[25:1]} + {4'd0, Xmin[25:4]} + {5'd0, Xmin[25:5]};
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end
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reg [25:0] t1 = 0, t2 = 0, t3 = 0;
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always @(posedge clk)
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begin
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t1[25:0] <= Xmax_D1[25:0];
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t2[25:0] <= Xmax_31by32[25:0] + Xmin_9by32[25:0];
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t3[25:0] <= Xmax_13by16[25:0] + Xmin_19by32[25:0];
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end
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reg [25:0] sub2_s = 0;
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reg [25:0] sub3_a = 0, sub3_b = 0, sub3_s = 0;
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reg [25:0] sub3_a_D1 = 0, sub3_b_D1 = 0;
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reg [25:0] t1_D1 = 0, t2_D1 = 0, t3_D1 = 0;
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always @(posedge clk)
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begin
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t1_D1[25:0] <= t1[25:0];
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t2_D1[25:0] <= t2[25:0];
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t3_D1[25:0] <= t3[25:0];
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sub2_s[25:0] <= t1[25:0] - t2[25:0];
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if(sub2_s[25])
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sub3_a[25:0] <= t2_D1[25:0];
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else
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sub3_a[25:0] <= t1_D1[25:0];
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sub3_b[25:0] <= t3_D1[25:0];
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sub3_a_D1[25:0] <= sub3_a[25:0];
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sub3_b_D1[25:0] <= sub3_b[25:0];
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sub3_s[25:0] <= sub3_a[25:0] - sub3_b[25:0];
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if(sub3_s[25])
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dout[25:0] <= sub3_b_D1[25:0];
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else
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dout[25:0] <= sub3_a_D1[25:0];
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end
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reg din_valid_D1 = 0, din_valid_D2 = 0, din_valid_D3 = 0, din_valid_D4 = 0;
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reg din_valid_D5 = 0, din_valid_D6 = 0, din_valid_D7 = 0, din_valid_D8 = 0;
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always @(posedge clk)
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begin
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din_valid_D1 <= din_valid;
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din_valid_D2 <= din_valid_D1;
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din_valid_D3 <= din_valid_D2;
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din_valid_D4 <= din_valid_D3;
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din_valid_D5 <= din_valid_D4;
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din_valid_D6 <= din_valid_D5;
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din_valid_D7 <= din_valid_D6;
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din_valid_D8 <= din_valid_D7;
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dout_valid <= din_valid_D8;
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end
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endmodule
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