860 lines
36 KiB
XML
860 lines
36 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>axi_pulse_gen</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>s_axi</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:slave>
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<spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
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</spirit:slave>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_awaddr</spirit:name>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_awprot</spirit:name>
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<spirit:name>AWVALID</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_awvalid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_awready</spirit:name>
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<spirit:name>WDATA</spirit:name>
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<spirit:name>s_axi_wdata</spirit:name>
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<spirit:name>WVALID</spirit:name>
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<spirit:name>s_axi_wvalid</spirit:name>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_wready</spirit:name>
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<spirit:name>s_axi_bresp</spirit:name>
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<spirit:name>s_axi_bvalid</spirit:name>
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<spirit:name>BREADY</spirit:name>
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<spirit:name>s_axi_bready</spirit:name>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_araddr</spirit:name>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_arprot</spirit:name>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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<spirit:name>s_axi_arvalid</spirit:name>
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<spirit:name>ARREADY</spirit:name>
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<spirit:name>s_axi_arready</spirit:name>
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<spirit:name>RDATA</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rdata</spirit:name>
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<spirit:name>RRESP</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rresp</spirit:name>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_rvalid</spirit:name>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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<spirit:name>s_axi_rready</spirit:name>
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<spirit:name>s_axi_aclk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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<spirit:physicalPort>
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<spirit:name>s_axi_aclk</spirit:name>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:name>s_axi_aresetn</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:language>Verilog</spirit:language>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>s_axi_rvalid</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>s_axi_rresp</spirit:name>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:userFileType>xdc</spirit:userFileType>
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<spirit:displayName>Id</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID">0</spirit:value>
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<spirit:name>ASYNC_CLK_EN</spirit:name>
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<spirit:displayName>ASYNC_CLK_EN</spirit:displayName>
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<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK_EN">true</spirit:value>
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<spirit:name>PULSE_WIDTH</spirit:name>
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<spirit:displayName>Pulse width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
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<spirit:name>PULSE_PERIOD</spirit:name>
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<spirit:displayName>Pulse period</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_pulse_gen_v1_0</spirit:value>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="886aab0b"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="46248f1e"/>
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1e6bc47d"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1ffac0ff"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|