44 lines
829 B
Verilog
44 lines
829 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04/21/2023 11:37:14 AM
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// Design Name:
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// Module Name: truncate_manual
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module truncate_manual
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#(
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DATA_I_WIDTH = 30,
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DATA_O_WIDTH = 12
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)
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(
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input clk,
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input rst,
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input [DATA_I_WIDTH-1 : 0] data_in,
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input data_in_valid,
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input [$clog2(DATA_I_WIDTH)-1 : 0] trunc_pos,
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output [DATA_O_WIDTH-1 : 0] data_out,
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output data_out_valid
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);
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assign data_out = data_in[trunc_pos -: DATA_O_WIDTH];
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endmodule
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