255 lines
11 KiB
XML
255 lines
11 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>util_clkdiv</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>clk_out</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>clk_out</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>clk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>util_clkdiv</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>46f830fd</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>util_clkdiv</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>95c49aa5</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>ce93cd79</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>clk</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>clk_sel</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>clk_out</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
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<spirit:name>SIM_DEVICE</spirit:name>
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<spirit:displayName>Sim Device</spirit:displayName>
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<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SIM_DEVICE">7SERIES</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="string">
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<spirit:name>SEL_0_DIV</spirit:name>
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<spirit:displayName>Sel 0 Div</spirit:displayName>
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<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEL_0_DIV">4</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="string">
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<spirit:name>SEL_1_DIV</spirit:name>
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<spirit:displayName>Sel 1 Div</spirit:displayName>
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<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEL_1_DIV">2</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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</spirit:model>
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<spirit:choices>
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<spirit:choice>
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<spirit:name>choice_list_2fc66e08</spirit:name>
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<spirit:enumeration>1</spirit:enumeration>
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<spirit:enumeration>2</spirit:enumeration>
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<spirit:enumeration>3</spirit:enumeration>
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<spirit:enumeration>4</spirit:enumeration>
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<spirit:enumeration>5</spirit:enumeration>
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<spirit:enumeration>6</spirit:enumeration>
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<spirit:enumeration>7</spirit:enumeration>
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<spirit:enumeration>8</spirit:enumeration>
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</spirit:choice>
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<spirit:choice>
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<spirit:name>choice_list_441fc920</spirit:name>
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<spirit:enumeration>7SERIES</spirit:enumeration>
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<spirit:enumeration>ULTRASCALE</spirit:enumeration>
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</spirit:choice>
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</spirit:choices>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>util_clkdiv_ooc.ttcl</spirit:name>
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<spirit:userFileType>ttcl</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>util_clkdiv_constr.xdc</spirit:name>
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<spirit:userFileType>xdc</spirit:userFileType>
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<spirit:define>
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<spirit:name>processing_order</spirit:name>
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<spirit:value>late</spirit:value>
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</spirit:define>
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</spirit:file>
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<spirit:file>
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<spirit:name>util_clkdiv.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_95c49aa5</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>util_clkdiv.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/util_clkdiv_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_ce93cd79</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
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<spirit:description>util_clkdiv_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>SIM_DEVICE</spirit:name>
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<spirit:displayName>Sim Device</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SIM_DEVICE" spirit:choiceRef="choice_list_441fc920">7SERIES</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SEL_0_DIV</spirit:name>
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<spirit:displayName>Sel 0 Div</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SEL_0_DIV" spirit:choiceRef="choice_list_2fc66e08">4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SEL_1_DIV</spirit:name>
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<spirit:displayName>Sel 1 Div</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SEL_1_DIV" spirit:choiceRef="choice_list_2fc66e08">2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_clkdiv_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>util_clkdiv_v1_0</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2024-06-06T03:15:55Z</xilinx:coreCreationDateTime>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="eb30d391"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="b5c8343e"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0c132cf6"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="253c2293"/>
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</xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>
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