add power mode switch

Makefile

@@ -3,10 +3,8 @@ DIR := $(shell pwd)
 compile_test:
 	cd $(DIR)/datalink814_ge/build && make all
 	cd $(DIR)/datalink814_sp/build && make all
-	cd $(DIR)/df_datalink/build && make all
 
 clean:
 	cd $(DIR)/datalink814_ge/build && make clean
 	cd $(DIR)/datalink814_sp/build && make clean
-	cd $(DIR)/df_datalink/build && make clean
 .PHONY: clean compile_test

README.md

@@ -0,0 +1,10 @@
+# Datalink 814 Projects
+
+## Changelog
+
+### 2023-12-21
+
+* Rewrote node list
+* Rewrote schedule event pool
+* Simplified RTT procedure
+* Adapted to new physical layer implementation (by 牛蒙浩 何广源)

datalink814_ge/src/linklayer/linklayer814.c

@@ -20,21 +20,20 @@
 #include <string.h>
 #include "linklayer814.h"
 #include "linklayer814_types.h"
+#include "node_list.h"
 #include "msg_def.h"
 #include "../error.h"
-#include "../phy_ctrl/phy_ctrlreg.h"
-#include "../time_ctrl/time_ctrl.h"
-#include "../util/util.h"
 #include "../common.h"
+#include "../util/util.h"
+#include "../time_ctrl/time_ctrl.h"
 
 /************************** Constant Definitions *****************************/
 #define NET_START_TIME_INFTY UINT32_MAX
 /************************** Variable Definitions *****************************/
 /***************** Macros (Inline Functions) Definitions *********************/
-
 /**************************** Type Definitions *******************************/
-
 /************************** Function Prototypes ******************************/
+static void L2_RcdShift(L2_RCD *rcd, int32_t netxVal);
 static void UpdateMainSate(L2_INST *instPtr, L2_NODE_STATE newSate);
 static void L2_SetSlotNum(L2_INST *instPtr, uint32_t newSlotNum);
 static void L2_SetFrameNum(L2_INST *instPtr, uint32_t newFrameNum);
@@ -296,6 +295,34 @@ inline void L2_RcdShift(L2_RCD *rcd, int32_t netxVal)
 	rcd->next = netxVal;
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Infer last received frame type.
+ *
+ * @param   instPtr  A pointer to physical layer control instance.
+ *
+ * @return  L2_FRAME_TYPE.
+ *
+ ******************************************************************************/
+L2_FRAME_TYPE L2_GetLastOptFrameType(L2_INST *instPtr)
+{
+	if (instPtr->myInfo.nodeType == L2_NODE_HEAD || L2_isCxn2Net(instPtr))
+	{
+		return instPtr->frame.curr;
+	}
+
+	switch (instPtr->scanFSM->scanStage)
+	{
+	case L2_SCAN_INIT_STAGE:
+	case L2_SCAN_BMADVT_STAGE:
+		return L2_INTRA_BM_FRAME;
+	case L2_SCANT_2WAYACQ_STAGE:
+		return L2_INTRA_W2_ACQ_FRAME;
+	default:
+		return L2_NONE_FRAME;
+	}
+}
+
 /*****************************************************************************/
 /**
  * @brief   Update L2 frame state, check if there is any valid L2 frame data in
@@ -322,7 +349,8 @@ void L2_FrameStateUpdate(L2_INST *instPtr)
 	Phy_RetrieveRecvData(phyRef, instPtr->recvPktData);
 	instPtr->log.frameRecv++;
 
-	switch (instPtr->frame.last)
+	// Update frame state.
+	switch (L2_GetLastOptFrameType(instPtr))
 	{
 	case L2_INTRA_SCAN_FRAME:
 	// INTRA_BM_FRAME could be received if current frame type is INTRA_BM_FRAME
@@ -340,13 +368,13 @@ void L2_FrameStateUpdate(L2_INST *instPtr)
 		}
 		break;
 	case L2_INTRA_W2_ACQ_FRAME:
-		instPtr->log.mgmtRecvCnt++;
+		instPtr->log.w2acqRecvCnt++;
 		if (L2_CrcCheck(instPtr->recvPktData,
 						W2ACQ_FRAME_CRC_DLEN, W2ACQ_FRAME_CRC_POS,
 						L2_CRC16_8005) == true)
 		{
 			L2_DataAvailUpdate(instPtr, true);
-			instPtr->log.mgmtCorrectCnt++;
+			instPtr->log.w2acqCorrectCnt++;
 		}
 		else
 		{
@@ -528,7 +556,7 @@ int32_t L2_SetupNextSlot(L2_INST *instPtr, L2_TOR_TYPE txrxMode, L2_FRAME_TYPE f
 
 	TIME_WORD pullTime = {0, 0};
 	pullTime.int_part = TimeCtrl_GetIntCnt(instPtr->config.tmcInstPtr) + 1;
-	Status = Phy_SetTimeWord(phyRef, &pullTime, TIME_WORD_POLL);
+	Status = Phy_SetTimeWord(phyRef, &pullTime, PHY_TIME_WORD_POLL);
 	if (Status != SUCCESS)
 	{
 		DBG_ERROR("Physical set pull time failed, with error code: %d\n", Status);
@@ -578,12 +606,12 @@ uint32_t L2_GetFrameLen(L2_FRAME_TYPE l2FrameType)
 /**
  * @brief   Convert L2 frame type to L1 frame type
  *
- * @param   phyInstPtr  A pointer to physical layer control instance.
+ * @param   l2Frame
  *
  * @return  L1 frame type.
  *
  ******************************************************************************/
-#ifndef TEST_200KBPS
+#ifdef TEST_200KBPS
 L1_FRAME_TYPE L2_L2frame2L1frame(L2_FRAME_TYPE l2Frame)
 {
 	switch (l2Frame)
@@ -651,12 +679,14 @@ L1_FRAME_TYPE L2_L2frame2L1frame(L2_FRAME_TYPE l2Frame)
 	}
 }
 #endif
+
 /*****************************************************************************/
 /**
  * @brief   Initialize link layer fsm instance, allocate memory to storage fsm
  *          data. Apply the default values to fsm.
  *
  * @param   instPtr	a pointer to physical layer controller instance
+ * @param	config a pointer to configurations
  *
  * @return  SUCCESS
  *          Other error code.
@@ -788,24 +818,24 @@ int32_t Linklayer_Init(L2_INST **instPtr, const L2_CONFIG *config)
 		goto error;
 	}
 
-	Status = ScanNet_Init(&((*instPtr)->scanNetFSM));
+	Status = L2_Scan_Init(&((*instPtr)->scanFSM));
 	if (Status != SUCCESS)
 	{
-		DBG_ERROR("ScanNet_Init runs failed, with error code: %d.\n", Status);
+		DBG_ERROR("L2_Scan_Init runs failed, with error code: %d.\n", Status);
 		goto error;
 	}
 
-	Status = MgmtNet_Init(&((*instPtr)->mgmtNetFSM));
+	Status = L2_Mgmt_Init(&((*instPtr)->mgmtFSM));
 	if (Status != SUCCESS)
 	{
-		DBG_ERROR("MgmtNet_Init runs failed, with error code: %d.\n", Status);
+		DBG_ERROR("L2_Mgmt_Init runs failed, with error code: %d.\n", Status);
 		goto error;
 	}
 
-	Status = ServiceNet_Init(&((*instPtr)->serviceNetFSM));
+	Status = L2_Service_Init(&((*instPtr)->serviceFSM));
 	if (Status != SUCCESS)
 	{
-		DBG_ERROR("ServiceNet_Init runs failed, with error code: %d.\n", Status);
+		DBG_ERROR("L2_Service_Init runs failed, with error code: %d.\n", Status);
 		goto error;
 	}
 
@@ -821,6 +851,18 @@ error:
 	return Status;
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Reconfigure link layer instance, reset all segment and reconfigure
+ * 			accordingly.
+ *
+ * @param   instPtr	a pointer to physical layer controller instance
+ * @param	config a pointer to configurations
+ *
+ * @return  SUCCESS
+ *          Other error code.
+ *
+ ******************************************************************************/
 int32_t Linklayer_Reconfig(L2_INST *instPtr, const L2_CONFIG *config)
 {
 	ASSERT(instPtr != NULL);
@@ -881,13 +923,22 @@ int32_t Linklayer_Reconfig(L2_INST *instPtr, const L2_CONFIG *config)
 	// Reset according instance
 	L2_ClearSchedEventPool(instPtr->schdEventPool);
 	L2_NodeList_Clear(instPtr->nodeList);
-	ScanNet_Reset(instPtr->scanNetFSM);
-	MgmtNet_Reset(instPtr->mgmtNetFSM);
-	ServiceNet_Reset(instPtr->serviceNetFSM);
+	L2_Scan_Reset(instPtr->scanFSM);
+	L2_Mgmt_Reset(instPtr->mgmtFSM);
+	L2_Service_Reset(instPtr->serviceFSM);
 	RTT_Reset(instPtr->rttFSM);
 	return SUCCESS;
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Completely destroy link layer instance, free all allocated memory.
+ *
+ * @param   instPtr	a pointer to physical layer controller instance
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
 void Linklayer_Destroy(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
@@ -900,13 +951,22 @@ void Linklayer_Destroy(L2_INST *instPtr)
 	// Destroy FSMs and nodeList
 	L2_DestroySchedEventPool(instPtr->schdEventPool);
 	L2_NodeList_Destroy(instPtr->nodeList);
-	ScanNet_Destroy(instPtr->scanNetFSM);
-	MgmtNet_Destroy(instPtr->mgmtNetFSM);
-	ServiceNet_Destroy(instPtr->serviceNetFSM);
+	L2_Scan_Destroy(instPtr->scanFSM);
+	L2_Mgmt_Destroy(instPtr->mgmtFSM);
+	L2_Service_Destroy(instPtr->serviceFSM);
 	RTT_Destroy(instPtr->rttFSM);
 	free(instPtr);
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Start link layer processing.
+ *
+ * @param   instPtr	a pointer to physical layer controller instance
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
 int32_t Linklayer_Start(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
@@ -915,6 +975,15 @@ int32_t Linklayer_Start(L2_INST *instPtr)
 	return SUCCESS;
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Halt link layer.
+ *
+ * @param   instPtr	a pointer to physical layer controller instance
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
 int32_t Linklayer_Halt(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
@@ -961,11 +1030,6 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
 		// TODO: Clear ACK
 		break;
 	}
-	case L2_EV_MGMT_PROC_DONE:
-	{
-		DBG_INFO("Event L2_EV_MGMT_PROC_DONE asserted....\n");
-		break;
-	}
 	case L2_EV_NET_SETUP_DONE:
 	{
 		DBG_INFO("Event L2_EV_NETSETUP_DONE asserted....\n");
@@ -997,8 +1061,17 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
 	case L2_EV_LOST_CXN:
 	{
 		DBG_INFO("Event L2_EV_LOST_CXN asserted....\n");
+		if (instPtr->config.myType == L2_NODE_HEAD)
+		{
+			DBG_ERROR("Illegal event, only None_Head node can assert L2_EV_LOST_CXN.\n");
+			break;
+		}
 		DBG_WARNING("Lost connection with head node [%d].\n", L2_GetHeadId(instPtr));
+		L2_Scan_Reset(instPtr->scanFSM);
+		L2_Mgmt_Reset(instPtr->mgmtFSM);
+		L2_Service_Reset(instPtr->serviceFSM);
 		instPtr->cxn2Net = false;
+		UpdateMainSate(instPtr, L2_INIT_STATE);
 		break;
 	}
 	case L2_EV_LOST_NODE:
@@ -1012,8 +1085,8 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
 		if (instPtr->nextState == L2_INIT_STATE)
 		{
 			// Reset scan net FMS for next scan process.
-			ScanNet_Reset(instPtr->scanNetFSM);
-			UpdateMainSate(instPtr, L2_NORMAL_STATE);
+			L2_Scan_Reset(instPtr->scanFSM);
+			UpdateMainSate(instPtr, L2_INIT_STATE);
 			instPtr->rtneConfig.rtneTable = normalTable;
 			instPtr->rtneConfig.rtnePrd = ARRAY_SIZE(normalTable);
 		}
@@ -1037,6 +1110,10 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
 			instPtr->rtneConfig.rtneTable = interSeekTable;
 			instPtr->rtneConfig.rtnePrd = ARRAY_SIZE(interSeekTable);
 		}
+		else
+		{
+			DBG_WARNING("Unsupported routine state [%d], Continue withe previous routine table.\n", instPtr->nextState);
+		}
 		break;
 	}
 	case L2_ROUTINE_UPDATE:
@@ -1066,12 +1143,10 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
  * @return  Status code.
  *
  ******************************************************************************/
-int mgmtFrameRecv = 0;
-int svcFrameRecv = 0;
 int32_t Linklayer_PktHandler(L2_INST *instPtr, L2_FRAME_TYPE frameType)
 {
 	ASSERT(instPtr != NULL);
-	int32_t Status = SUCCESS;
+	int32_t Status;
 
 	if (instPtr->dataAvail == false)
 	{
@@ -1086,7 +1161,7 @@ int32_t Linklayer_PktHandler(L2_INST *instPtr, L2_FRAME_TYPE frameType)
 	case L2_INTRA_BM_FRAME:
 	case L2_INTER_W2_ACQ_FRAME:
 	case L2_INTRA_W2_ACQ_FRAME:
-		Status = ScanNet_PktHandler(instPtr);
+		Status = L2_Scan_PktHandler(instPtr);
 		break;
 	case L2_INTER_MGMT_FRAME:
 	case L2_INTRA_MGMT_FRAME:
@@ -1107,8 +1182,7 @@ int32_t Linklayer_PktHandler(L2_INST *instPtr, L2_FRAME_TYPE frameType)
 				instPtr->mgmtMsgRecvCnt1++;
 			}
 		}
-		mgmtFrameRecv++;
-		Status = MgmtNet_PktHandler(instPtr);
+		Status = L2_Mgmt_PktHandler(instPtr);
 		break;
 	case L2_INTER_SVC_FRAME:
 	case L2_INTRA_SVC_FRAME:
@@ -1127,8 +1201,7 @@ int32_t Linklayer_PktHandler(L2_INST *instPtr, L2_FRAME_TYPE frameType)
 				instPtr->svcMsgRecvCnt1++;
 			}
 		}
-		svcFrameRecv++;
-		Status = ServiceNet_PktHandler(instPtr);
+		Status = L2_Service_PktHandler(instPtr);
 		break;
 	default:
 		DBG_WARNING("L2FrameHandler: UNKNOWN L2-FrameType %d\n", frameType);
@@ -1154,15 +1227,6 @@ static int32_t Linklayer_Routine(L2_INST *instPtr)
 	int32_t Status;
 	uint32_t tableIndx, entryIndx;
 
-	// FIXME: Consider time wrapping.
-	uint32_t nextTimeUnit = (TimeCtrl_GetIntCnt(instPtr->config.tmcInstPtr) + 1) / L2_SLOTS_PER_FRAME;
-	if (nextTimeUnit < instPtr->netStartTime)
-	{
-		DBG_WARNING("Linklayer not start yet, next time unit: %u, start time unit: %u.\n",
-					nextTimeUnit, instPtr->netStartTime);
-		return EIGNORE;
-	}
-
 	// Determine which routine entry is going to be performed.
 	tableIndx = L2_GetNextFrameNum(instPtr) % instPtr->rtneConfig.rtnePrd;
 	entryIndx = L2_GetNextSlotNum(instPtr);
@@ -1188,17 +1252,17 @@ static int32_t Linklayer_Routine(L2_INST *instPtr)
 	case L2_SLOT_INTRA_SCAN_BM:
 	case L2_SLOT_INTER_SCAN_2W:
 	case L2_SLOT_INTRA_SCAN_2W:
-		Status = ScanNet_Routine(instPtr, &rtneEntry);
+		Status = L2_Scan_Routine(instPtr, &rtneEntry);
 		break;
 	case L2_SLOT_INTER_SVC:
 	case L2_SLOT_INTRA_SVC:
-		Status = ServiceNet_Routine(instPtr, &rtneEntry);
+		Status = L2_Service_Routine(instPtr, &rtneEntry);
 		break;
 	case L2_SLOT_INTER_MGMT:
 	case L2_SLOT_INTRA_MGMT:
 	case L2_SLOT_INTER_TSYNC:
 	case L2_SLOT_INTRA_TSYNC:
-		Status = MgmtNet_Routine(instPtr, &rtneEntry);
+		Status = L2_Mgmt_Routine(instPtr, &rtneEntry);
 		break;
 	default:
 		DBG_ERROR("UNKNOWN slot type [%d].\n", rtneEntry.slotType);
@@ -1244,6 +1308,15 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 		return SUCCESS;
 	}
 
+	// FIXME: Consider time wrapping.
+	uint32_t nextTimeUnit = (TimeCtrl_GetIntCnt(instPtr->config.tmcInstPtr) + 1) / L2_SLOTS_PER_FRAME;
+	if (nextTimeUnit < instPtr->netStartTime)
+	{
+		DBG_WARNING("Linklayer not start yet, next time unit: %u, start time unit: %u.\n",
+					nextTimeUnit, instPtr->netStartTime);
+		return EIGNORE;
+	}
+
 	// Update slot number.
 	L2_UpdateSlotNum(instPtr);
 
@@ -1256,7 +1329,10 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 	// Handle frame received in last slot.
 	if (L2_isDataAvail(instPtr) == true)
 	{
-		Linklayer_PktHandler(instPtr, L2_GetLastFrameType(instPtr));
+		if (Linklayer_PktHandler(instPtr, L2_GetLastOptFrameType(instPtr)) != SUCCESS)
+		{
+			DBG_ERROR("Failed to handle last received frame: %d.\n", instPtr->frame.last);
+		}
 	}
 
 	// Run Link layer routine, setup next slot procedure.
@@ -1275,9 +1351,10 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 		else
 		{
 			Phy_SetMode(instPtr->config.phyInstPtr, PHY_MODE_LISTEN);
-			Status = ScanNet_Proc(instPtr);
+			Status = L2_Scan_Proc(instPtr);
 		}
 	}
+	
 	// Check if previous runs has error occurred.
 	if (Status != SUCCESS)
 	{

datalink814_ge/src/linklayer/linklayer814.h

@@ -53,7 +53,7 @@ typedef struct
 	uint8_t bkpHeadId;
 	uint8_t netScale;
 	PHY_INST *phyInstPtr;
-	TIMECTRL_INST *tmcInstPtr;
+	TMC_INST *tmcInstPtr;
 } L2_CONFIG;
 
 typedef struct
@@ -106,9 +106,9 @@ typedef struct
 	L2_NODE_STATE mainState;   // the main state of link layer state
 	L2_NODE_STATE nextState;   // next state of link layer state, which will be applied to mainState every second.
 	L2_RTNE_CONFIG rtneConfig; // current routine table configuration and status.
-	L2_SCAN_FSM *scanNetFSM;   // FSM of scan net (link set up)
-	L2_MGMT_FSM *mgmtNetFSM;   // FSM of management net (link management and time sync)
-	L2_SVC_FSM *serviceNetFSM; // FSM of service net (data service)
+	L2_SCAN_FSM *scanFSM;   // FSM of scan net (link set up)
+	L2_MGMT_FSM *mgmtFSM;   // FSM of management net (link management and time sync)
+	L2_SVC_FSM *serviceFSM; // FSM of service net (data service)
 	L2_RTT_FSM *rttFSM;		   // FSM for RTT (time sync algorithm)
 	uint8_t *sendPktData;
 	uint8_t *recvPktData;
@@ -152,7 +152,7 @@ int32_t L2_RescheduleEventAfter(L2_INST *instPtr, L2_SCHD_EVENT *schdEvent, uint
 
 // Framing
 void L2_FrameStateUpdate(L2_INST *instPtr);
-L2_FRAME_TYPE L2_GetLastRcvFrameType(L2_INST *instPtr);
+L2_FRAME_TYPE L2_GetLastOptFrameType(L2_INST *instPtr);
 L1_FRAME_TYPE L2_L2frame2L1frame(L2_FRAME_TYPE l2Frame);
 void FrameGetChunk(BIT_ARRAY *bitarr, uint32_t offset, uint32_t numBit, uint64_t *chunk);
 void FrameInsertChunk(BIT_ARRAY *bitarr, uint32_t offset, uint32_t numBit, uint64_t chunck);
@@ -160,26 +160,26 @@ int32_t L2_CrcAppend(uint8_t *dataBuff, uint32_t dataLen, uint32_t crcPos, L2_CR
 bool L2_CrcCheck(uint8_t *dataBuff, uint32_t dataLen, uint32_t crcPos, L2_CRC_TYPE crcType);
 
 // Scan Net
-int32_t ScanNet_Init(L2_SCAN_FSM **scanFSMPtr);
-void ScanNet_Reset(L2_SCAN_FSM *scanFSMPtr);
-void ScanNet_Destroy(L2_SCAN_FSM *scanFSMPtr);
-int32_t ScanNet_Proc(L2_INST *instPtr);
-int32_t ScanNet_PktHandler(L2_INST *instPtr);
-int32_t ScanNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry);
+int32_t L2_Scan_Init(L2_SCAN_FSM **scanFSMPtr);
+void L2_Scan_Reset(L2_SCAN_FSM *scanFSMPtr);
+void L2_Scan_Destroy(L2_SCAN_FSM *scanFSMPtr);
+int32_t L2_Scan_Proc(L2_INST *instPtr);
+int32_t L2_Scan_PktHandler(L2_INST *instPtr);
+int32_t L2_Scan_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry);
 
 // Management Net
-int32_t MgmtNet_Init(L2_MGMT_FSM **mgmtFSM);
-void MgmtNet_Reset(L2_MGMT_FSM *mgmtFSM);
-void MgmtNet_Destroy(L2_MGMT_FSM *mgmtFSM);
-int32_t MgmtNet_PktHandler(L2_INST *instPtr);
-int32_t MgmtNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry);
+int32_t L2_Mgmt_Init(L2_MGMT_FSM **mgmtFSM);
+void L2_Mgmt_Reset(L2_MGMT_FSM *mgmtFSM);
+void L2_Mgmt_Destroy(L2_MGMT_FSM *mgmtFSM);
+int32_t L2_Mgmt_PktHandler(L2_INST *instPtr);
+int32_t L2_Mgmt_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry);
 
 // Service net
-int32_t ServiceNet_Init(L2_SVC_FSM **serviceFSM);
-void ServiceNet_Reset(L2_SVC_FSM *serviceFSM);
-void ServiceNet_Destroy(L2_SVC_FSM *serviceFSM);
-int32_t ServiceNet_PktHandler(L2_INST *instPtr);
-int32_t ServiceNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *schedEntry);
+int32_t L2_Service_Init(L2_SVC_FSM **serviceFSM);
+void L2_Service_Reset(L2_SVC_FSM *serviceFSM);
+void L2_Service_Destroy(L2_SVC_FSM *serviceFSM);
+int32_t L2_Service_PktHandler(L2_INST *instPtr);
+int32_t L2_Service_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *schedEntry);
 
 // Miscellaneous
 uint8_t L2_GetNodeId(L2_INST *instPtr);
@@ -190,7 +190,6 @@ L2_NODE_STATE L2_GetMainState(L2_INST *instPtr);
 L2_RTT_FSM *L2_GetRttFsm(L2_INST *instPtr);
 bool L2_isDataAvail(L2_INST *instPtr);
 bool L2_isCxn2Net(L2_INST *instPtr);
-void L2_RcdShift(L2_RCD *rcd, int32_t netxVal);
 uint32_t L2_GetFrameLen(L2_FRAME_TYPE l2FrameType);
 uint32_t L2_GetLastFrameNum(L2_INST *instPtr);
 uint32_t L2_GetLastSlotNum(L2_INST *instPtr);

datalink814_ge/src/linklayer/linklayer814_types.h

@@ -19,8 +19,9 @@
 
 /***************************** Include Files *********************************/
 #include <stdbool.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include "geometry/coord.h"
+#include "geometry/quaternion.h"
 #include "../phy_ctrl/phy_ctrl.h"
 /************************** Constant Definitions *****************************/
 // Common node ID definition
@@ -46,6 +47,7 @@
 #define L2_SLOTS_PER_SUBFRAME 20
 
 #define L2_NUM_SLOTS_NONE UINT32_MAX
+#define L2_NUM_SLOTS_100MS 20
 #define L2_NUM_SLOTS_20MS 4
 #define L2_NUM_SLOTS_10MS 2
 #define L2_NUM_SLOTS_5MS 1
@@ -91,6 +93,9 @@ typedef enum
 	L2_SEEK_STATE = 5
 } L2_NODE_STATE;
 
+/** @name Node information type definition
+ * The following types define the detail node info which needed by the link layer.
+ */
 typedef struct
 {
 	uint8_t nodeId;
@@ -100,6 +105,7 @@ typedef struct
 	uint8_t beamNo;
 	COORD pos;
 	COORD speed;
+	QUATERNION attitude;
 } L2_NODE_INFO;
 
 /** @name L2 event enum
@@ -109,18 +115,17 @@ typedef enum
 {
 	L2_EV_NONE = 0,
 	L2_EV_SCAN_PROC_DONE = 1,
-	L2_EV_MGMT_PROC_DONE = 2,
-	L2_EV_NET_SETUP_DONE = 3,
-	L2_EV_TIME_SYNC = 4,
-	L2_EV_RTT_RECV_UPDATE = 5,
-	L2_EV_LINK_SET_REQ = 6,
-	L2_EV_LOST_CXN = 7,
-	L2_EV_LOST_NODE = 8,
-	L2_EV_SET_FRAME_NUM = 9,
-	L2_EV_SET_SLOT_NUM = 10,
-	L2_EV_MAIN_STATE_UPDATE = 11,
-	L2_ROUTINE_FINISH = 12,
-	L2_ROUTINE_UPDATE = 13
+	L2_EV_NET_SETUP_DONE = 2,
+	L2_EV_TIME_SYNC = 3,
+	L2_EV_RTT_RECV_UPDATE = 4,
+	L2_EV_LINK_SET_REQ = 5,
+	L2_EV_LOST_CXN = 6,
+	L2_EV_LOST_NODE = 7,
+	L2_EV_SET_FRAME_NUM = 8,
+	L2_EV_SET_SLOT_NUM = 9,
+	L2_EV_MAIN_STATE_UPDATE = 10,
+	L2_ROUTINE_FINISH = 11,
+	L2_ROUTINE_UPDATE = 12
 } L2_EVENT_TYPE;
 
 /** @name L2 event
@@ -153,17 +158,6 @@ typedef enum
 	L2_SLOT_INTRA_TSYNC = 13,
 } L2_SLOT_TYPE;
 
-/** @name Frame types
- * A definition of different frame types.
- */
-typedef enum
-{
-	L2_CRC_NONE = 0,
-	L2_CRC16_1021 = 1,
-	L2_CRC16_8005 = 2,
-	L2_CRC8_31 = 3
-} L2_CRC_TYPE;
-
 /** @name Frame types
  * A definition of different frame types.
  */
@@ -184,6 +178,17 @@ typedef enum
 	L2_INTRA_SVC_FRAME = 12
 } L2_FRAME_TYPE;
 
+/** @name Frame types
+ * A definition of different frame types.
+ */
+typedef enum
+{
+	L2_CRC_NONE = 0,
+	L2_CRC16_1021 = 1,
+	L2_CRC16_8005 = 2,
+	L2_CRC8_31 = 3
+} L2_CRC_TYPE;
+
 /** @name Schedule subtable entry
  * A definition of Schedule subtable entry.
  */
@@ -244,7 +249,7 @@ typedef enum
 typedef struct
 {
 	bool isLocked;	// init acq done.
-	bool isBmRcved; // bm received.
+	bool isBmRecvd; // bm received.
 	bool isAcked;	// 2way acq done.
 	uint32_t scanCnt;
 	uint32_t bmTimeout;

datalink814_ge/src/linklayer/net_mgmt.c

@@ -550,14 +550,14 @@ failed:
  *          EALLOC Memory allocation error.
  *
  ******************************************************************************/
-int32_t MgmtNet_Init(L2_MGMT_FSM **mgmtFSM)
+int32_t L2_Mgmt_Init(L2_MGMT_FSM **mgmtFSM)
 {
 	(*mgmtFSM) = (L2_MGMT_FSM *)malloc(sizeof(L2_MGMT_FSM));
 	if (*mgmtFSM == NULL)
 	{
 		return EALLOC;
 	}
-	MgmtNet_Reset(*mgmtFSM);
+	L2_Mgmt_Reset(*mgmtFSM);
 	return SUCCESS;
 }
 
@@ -570,7 +570,7 @@ int32_t MgmtNet_Init(L2_MGMT_FSM **mgmtFSM)
  * @return	NONE
  *
  ******************************************************************************/
-void MgmtNet_Reset(L2_MGMT_FSM *mgmtFSM)
+void L2_Mgmt_Reset(L2_MGMT_FSM *mgmtFSM)
 {
 	mgmtFSM->isBisarProc = false;
 	mgmtFSM->isPendSlotAlloc = false;
@@ -607,7 +607,7 @@ void MgmtNet_Reset(L2_MGMT_FSM *mgmtFSM)
  * @return	NONE
  *
  ******************************************************************************/
-void MgmtNet_Destroy(L2_MGMT_FSM *mgmtFSM)
+void L2_Mgmt_Destroy(L2_MGMT_FSM *mgmtFSM)
 {
 	free(mgmtFSM);
 }
@@ -623,15 +623,15 @@ void MgmtNet_Destroy(L2_MGMT_FSM *mgmtFSM)
  *          Other Packed was dumped(not addressed to me, unrecognized frame type)
  *
  ******************************************************************************/
-int32_t MgmtNet_PktHandler(L2_INST *instPtr)
+int32_t L2_Mgmt_PktHandler(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	int32_t Status;
 	uint32_t filedSize = 0;
 	uint64_t dataChunk = 0;
-	L2_MGMT_MSG_RECORD *mgmtMsgLog = &(instPtr->mgmtNetFSM->mgmtMsgLog);
-	L2_RTT_MSG_RECORD *rttMsgRspLog = &(instPtr->mgmtNetFSM->rttMsgRspLog);
-	L2_RTT_MSG_RECORD *rttMsgReqLog = &(instPtr->mgmtNetFSM->rttMsgReqLog);
+	L2_MGMT_MSG_RECORD *mgmtMsgLog = &(instPtr->mgmtFSM->mgmtMsgLog);
+	L2_RTT_MSG_RECORD *rttMsgRspLog = &(instPtr->mgmtFSM->rttMsgRspLog);
+	L2_RTT_MSG_RECORD *rttMsgReqLog = &(instPtr->mgmtFSM->rttMsgReqLog);
 
 	DBG_INFO("Management net handling packet...\n");
 
@@ -641,7 +641,7 @@ int32_t MgmtNet_PktHandler(L2_INST *instPtr)
 		DBG_INFO("Failed to start handling process...\n");
 		return EALLOC;
 	}
-	switch (L2_GetLastFrameType(instPtr))
+	switch (L2_GetLastOptFrameType(instPtr))
 	{
 	case L2_INTER_MGMT_FRAME:
 	case L2_INTRA_MGMT_FRAME:
@@ -936,7 +936,7 @@ static bool IsTTLValid(NODE_ENTRY *entry)
  * @return  Slot has be used.
  *
  ******************************************************************************/
-int32_t MgmtNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
+int32_t L2_Mgmt_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 {
 	ASSERT(instPtr != NULL);
 	int32_t Status;
@@ -1043,13 +1043,12 @@ int32_t MgmtNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 		L2_EVENT stateEvent = {
 			.event = L2_EV_MAIN_STATE_UPDATE,
 			.msg = &newState};
-		if (L2_GetNodeListLen(instPtr->nodeList) < instPtr->config.netScale && L2_GetMainState(instPtr) != L2_INTRA_SEEK_STATE)
+		if (L2_GetNodeListLen(instPtr->nodeList) < instPtr->config.netScale - 1)
 		{
 			newState = L2_INTRA_SEEK_STATE;
 			AssertL2Event(instPtr, &stateEvent);
 		}
-		else if (L2_GetNodeListLen(instPtr->nodeList) >= instPtr->config.netScale &&
-				 L2_GetMainState(instPtr) != L2_NORMAL_STATE)
+		else
 		{
 			newState = L2_NORMAL_STATE;
 			AssertL2Event(instPtr, &stateEvent);

datalink814_ge/src/linklayer/net_scan.c

@@ -27,12 +27,7 @@
 #include "../bit_array/bit_macros.h"
 
 /************************** Constant Definitions *****************************/
-#define INIT_BEAM_NO 0
-#define BEAM_PER_ANT 37
-#define INIT_ANT_NO 0
-#define ANT_NUM 6
-
-#define BM_LSTEN_TIMEOUT 40
+#define BM_LISTEN_TIMEOUT 40
 
 #define SQUENCE_SCAN_SLOTS 0
 
@@ -93,8 +88,8 @@ static void BmrecvStateUpdate(L2_SCAN_FSM *scanFsmPtr, bool state)
 {
 	ASSERT(scanFsmPtr != NULL);
 	DBG_INFO("Update BmRecvState from [%d] to [%d].\n",
-			 scanFsmPtr->isBmRcved, state);
-	scanFsmPtr->isBmRcved = state;
+			 scanFsmPtr->isBmRecvd, state);
+	scanFsmPtr->isBmRecvd = state;
 	return;
 }
 
@@ -445,7 +440,7 @@ failed:
 static int32_t Scan_InitScanHandler(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
-	L2_SCAN_FSM *scanFsmPtr = instPtr->scanNetFSM;
+	L2_SCAN_FSM *scanFsmPtr = instPtr->scanFSM;
 	DBG_INFO("** Netsetup - InitScan Procedure (Attempts: %u)**\n", scanFsmPtr->scanCnt);
 
 	if (scanFsmPtr->scanMode == L2_SCAN_INTRA_MODE)
@@ -499,11 +494,11 @@ static int32_t Scan_InitScanHandler(L2_INST *instPtr)
  ******************************************************************************/
 static int32_t Scan_BmAdvtHandler(L2_INST *instPtr)
 {
-	L2_SCAN_FSM *scanFsmPtr = instPtr->scanNetFSM;
+	L2_SCAN_FSM *scanFsmPtr = instPtr->scanFSM;
 	DBG_INFO("** Netsetup - BmAdvt Procedure (Timeout: %u) **\n", scanFsmPtr->bmTimeout);
 
 	// if received a valid bm frame.
-	if (scanFsmPtr->isBmRcved == true)
+	if (scanFsmPtr->isBmRecvd == true)
 	{
 		scanFsmPtr->bmTimeout = 0; /* reset listen counter. */
 		DBG_INFO("Received Bm frame, skipping 10ms for turn around...\n");
@@ -515,7 +510,7 @@ static int32_t Scan_BmAdvtHandler(L2_INST *instPtr)
 	else
 	{
 		/* if time out reached, go back to init scan stage. */
-		if (scanFsmPtr->bmTimeout > BM_LSTEN_TIMEOUT)
+		if (scanFsmPtr->bmTimeout > BM_LISTEN_TIMEOUT)
 		{
 			if (scanFsmPtr->scanMode == L2_SCAN_INTRA_MODE)
 			{
@@ -533,8 +528,7 @@ static int32_t Scan_BmAdvtHandler(L2_INST *instPtr)
 				return FAILURE;
 			}
 			DBG_WARNING("BM timeout, restart net scan from L2_SCAN_INIT_STAGE.\n");
-			scanFsmPtr->bmTimeout = 0; /* reset listen counter. */
-			StageUpdate(scanFsmPtr, L2_SCAN_INIT_STAGE);
+			L2_Scan_Reset(scanFsmPtr);
 		}
 		else
 		{
@@ -570,7 +564,7 @@ static int32_t Scan_BmAdvtHandler(L2_INST *instPtr)
  ******************************************************************************/
 static int32_t Scan_2WAcqHandler(L2_INST *instPtr)
 {
-	L2_SCAN_FSM *scanFsmPtr = instPtr->scanNetFSM;
+	L2_SCAN_FSM *scanFsmPtr = instPtr->scanFSM;
 	DBG_INFO("** Netsetup - 2WAcq Procedure (Timeout: %u) **\n", scanFsmPtr->w2acqTimeout);
 	L2_FRAME_TYPE frameType = L2_NONE_FRAME;
 
@@ -592,8 +586,7 @@ static int32_t Scan_2WAcqHandler(L2_INST *instPtr)
 	if (scanFsmPtr->w2acqTimeout >= WAY2_ACQ_SLOT_MAX)
 	{
 		DBG_WARNING("2WAcq timeout, restart net scan from L2_SCAN_INIT_STAGE.\n");
-		scanFsmPtr->w2acqTimeout = 0; // reset counter for next scan.
-		StageUpdate(scanFsmPtr, L2_SCAN_INIT_STAGE);
+		L2_Scan_Reset(scanFsmPtr);
 	}
 	else
 	{
@@ -617,11 +610,11 @@ static int32_t Scan_2WAcqHandler(L2_INST *instPtr)
  * 			error code
  *
  ******************************************************************************/
-int32_t ScanNet_PktHandler(L2_INST *instPtr)
+int32_t L2_Scan_PktHandler(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	uint32_t Status;
-	L2_SCAN_FSM *scanFsmPtr = instPtr->scanNetFSM;
+	L2_SCAN_FSM *scanFsmPtr = instPtr->scanFSM;
 	uint64_t dataChunk;
 
 	DBG_INFO("Scan net handling packet...\n");
@@ -632,7 +625,7 @@ int32_t ScanNet_PktHandler(L2_INST *instPtr)
 		DBG_INFO("Failed to start handling process...\n");
 		return EALLOC;
 	}
-	switch (L2_GetLastFrameType(instPtr))
+	switch (L2_GetLastOptFrameType(instPtr))
 	{
 	case L2_INTER_SCAN_FRAME:
 	case L2_INTRA_SCAN_FRAME:
@@ -872,7 +865,7 @@ failed:
  *          EMAC_MEMORY_ALLOC_ERROR Memory allocate error.
  *
  ******************************************************************************/
-int32_t ScanNet_Init(L2_SCAN_FSM **scanFSMPtr)
+int32_t L2_Scan_Init(L2_SCAN_FSM **scanFSMPtr)
 {
 	*scanFSMPtr = (L2_SCAN_FSM *)malloc(sizeof(L2_SCAN_FSM));
 	if (*scanFSMPtr == NULL)
@@ -880,7 +873,7 @@ int32_t ScanNet_Init(L2_SCAN_FSM **scanFSMPtr)
 		DBG_ERROR("Failed to allocate memory for scanFsmPtr.\n");
 		return EALLOC;
 	}
-	ScanNet_Reset(*scanFSMPtr);
+	L2_Scan_Reset(*scanFSMPtr);
 	return (SUCCESS);
 }
 
@@ -893,11 +886,11 @@ int32_t ScanNet_Init(L2_SCAN_FSM **scanFSMPtr)
  * @return  NONE
  *
  ******************************************************************************/
-void ScanNet_Reset(L2_SCAN_FSM *scanFSMPtr)
+void L2_Scan_Reset(L2_SCAN_FSM *scanFSMPtr)
 {
 	ASSERT(scanFSMPtr != NULL);
 	scanFSMPtr->isLocked = false;
-	scanFSMPtr->isBmRcved = false;
+	scanFSMPtr->isBmRecvd = false;
 	scanFSMPtr->isAcked = false;
 	scanFSMPtr->scanCnt = 0;
 	scanFSMPtr->bmTimeout = 0;
@@ -931,7 +924,7 @@ void ScanNet_Reset(L2_SCAN_FSM *scanFSMPtr)
  * @return  NONE
  *
  ******************************************************************************/
-void ScanNet_Destroy(L2_SCAN_FSM *scanFSMPtr)
+void L2_Scan_Destroy(L2_SCAN_FSM *scanFSMPtr)
 {
 	free(scanFSMPtr);
 }
@@ -945,12 +938,12 @@ void ScanNet_Destroy(L2_SCAN_FSM *scanFSMPtr)
  * @return  used slot (5ms slot).
  *
  ******************************************************************************/
-int32_t ScanNet_Proc(L2_INST *instPtr)
+int32_t L2_Scan_Proc(L2_INST *instPtr)
 {
-	L2_SCAN_FSM *scanFsmPtr = instPtr->scanNetFSM;
+	L2_SCAN_FSM *scanFsmPtr = instPtr->scanFSM;
 	if (L2_GetNodeType(instPtr) == L2_NODE_HEAD)
 	{
-		DBG_ERROR("Only member node needs to execute ScanNet_Proc. \n");
+		DBG_ERROR("Only member node needs to execute L2_Scan_Proc. \n");
 		return FAILURE;
 	}
 	int32_t Status;
@@ -990,7 +983,7 @@ int32_t ScanNet_Proc(L2_INST *instPtr)
  *
  ******************************************************************************/
 int acqSend = 0;
-int32_t ScanNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
+int32_t L2_Scan_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 {
 	ASSERT(instPtr != NULL);
 	L2_TOR_TYPE torState;
@@ -1072,7 +1065,7 @@ int32_t ScanNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 			}
 		}
 		/* Antenna setting (reserved.) */
-		L2_SetupNextSlot(instPtr, L2_TOR_TX, L2_INTRA_BM_FRAME);
+		L2_SetupNextSlot(instPtr, torState, L2_INTRA_BM_FRAME);
 		break;
 	case L2_SLOT_INTER_SCAN_2W:
 		// TODO:
@@ -1094,7 +1087,7 @@ int32_t ScanNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 				Status = FAILURE;
 				goto routine_err;
 			}
-			W2ackStateUpdate(instPtr->scanNetFSM, true);
+			W2ackStateUpdate(instPtr->scanFSM, true);
 			acqSend++;
 		}
 		/* Antenna setting (reserved.) */

datalink814_ge/src/linklayer/net_service.c

@@ -179,25 +179,45 @@ static int PduHeader_Packing(L2_INST *instPtr, BIT_ARRAY *bitarr, L2_PDU_HEADER_
  *          Other       Initialize failed.
  *
  ******************************************************************************/
-int32_t ServiceNet_Init(L2_SVC_FSM **serviceFSM)
+int32_t L2_Service_Init(L2_SVC_FSM **serviceFSM)
 {
-	(*serviceFSM) = (L2_SVC_FSM *)malloc(sizeof(L2_SVC_FSM));
+	*serviceFSM = (L2_SVC_FSM *)malloc(sizeof(L2_SVC_FSM));
 	if (*serviceFSM == NULL)
 	{
 		return EALLOC;
 	}
-	ServiceNet_Reset(*serviceFSM);
+	L2_Service_Reset(*serviceFSM);
 	return SUCCESS;
 }
 
-void ServiceNet_Reset(L2_SVC_FSM *serviceFSM)
+/*****************************************************************************/
+/**
+ * @brief  Reset ServiceNet FSM
+ *
+ * @param   scanFsmPtr a pointer to service net finite state machine
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void L2_Service_Reset(L2_SVC_FSM *serviceFSM)
 {
+	ASSERT(serviceFSM != NULL);
 	serviceFSM->isBisar = false;
 	serviceFSM->isBisarEven = false;
 	serviceFSM->bisarDst = L2_NONE_ID;
 }
 
-void ServiceNet_Destroy(L2_SVC_FSM *serviceFSM)
+
+/*****************************************************************************/
+/**
+ * @brief  Destroy ServiceNet FSM, free memory
+ *
+ * @param   scanFsmPtr a pointer to service net finite state machine
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void L2_Service_Destroy(L2_SVC_FSM *serviceFSM)
 {
 	free(serviceFSM);
 }
@@ -211,7 +231,7 @@ void ServiceNet_Destroy(L2_SVC_FSM *serviceFSM)
  *          other       error occurred.
  *
  ******************************************************************************/
-int32_t ServiceNet_PktHandler(L2_INST *instPtr)
+int32_t L2_Service_PktHandler(L2_INST *instPtr)
 {
 	// TODO:
 	DBG_INFO("Scan net handling packet...\n");
@@ -229,7 +249,7 @@ int32_t ServiceNet_PktHandler(L2_INST *instPtr)
  * @return  Slot has been used.
  *
  ******************************************************************************/
-int32_t ServiceNet_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
+int32_t L2_Service_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 {
 	ASSERT(instPtr != NULL);
 	int32_t Status;

datalink814_ge/src/linklayer/node_list.c

@@ -21,7 +21,7 @@
 #include <stdbool.h>
 #include "linklayer814_types.h"
 #include "node_list.h"
-#include "../util/list.h"
+#include "../util/clist.h"
 #include "../common.h"
 #include "../error.h"
 
@@ -79,7 +79,7 @@ static int8_t entry_compare(void *a, void *b)
  ******************************************************************************/
 int32_t L2_NodeList_Init(NODE_LIST **list)
 {
-	(*list) = list_new();
+	(*list) = clist_new();
 	if (*list == NULL)
 	{
 		return ENOMEM;
@@ -100,7 +100,7 @@ int32_t L2_NodeList_Init(NODE_LIST **list)
 void L2_NodeList_Clear(NODE_LIST *list)
 {
 	ASSERT(list != NULL);
-	list_clear(list);
+	clist_clear(list);
 }
 
 /*****************************************************************************/
@@ -114,7 +114,7 @@ void L2_NodeList_Clear(NODE_LIST *list)
  ******************************************************************************/
 void L2_NodeList_Destroy(NODE_LIST *list)
 {
-	list_destroy(list);
+	clist_destroy(list);
 }
 /*****************************************************************************/
 /**
@@ -131,7 +131,7 @@ NODE_ENTRY *L2_GetNodeById(NODE_LIST *list, uint8_t nodeId)
 {
 	ASSERT(list != NULL);
 	util_entry.nodeInfo.nodeId = nodeId;
-	list_node_t *node = list_find(list, &util_entry);
+	clist_node_t *node = clist_find(list, &util_entry);
 	if (node == NULL)
 	{
 		return NULL;
@@ -169,7 +169,7 @@ NODE_ENTRY *L2_AppendNode(NODE_LIST *list, uint8_t nodeId, L2_NODE_TYPE nodeType
 		DBG_ERROR("Failed to allocated memory for nodeEntry.\n");
 		return NULL;
 	}
-	list_node_t *node = list_node_new(nodeEntry);
+	clist_node_t *node = clist_node_new(nodeEntry);
 	if (node == NULL)
 	{
 		DBG_ERROR("Failed to allocated memory for list node.\n");
@@ -186,7 +186,7 @@ NODE_ENTRY *L2_AppendNode(NODE_LIST *list, uint8_t nodeId, L2_NODE_TYPE nodeType
 	nodeEntry->nodeInfo.speed.z = 0;
 	nodeEntry->nodeInfo.beamNo = 0;
 	nodeEntry->ttlCnt = 0;
-	list_rpush(list, node);
+	clist_rpush(list, node);
 	return nodeEntry;
 }
 
@@ -205,14 +205,14 @@ int32_t L2_DeleteNodeById(NODE_LIST *list, uint8_t nodeId)
 {
 	ASSERT(list != NULL);
 	util_entry.nodeInfo.nodeId = nodeId;
-	list_node_t *node = list_find(list, &util_entry);
+	clist_node_t *node = clist_find(list, &util_entry);
 	if (node == NULL)
 	{
 		DBG_WARNING("Node [%d] in not in node list, skip deleting process.\n", nodeId);
 		return SUCCESS;
 	}
 	DBG_INFO("Deleting node [%d].\n", nodeId);
-	list_remove(list, node);
+	clist_remove(list, node);
 	return SUCCESS;
 }
 
@@ -490,14 +490,14 @@ int32_t L2_IterEditNode(NODE_LIST *list, const void *param, int32_t (*operation)
 {
 	ASSERT(list != NULL);
 	int32_t Status;
-	list_node_t *node;
-	list_iterator_t *iter = list_iterator_new(list, LIST_HEAD);
+	clist_node_t *node;
+	clist_iterator_t *iter = clist_iterator_new(list, LIST_HEAD);
 	if (iter == NULL)
 	{
 		DBG_ERROR("Failed to initialize list iteration process.\n");
 		return EALLOC;
 	}
-	while ((node = list_iterator_next(iter)))
+	while ((node = clist_iterator_next(iter)))
 	{
 		Status = operation((NODE_ENTRY *)node->val, param);
 		if (Status != SUCCESS)
@@ -506,7 +506,7 @@ int32_t L2_IterEditNode(NODE_LIST *list, const void *param, int32_t (*operation)
 			break;
 		}
 	}
-	list_iterator_destroy(iter);
+	clist_iterator_destroy(iter);
 	return Status;
 }
 
@@ -524,20 +524,20 @@ int32_t L2_IterEditNode(NODE_LIST *list, const void *param, int32_t (*operation)
 int32_t L2_IterDeleteNode(NODE_LIST *list, bool (*condition)(NODE_ENTRY *))
 {
 	ASSERT(list != NULL);
-	list_node_t *node;
-	list_iterator_t *iter = list_iterator_new(list, LIST_HEAD);
+	clist_node_t *node;
+	clist_iterator_t *iter = clist_iterator_new(list, LIST_HEAD);
 	if (iter == NULL)
 	{
 		DBG_ERROR("Failed to initialize list iteration process.\n");
 		return EALLOC;
 	}
-	while ((node = list_iterator_next(iter)))
+	while ((node = clist_iterator_next(iter)))
 	{
 		if (condition((NODE_ENTRY *)node->val) == false)
 		{
-			list_remove(list, node);
+			clist_remove(list, node);
 		}
 	}
-	list_iterator_destroy(iter);
+	clist_iterator_destroy(iter);
 	return SUCCESS;
 }

datalink814_ge/src/linklayer/node_list.h

@@ -24,7 +24,7 @@
 #include "linklayer814_types.h"
 #include "geometry/coord.h"
 #include "../util/util.h"
-#include "../util/list.h"
+#include "../util/clist.h"
 
 /************************** Constant Definitions *****************************/
 /***************** Macros (Inline Functions) Definitions *********************/
@@ -36,7 +36,7 @@ typedef struct NODE_LIST_ENTRY
 	int32_t timeDevi;
 } NODE_ENTRY;
 
-typedef list_t NODE_LIST;
+typedef clist_t NODE_LIST;
 
 /************************** Variable Definitions *****************************/
 

datalink814_ge/src/linklayer/rtt.c

@@ -0,0 +1,472 @@
+/*****************************************************************************/
+/**
+ * Description: RTT algorithm.
+ *
+ * Author: FanHao
+ * Date: 2023-12-10 20:43
+ * LastEditors: FanHao
+ * LastEditTime: 2023-12-10 20:43
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-12-10]: Initial version, split form time_sync.c
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <string.h>
+#include <stdlib.h>
+#include "linklayer814.h"
+#include "rtt.h"
+#include "../time_ctrl/time_ctrl.h"
+#include "../phy_ctrl/phy_ctrl.h"
+#include "../error.h"
+#include "../common.h"
+
+/************************** Constant Definitions *****************************/
+#define LIGHT_SPPED_AIR 299702547.0 // m/s
+#define LIGHT_SPPED_VAC 299792458.0 // m/s
+#define RTT_DOPPLER_NONE UINT32_MAX
+
+const TIME_WORD RTT_TIME_NONE = 
+{
+	.int_part = UINT32_MAX,
+	.frac_part = UINT32_MAX
+};
+/***************** Macros (Inline Functions) Definitions *********************/
+/**************************** Type Definitions *******************************/
+/************************** Variable Definitions *****************************/
+/************************** Function Prototypes ******************************/
+
+static void RTT_StageUpdate(L2_RTT_FSM *rttFsmPtr, L2_RTT_STGE newStage);
+static void RTT_GetFrameStart(L2_INST *instPtr, TIME_WORD *tmStamp, L2_TOR_TYPE torType);
+
+/*****************************************************************************/
+/**
+ * @brief   Update corrent time-sync for RTT stage
+ *
+ * @param   scanFsmPtr  A pointer to scan net fsm.
+ * @param   newSatge    New state.
+ *
+ * @return  NONE.
+ *
+ ******************************************************************************/
+static void RTT_StageUpdate(L2_RTT_FSM *rttFsmPtr, L2_RTT_STGE newStage)
+{
+	ASSERT(rttFsmPtr != NULL);
+	ASSERT(newStage >= RTT_NONE_STAGE && newStage <= RTT_RSP2);
+	DBG_INFO("RTT Stage Update: %d -> %d.\n", rttFsmPtr->rttStage, newStage);
+	rttFsmPtr->rttStage = newStage;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Reset RTT FSM
+ *
+ * @param   rttFsmPtr	a pointer to rtt FSM instance.
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void RTT_Reset(L2_RTT_FSM *rttFsmPtr)
+{
+	ASSERT(rttFsmPtr != NULL);
+	memset(&(rttFsmPtr->rttRecord), 0x00, sizeof(RTT_RECORD));
+	rttFsmPtr->rttStage = RTT_REQ1;
+	rttFsmPtr->isR1Valid = false;
+	rttFsmPtr->isR2Valid = false;
+	rttFsmPtr->isR3Valid = false;
+	rttFsmPtr->isR4Valid = false;
+	rttFsmPtr->timeStamp.int_part = 0;
+	rttFsmPtr->timeStamp.frac_part = 0;
+	rttFsmPtr->doppler = 0;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Destroy RTT FSM, free allocated memory.
+ *
+ * @param   rttFsmPtr	a pointer to rtt FSM instance.
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void RTT_Destroy(L2_RTT_FSM *rttFsmPtr)
+{
+	free(rttFsmPtr);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get the frame start time. If torType == L2_TOR_TX, get the next
+ * 			slot start time, if torType == L2_TOR_RX get last frame start
+ * 			time.
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ * @param   tmStamp	a pointer to store frame start time
+ * @param   torType	tx/rx mode
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void RTT_GetFrameStart(L2_INST *instPtr, TIME_WORD *tmStamp, L2_TOR_TYPE torType)
+{
+	ASSERT(instPtr != NULL);
+	ASSERT(tmStamp != NULL);
+	// Get the next frame start time
+	if (torType == L2_TOR_TX)
+	{
+		tmStamp->int_part = L2_GetNextFrameNum(instPtr) * L2_SLOTS_PER_FRAME + L2_GetNextSlotNum(instPtr);
+		tmStamp->frac_part = 0;
+	}
+	// Get the last reiceive frame start time
+	else if (torType == L2_TOR_RX)
+	{
+		PHY_INST *phyRef = instPtr->config.phyInstPtr;
+		TIME_WORD timeStamp;
+		int64_t timeDiff;
+		Phy_GetLastReceivedFrameSyncTimeStamp(phyRef, &timeStamp);
+		timeDiff = (uint64_t)timeStamp.frac_part;
+		timeDiff += ((uint64_t)timeStamp.int_part) * TIME_FRAC_MAX;
+		Phy_GetLastReceivedSlotStartTimeStamp(phyRef, tmStamp);
+		timeDiff -= ((uint64_t)tmStamp->int_part) * TIME_FRAC_MAX;
+		timeDiff -= (uint64_t)tmStamp->frac_part;
+		timeDiff = (int64_t)Phy_GetTimeComp(L2_L2frame2L1frame(L2_GetLastFrameType(instPtr))) - timeDiff;
+		if (timeDiff < 0)
+		{
+			timeDiff += TIME_FRAC_MAX;
+			tmStamp->int_part--;
+			_nop_();
+		}
+		tmStamp->frac_part = (TIME_FRAC)timeDiff;
+	}
+	else
+	{
+		*tmStamp = RTT_TIME_NONE;
+		DBG_ERROR("Unexpected tx/rx mode, setting dummy values.\n");
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Initialize RTT FSM, allocate memory for FSM instance.
+ *
+ * @param   rttFsmPtr
+ *
+ * @return  SUCCESS Initialization successful.
+ *          EMAC_MEMORY_ALLOC_ERROR Memory allocate error.
+ *
+ ******************************************************************************/
+int32_t RTT_Init(L2_RTT_FSM **rttFsmPtr)
+{
+	(*rttFsmPtr) = (L2_RTT_FSM *)malloc(sizeof(L2_RTT_FSM));
+	if (*rttFsmPtr == NULL)
+	{
+		free(*rttFsmPtr);
+		return EALLOC;
+	}
+	RTT_Reset(*rttFsmPtr);
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Update RTT FSM accordingly.
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ * @param	torType tx/rx mode type
+ *
+ * @return  SUCCESS
+ * 			error code
+ *
+ ******************************************************************************/
+int32_t RTT_FsmUpdate(L2_INST *instPtr, L2_TOR_TYPE torType)
+{
+	ASSERT(instPtr != NULL);
+	L2_RTT_FSM *rttFsmPtr = L2_GetRttFsm(instPtr);
+	RTT_RECORD *rttRecord = &(rttFsmPtr->rttRecord);
+	PHY_INST *phyRef = instPtr->config.phyInstPtr;
+
+	DBG_INFO("-------- RTT FSM Update --------\n");
+	// Stage trans
+	// For Head Node: Tx->Rx->Tx->Rx
+	if (L2_GetNodeType(instPtr) == L2_NODE_HEAD)
+	{
+		switch (rttFsmPtr->rttStage)
+		{
+		case RTT_REQ1:
+			if (torType == L2_TOR_TX)
+			{
+				DBG_INFO("Prepare data for RTT REQ-1\n");
+				// Update Tt1
+				RTT_GetFrameStart(instPtr, &(rttRecord->Tt1), torType);
+				DBG_INFO("Tt1-timeL:%u.\n", rttRecord->Tt1.int_part);
+				DBG_INFO("Tt1-timeH:%u.\n", rttRecord->Tt1.frac_part);
+
+				// Prepare data for sending...
+				rttFsmPtr->timeStamp = rttRecord->Tt1;
+				rttFsmPtr->doppler = RTT_DOPPLER_NONE;
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP1);
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		case RTT_RSP1:
+			if (torType == L2_TOR_RX)
+			{
+				if (L2_isDataAvail(instPtr) == true)
+				{
+					DBG_INFO("RTT RSP-1 have been received.\n");
+					DBG_INFO("Preparing data for RTT REQ-2.\n");
+					rttFsmPtr->isR2Valid = true;
+					// Update doppler
+					rttRecord->dopplerR2 = (int32_t)Phy_GetFreqEst(phyRef);
+					// Update Tr2
+					RTT_GetFrameStart(instPtr, &(rttRecord->Tr2), torType);
+					// Calculate TroundA
+					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt1), &(rttRecord->Tr2), &(rttRecord->TroundA));
+				}
+				else
+				{
+					DBG_WARNING("RTT RSP-1 had not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set Tr2 dopplerR2 and TroundA to dummy value.\n");
+					rttFsmPtr->isR2Valid = false;
+					rttRecord->dopplerR2 = RTT_DOPPLER_NONE;
+					rttRecord->Tr2 = RTT_TIME_NONE;
+					rttRecord->TroundA = RTT_TIME_NONE;
+				}
+				DBG_INFO("dopplerR2:%d.\n", rttRecord->dopplerR2);
+				DBG_INFO("Tr2-timeL:%u.\n", rttRecord->Tr2.frac_part);
+				DBG_INFO("Tr2-timeH:%u.\n", rttRecord->Tr2.int_part);
+				DBG_INFO("TroundA-timeL:%u.\n", rttRecord->TroundA.frac_part);
+				DBG_INFO("TroundA-timeH:%u.\n", rttRecord->TroundA.int_part);
+				RTT_StageUpdate(rttFsmPtr, RTT_REQ2);
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		case RTT_REQ2:
+			if (torType == L2_TOR_TX)
+			{
+				DBG_INFO("Prepare data for RTT REQ-2\n");
+				// Update Tt3
+				RTT_GetFrameStart(instPtr, &(rttRecord->Tt3), torType);
+
+				if (rttFsmPtr->isR2Valid)
+				{
+					// Calculate reply A
+					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt3), &(rttRecord->Tr2), &(rttRecord->TreplyA));
+				}
+				else
+				{
+					DBG_WARNING("RTT RSP-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set TreplyA to dummy value.\n");
+					rttRecord->TreplyA = RTT_TIME_NONE;
+				}
+				DBG_INFO("Tt3-timeL:%u.\n", rttRecord->Tt3.frac_part);
+				DBG_INFO("Tt3-timeH:%u.\n", rttRecord->Tt3.int_part);
+				DBG_INFO("TreplyA-timeL:%u.\n", rttRecord->TreplyA.frac_part);
+				DBG_INFO("TreplyA-timeH:%u.\n", rttRecord->TreplyA.int_part);
+
+				// Prepare data for sending.
+				rttFsmPtr->timeStamp = rttRecord->TroundA;
+				rttFsmPtr->doppler = rttRecord->dopplerR2;
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP2);
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		case RTT_RSP2:
+			if (torType == L2_TOR_RX)
+			{
+				if (L2_isDataAvail(instPtr) == true)
+				{
+					DBG_INFO("RTT RSP-2 have been received.\n");
+					rttFsmPtr->isR4Valid = true;
+					// Update doppler
+					double doppler = Phy_GetFreqEst(phyRef);
+					rttRecord->dopplerR2 = (int32_t)doppler;
+					// Update Tr4
+					RTT_GetFrameStart(instPtr, &(rttRecord->Tr4), torType);
+					// Calculate TroundA
+					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt3), &(rttRecord->Tr4), &(rttRecord->TroundA));
+				}
+				else
+				{
+					DBG_WARNING("RTT RSP-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set Tr4 dopplerR4 and TroundA to dummy value.\n");
+					rttFsmPtr->isR4Valid = false;
+					rttRecord->dopplerR4 = RTT_DOPPLER_NONE;
+					rttRecord->Tr4 = RTT_TIME_NONE;
+					rttRecord->TroundA = RTT_TIME_NONE;
+				}
+				DBG_INFO("dopplerR4:%d.\n", rttRecord->dopplerR4);
+				DBG_INFO("Tr4-timeL:%u.\n", rttRecord->Tr4.frac_part);
+				DBG_INFO("Tr4-timeH:%u.\n", rttRecord->Tr4.int_part);
+				DBG_INFO("TroundA-timeL:%u.\n", rttRecord->TroundA.frac_part);
+				DBG_INFO("TroundA-timeH:%u.\n", rttRecord->TroundA.int_part);
+				RTT_StageUpdate(rttFsmPtr, RTT_REQ1);
+				DBG_INFO("RTT procedure end...\n");
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		default:
+			DBG_ERROR("Unexpected RTT FSM stage [%d].\n", rttFsmPtr->rttStage);
+			break;
+		}
+	}
+	// For Member Node: Rx->Tx->Rx->Tx
+	else
+	{
+		switch (rttFsmPtr->rttStage)
+		{
+		case RTT_REQ1:
+			if (torType == L2_TOR_RX)
+			{
+				if (L2_isDataAvail(instPtr) == true)
+				{
+					DBG_INFO("RTT REQ-1 have been received.\n");
+					DBG_INFO("Preparing data for RTT RSP-1.\n");
+					rttFsmPtr->isR2Valid = true;
+					// Update doppler
+					rttRecord->dopplerR2 = (int32_t)Phy_GetFreqEst(phyRef);
+					// Update Tr1
+					RTT_GetFrameStart(instPtr, &(rttRecord->Tr1), torType);
+				}
+				else
+				{
+					DBG_WARNING("RTT REQ-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set dopplerR1 and Tr1 to dummy value.\n");
+					rttFsmPtr->isR1Valid = false;
+					rttRecord->dopplerR1 = RTT_DOPPLER_NONE;
+					rttRecord->Tr1 = RTT_TIME_NONE;
+				}
+				DBG_INFO("dopplerR1:%d.\n", rttRecord->dopplerR1);
+				DBG_INFO("Tr1-timeL:%u.\n", rttRecord->Tr1.frac_part);
+				DBG_INFO("Tr1-timeH:%u.\n", rttRecord->Tr1.int_part);
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP1);
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		case RTT_RSP1:
+			if (torType == L2_TOR_TX)
+			{
+				DBG_INFO("Prepare data for RTT RSP-1\n");
+				// Update Tt2
+				RTT_GetFrameStart(instPtr, &(rttRecord->Tt2), torType);
+				if (rttFsmPtr->isR1Valid)
+				{
+					// Calculate reply B
+					TimeCtrl_CalculateTimeGap(&(rttRecord->Tr1), &(rttRecord->Tt2), &(rttRecord->TreplyB));
+				}
+				else
+				{
+					rttRecord->TreplyB = RTT_TIME_NONE;
+					DBG_WARNING("RTT REQ-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set ReplayB to dummy value.\n");
+				}
+				DBG_INFO("Tt2-timeL:%u.\n", rttRecord->Tt2.frac_part);
+				DBG_INFO("Tt2-timeH:%u.\n", rttRecord->Tt2.int_part);
+				DBG_INFO("TreplyB-timeL:%u.\n", rttRecord->TreplyB.frac_part);
+				DBG_INFO("TreplyB-timeH:%u.\n", rttRecord->TreplyB.int_part);
+
+				// Prepare data for sending.
+				rttFsmPtr->timeStamp = rttRecord->TreplyB;
+				rttFsmPtr->doppler = rttRecord->dopplerR1;
+				RTT_StageUpdate(rttFsmPtr, RTT_REQ2);
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		case RTT_REQ2:
+			if (torType == L2_TOR_RX)
+			{
+				if (L2_isDataAvail(instPtr) == true)
+				{
+					DBG_INFO("RTT REQ-2 have been received.\n");
+					DBG_INFO("Preparing data for RTT RSP-2.\n");
+					rttFsmPtr->isR3Valid = true;
+					// Update doppler
+					rttRecord->dopplerR2 = (int32_t)Phy_GetFreqEst(phyRef);
+					// Update Tr3
+					RTT_GetFrameStart(instPtr, &(rttRecord->Tr3), torType);
+					// Calculate TroundB
+					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt2), &(rttRecord->Tr3), &(rttRecord->TroundB));
+				}
+				else
+				{
+					DBG_WARNING("RTT REQ-2 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set dopplerR3 and ReplayB to dummy value.\n");
+					rttFsmPtr->isR3Valid = false;
+					rttRecord->dopplerR3 = RTT_DOPPLER_NONE;
+					rttRecord->TroundB = RTT_TIME_NONE;
+				}
+				DBG_INFO("dopplerR3:%d.\n", rttRecord->dopplerR3);
+				DBG_INFO("Tr3-timeL:%u.\n", rttRecord->Tr3.frac_part);
+				DBG_INFO("Tr3-timeH:%u.\n", rttRecord->Tr3.int_part);
+				DBG_INFO("TroundB-timeL:%u.\n", rttRecord->TroundB.frac_part);
+				DBG_INFO("TroundB-timeH:%u.\n", rttRecord->TroundB.int_part);
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP2);
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		case RTT_RSP2:
+			if (torType == L2_TOR_TX)
+			{
+				DBG_INFO("Prepare data for RTT RSP-2\n");
+				// Update Tt4
+				RTT_GetFrameStart(instPtr, &(rttRecord->Tt4), torType);
+				if (rttFsmPtr->isR3Valid)
+				{
+					// Calculate reply B
+					TimeCtrl_CalculateTimeGap(&(rttRecord->Tr3), &(rttRecord->Tt4), &(rttRecord->TreplyB));
+					// TODO: implement a time adjustment.
+				}
+				else
+				{
+					DBG_WARNING("RTT REQ-2 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
+					DBG_WARNING("Set ReplayB to dummy value.\n");
+					rttRecord->TreplyB = RTT_TIME_NONE;
+				}
+				DBG_INFO("Tt4-timeL:%u.\n", rttRecord->Tt4.frac_part);
+				DBG_INFO("Tt4-timeH:%u.\n", rttRecord->Tt4.int_part);
+				DBG_INFO("TreplyB-timeL:%u.\n", rttRecord->TreplyB.frac_part);
+				DBG_INFO("TreplyB-timeH:%u.\n", rttRecord->TreplyB.int_part);
+
+				// Prepare data for sending.
+				rttFsmPtr->timeStamp = rttRecord->TreplyB;
+				rttFsmPtr->doppler = rttRecord->dopplerR3;
+				RTT_StageUpdate(rttFsmPtr, RTT_REQ1);
+				DBG_INFO("RTT procedure end...\n");
+			}
+			else
+			{
+				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
+			}
+			break;
+		default:
+			DBG_ERROR("Unexpected RTT FSM stage [%d].\n", rttFsmPtr->rttStage);
+			break;
+		}
+	}
+	return SUCCESS;
+}

datalink814_ge/src/linklayer/schdevent.c

@@ -20,7 +20,7 @@
 #include "linklayer814.h"
 #include "linklayer814_types.h"
 #include "../error.h"
-#include "../util/list.h"
+#include "../util/clist.h"
 /***************** Macros (Inline Functions) Definitions *********************/
 /**************************** Type Definitions *******************************/
 /************************** Variable Definitions *****************************/
@@ -80,7 +80,7 @@ int32_t L2_CreateSchedEventPool(L2_SCHD_POOL **schdPool)
 		DBG_ERROR("Failed to allocated memory for schdPool.\n");
 		return EALLOC;
 	}
-	(*schdPool)->schdList = list_new();
+	(*schdPool)->schdList = clist_new();
 	if ((*schdPool)->schdList == NULL)
 	{
 		DBG_ERROR("Failed to allocated memory for schdPool->schdList.\n");
@@ -106,7 +106,7 @@ int32_t L2_CreateSchedEventPool(L2_SCHD_POOL **schdPool)
 void L2_ClearSchedEventPool(L2_SCHD_POOL *schdPool)
 {
 	ASSERT(schdPool != NULL);
-	list_clear(schdPool->schdList);
+	clist_clear(schdPool->schdList);
 	schdPool->envCnt = 0;
 }
 
@@ -125,7 +125,7 @@ void L2_DestroySchedEventPool(L2_SCHD_POOL *schdPool)
 	{
 		return;
 	}
-	list_destroy(schdPool->schdList);
+	clist_destroy(schdPool->schdList);
 	free(schdPool);
 }
 
@@ -155,7 +155,7 @@ L2_SCHD_EVENT *L2_CreatNewSchdEvent(L2_SCHD_POOL *schdPool, L2_EVENT_TYPE event,
 		DBG_ERROR("Failed to allocate schedule event.\n");
 		return NULL;
 	}
-	list_node_t *node = list_node_new(schdEvent);
+	clist_node_t *node = clist_node_new(schdEvent);
 	if (node == NULL)
 	{
 		DBG_ERROR("Failed to allocate schedule event list node.\n");
@@ -170,7 +170,7 @@ L2_SCHD_EVENT *L2_CreatNewSchdEvent(L2_SCHD_POOL *schdPool, L2_EVENT_TYPE event,
 	schdEvent->isVolatile = isVolatile;
 	schdEvent->schdSlot = L2_SLOTNO_NONE;
 	schdEvent->schdFrame = L2_FRAMENO_NONE;
-	list_rpush(schdPool->schdList, node);
+	clist_rpush(schdPool->schdList, node);
 	return schdEvent;
 }
 
@@ -189,7 +189,7 @@ L2_SCHD_EVENT *L2_GetEventById(L2_SCHD_POOL *schdPool, uint32_t id)
 {
 	ASSERT(schdPool != NULL);
 	util_schdevent.eventId = id;
-	list_node_t *node = list_find(schdPool->schdList, &util_schdevent);
+	clist_node_t *node = clist_find(schdPool->schdList, &util_schdevent);
 	if (node != NULL)
 	{
 		DBG_WARNING("Event with id=%d, dose not exist.\n", id);
@@ -214,13 +214,13 @@ int32_t L2_DeleteSchdEventById(L2_SCHD_POOL *schdPool, uint32_t id)
 {
 	ASSERT(schdPool != NULL);
 	util_schdevent.eventId = id;
-	list_node_t *node = list_find(schdPool->schdList, &util_schdevent);
+	clist_node_t *node = clist_find(schdPool->schdList, &util_schdevent);
 	if (node != NULL)
 	{
 		DBG_ERROR("Event with id=%d, dose not exist.\n", id);
 		return EIGNORE;
 	}
-	list_remove(schdPool->schdList, node);
+	clist_remove(schdPool->schdList, node);
 	return SUCCESS;
 }
 
@@ -343,16 +343,16 @@ int32_t L2_RescheduleEventAfter(L2_INST *instPtr, L2_SCHD_EVENT *schdEvent, uint
 void L2_EventPoolHandler(L2_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
-	list_node_t *node;
+	clist_node_t *node;
 	L2_SCHD_EVENT *event;
 	L2_SCHD_POOL *pool = instPtr->schdEventPool;
-	list_iterator_t *iter = list_iterator_new(pool->schdList, LIST_HEAD);
+	clist_iterator_t *iter = clist_iterator_new(pool->schdList, LIST_HEAD);
 	if (iter == NULL)
 	{
 		DBG_ERROR("Failed to initialize schedule event pool iteration.\n");
 		return;
 	}
-	while ((node = list_iterator_next(iter)))
+	while ((node = clist_iterator_next(iter)))
 	{
 		event = (L2_SCHD_EVENT *)node->val;
 		if (L2_isEventScheduled(event))
@@ -364,7 +364,7 @@ void L2_EventPoolHandler(L2_INST *instPtr)
 				if (event->isVolatile == true)
 				{
 					DBG_INFO("Deleting scheduled event [%d], since it is volatile.\n", event->eventId);
-					list_remove(pool->schdList, node);
+					clist_remove(pool->schdList, node);
 				}
 				else
 				{
@@ -373,7 +373,7 @@ void L2_EventPoolHandler(L2_INST *instPtr)
 			}
 		}
 	}
-	list_iterator_destroy(iter);
+	clist_iterator_destroy(iter);
 }
 
 /*****************************************************************************/

datalink814_ge/src/linklayer/schdevent.h

@@ -21,7 +21,7 @@
 #include <stdlib.h>
 #include "linklayer814_types.h"
 #include "../error.h"
-#include "../util/list.h"
+#include "../util/clist.h"
 /***************** Macros (Inline Functions) Definitions *********************/
 /**************************** Type Definitions *******************************/
 /** @name L2 event
@@ -43,7 +43,7 @@ typedef struct
  */
 typedef struct
 {
-	list_t *schdList;
+	clist_t *schdList;
 	uint32_t envCnt;
 } L2_SCHD_POOL;
 

datalink814_ge/src/linklayer/time_sync.c

@@ -20,27 +20,17 @@
 #include <string.h>
 #include <stdlib.h>
 #include "linklayer814.h"
-#include "rtt.h"
 #include "../time_ctrl/time_ctrl.h"
+#include "../phy_ctrl/phy_ctrl.h"
 #include "../error.h"
 #include "../common.h"
 
 /************************** Constant Definitions *****************************/
-#define LIGHT_SPPED_AIR 299702547.0 // m/s
-#define LIGHT_SPPED_VAC 299792458.0 // m/s
-#define RTT_DOPPLER_NONE UINT32_MAX
-
-const TIME_WORD RTT_TIME_NONE = {
-	.int_part = UINT32_MAX,
-	.frac_part = UINT32_MAX};
 /***************** Macros (Inline Functions) Definitions *********************/
 /**************************** Type Definitions *******************************/
 /************************** Variable Definitions *****************************/
 /************************** Function Prototypes ******************************/
 
-static void RTT_StageUpdate(L2_RTT_FSM *rttFsmPtr, L2_RTT_STGE newStage);
-static void RTT_GetFrameStart(L2_INST *instPtr, TIME_WORD *tmStamp, L2_TOR_TYPE torType);
-
 /*****************************************************************************/
 /**
  * @brief    a slot alignment, base on physical layer information.
@@ -61,9 +51,11 @@ int32_t L2_TimeAlign(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool
 	lastRecvdFrame = Phy_GetLastRecvFrameType(instPtr->config.phyInstPtr);
 	if (lastRecvdFrame == L1_NONE_FRAME)
 	{
+		DBG_ERROR("Invalid TimeAlign operation, no frame was received.");
 		return EIGNORE;
 	}
 
+	DBG_INFO("Starting TimeAlign operation...\n");
 	// read nextSendTime from physical layer
 	uint64_t currTime, expctTime;
 	int64_t timeDiff;
@@ -86,432 +78,4 @@ int32_t L2_TimeAlign(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool
 	slotTimerAdjmet.frac_part = (uint32_t)(timeDiff % TIME_FRAC_MAX);
 	TimeCtrl_TimeAdjust(instPtr->config.tmcInstPtr, &slotTimerAdjmet, TM_ADJ_ADD);
 	return SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Update corrent time-sync for RTT stage
- *
- * @param   scanFsmPtr  A pointer to scan net fsm.
- * @param   newSatge    New state.
- *
- * @return  NONE.
- *
- ******************************************************************************/
-static void RTT_StageUpdate(L2_RTT_FSM *rttFsmPtr, L2_RTT_STGE newStage)
-{
-	ASSERT(rttFsmPtr != NULL);
-	ASSERT(newStage >= RTT_NONE_STAGE && newStage <= RTT_RSP2);
-	DBG_INFO("RTT Stage Update: %d -> %d.\n", rttFsmPtr->rttStage, newStage);
-	rttFsmPtr->rttStage = newStage;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Reset RTT FSM
- *
- * @param   rttFsmPtr	a pointer to rtt FSM instance.
- *
- * @return  NONE
- *
- ******************************************************************************/
-void RTT_Reset(L2_RTT_FSM *rttFsmPtr)
-{
-	ASSERT(rttFsmPtr != NULL);
-	memset(&(rttFsmPtr->rttRecord), 0x00, sizeof(RTT_RECORD));
-	rttFsmPtr->rttStage = RTT_REQ1;
-	rttFsmPtr->isR1Valid = false;
-	rttFsmPtr->isR2Valid = false;
-	rttFsmPtr->isR3Valid = false;
-	rttFsmPtr->isR4Valid = false;
-	rttFsmPtr->timeStamp.int_part = 0;
-	rttFsmPtr->timeStamp.frac_part = 0;
-	rttFsmPtr->doppler = 0;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Destroy RTT FSM, free allocated memory.
- *
- * @param   rttFsmPtr	a pointer to rtt FSM instance.
- *
- * @return  NONE
- *
- ******************************************************************************/
-void RTT_Destroy(L2_RTT_FSM *rttFsmPtr)
-{
-	free(rttFsmPtr);
-}
-
-/*****************************************************************************/
-/**
- * @brief   Get the frame start time. If torType == L2_TOR_TX, get the next
- * 			slot start time, if torType == L2_TOR_RX get last frame start
- * 			time.
- *
- * @param   instPtr	a pointer to linklayer layer instance
- * @param   tmStamp	a pointer to store frame start time
- * @param   torType	tx/rx mode
- *
- * @return  NONE
- *
- ******************************************************************************/
-void RTT_GetFrameStart(L2_INST *instPtr, TIME_WORD *tmStamp, L2_TOR_TYPE torType)
-{
-	ASSERT(instPtr != NULL);
-	ASSERT(tmStamp != NULL);
-	// Get the next frame start time
-	if (torType == L2_TOR_TX)
-	{
-		tmStamp->int_part = L2_GetNextFrameNum(instPtr) * L2_SLOTS_PER_FRAME + L2_GetNextSlotNum(instPtr);
-		tmStamp->frac_part = 0;
-	}
-	// Get the last reiceive frame start time
-	else if (torType == L2_TOR_RX)
-	{
-		PHY_INST *phyRef = instPtr->config.phyInstPtr;
-		TIME_WORD timeStamp;
-		int64_t timeDiff;
-		Phy_GetLastReceivedFrameSyncTimeStamp(phyRef, &timeStamp);
-		timeDiff = (uint64_t)timeStamp.frac_part;
-		timeDiff += ((uint64_t)timeStamp.int_part) * TIME_FRAC_MAX;
-		Phy_GetLastReceivedSlotStartTimeStamp(phyRef, tmStamp);
-		timeDiff -= ((uint64_t)tmStamp->int_part) * TIME_FRAC_MAX;
-		timeDiff -= (uint64_t)tmStamp->frac_part;
-		timeDiff = (int64_t)Phy_GetTimeComp(L2_L2frame2L1frame(L2_GetLastFrameType(instPtr))) - timeDiff;
-		if (timeDiff < 0)
-		{
-			timeDiff += TIME_FRAC_MAX;
-			tmStamp->int_part--;
-			_nop_();
-		}
-		tmStamp->frac_part = (TIME_FRAC)timeDiff;
-	}
-	else
-	{
-		*tmStamp = RTT_TIME_NONE;
-		DBG_ERROR("Unexpected tx/rx mode, setting dummy values.\n");
-	}
-}
-
-/*****************************************************************************/
-/**
- * @brief   Initialize RTT FSM, allocate memory for FSM instance.
- *
- * @param   rttFsmPtr
- *
- * @return  SUCCESS Initialization successful.
- *          EMAC_MEMORY_ALLOC_ERROR Memory allocate error.
- *
- ******************************************************************************/
-int32_t RTT_Init(L2_RTT_FSM **rttFsmPtr)
-{
-	(*rttFsmPtr) = (L2_RTT_FSM *)malloc(sizeof(L2_RTT_FSM));
-	if (*rttFsmPtr == NULL)
-	{
-		free(*rttFsmPtr);
-		return EALLOC;
-	}
-	RTT_Reset(*rttFsmPtr);
-	return SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Update RTT FSM accordingly.
- *
- * @param   instPtr	a pointer to linklayer layer instance
- * @param	torType tx/rx mode type
- *
- * @return  SUCCESS
- * 			error code
- *
- ******************************************************************************/
-int32_t RTT_FsmUpdate(L2_INST *instPtr, L2_TOR_TYPE torType)
-{
-	ASSERT(instPtr != NULL);
-	L2_RTT_FSM *rttFsmPtr = L2_GetRttFsm(instPtr);
-	RTT_RECORD *rttRecord = &(rttFsmPtr->rttRecord);
-	PHY_INST *phyRef = instPtr->config.phyInstPtr;
-
-	DBG_INFO("-------- RTT FSM Update --------\n");
-	// Stage trans
-	// For Head Node: Tx->Rx->Tx->Rx
-	if (L2_GetNodeType(instPtr) == L2_NODE_HEAD)
-	{
-		switch (rttFsmPtr->rttStage)
-		{
-		case RTT_REQ1:
-			if (torType == L2_TOR_TX)
-			{
-				DBG_INFO("Prepare data for RTT REQ-1\n");
-				// Update Tt1
-				RTT_GetFrameStart(instPtr, &(rttRecord->Tt1), torType);
-				DBG_INFO("Tt1-timeL:%u.\n", rttRecord->Tt1.int_part);
-				DBG_INFO("Tt1-timeH:%u.\n", rttRecord->Tt1.frac_part);
-
-				// Prepare data for sending...
-				rttFsmPtr->timeStamp = rttRecord->Tt1;
-				rttFsmPtr->doppler = RTT_DOPPLER_NONE;
-				RTT_StageUpdate(rttFsmPtr, RTT_RSP1);
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		case RTT_RSP1:
-			if (torType == L2_TOR_RX)
-			{
-				if (L2_isDataAvail(instPtr) == true)
-				{
-					DBG_INFO("RTT RSP-1 have been received.\n");
-					DBG_INFO("Preparing data for RTT REQ-2.\n");
-					rttFsmPtr->isR2Valid = true;
-					// Update doppler
-					rttRecord->dopplerR2 = (int32_t)Phy_GetCoarseFreqEst(phyRef);
-					// Update Tr2
-					RTT_GetFrameStart(instPtr, &(rttRecord->Tr2), torType);
-					// Calculate TroundA
-					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt1), &(rttRecord->Tr2), &(rttRecord->TroundA));
-				}
-				else
-				{
-					DBG_WARNING("RTT RSP-1 had not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set Tr2 dopplerR2 and TroundA to dummy value.\n");
-					rttFsmPtr->isR2Valid = false;
-					rttRecord->dopplerR2 = RTT_DOPPLER_NONE;
-					rttRecord->Tr2 = RTT_TIME_NONE;
-					rttRecord->TroundA = RTT_TIME_NONE;
-				}
-				DBG_INFO("dopplerR2:%d.\n", rttRecord->dopplerR2);
-				DBG_INFO("Tr2-timeL:%u.\n", rttRecord->Tr2.frac_part);
-				DBG_INFO("Tr2-timeH:%u.\n", rttRecord->Tr2.int_part);
-				DBG_INFO("TroundA-timeL:%u.\n", rttRecord->TroundA.frac_part);
-				DBG_INFO("TroundA-timeH:%u.\n", rttRecord->TroundA.int_part);
-				RTT_StageUpdate(rttFsmPtr, RTT_REQ2);
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		case RTT_REQ2:
-			if (torType == L2_TOR_TX)
-			{
-				DBG_INFO("Prepare data for RTT REQ-2\n");
-				// Update Tt3
-				RTT_GetFrameStart(instPtr, &(rttRecord->Tt3), torType);
-
-				if (rttFsmPtr->isR2Valid)
-				{
-					// Calculate reply A
-					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt3), &(rttRecord->Tr2), &(rttRecord->TreplyA));
-				}
-				else
-				{
-					DBG_WARNING("RTT RSP-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set TreplyA to dummy value.\n");
-					rttRecord->TreplyA = RTT_TIME_NONE;
-				}
-				DBG_INFO("Tt3-timeL:%u.\n", rttRecord->Tt3.frac_part);
-				DBG_INFO("Tt3-timeH:%u.\n", rttRecord->Tt3.int_part);
-				DBG_INFO("TreplyA-timeL:%u.\n", rttRecord->TreplyA.frac_part);
-				DBG_INFO("TreplyA-timeH:%u.\n", rttRecord->TreplyA.int_part);
-
-				// Prepare data for sending.
-				rttFsmPtr->timeStamp = rttRecord->TroundA;
-				rttFsmPtr->doppler = rttRecord->dopplerR2;
-				RTT_StageUpdate(rttFsmPtr, RTT_RSP2);
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		case RTT_RSP2:
-			if (torType == L2_TOR_RX)
-			{
-				if (L2_isDataAvail(instPtr) == true)
-				{
-					DBG_INFO("RTT RSP-2 have been received.\n");
-					rttFsmPtr->isR4Valid = true;
-					// Update doppler
-					double doppler = Phy_GetCoarseFreqEst(phyRef);
-					rttRecord->dopplerR2 = (int32_t)doppler;
-					// Update Tr4
-					RTT_GetFrameStart(instPtr, &(rttRecord->Tr4), torType);
-					// Calculate TroundA
-					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt3), &(rttRecord->Tr4), &(rttRecord->TroundA));
-				}
-				else
-				{
-					DBG_WARNING("RTT RSP-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set Tr4 dopplerR4 and TroundA to dummy value.\n");
-					rttFsmPtr->isR4Valid = false;
-					rttRecord->dopplerR4 = RTT_DOPPLER_NONE;
-					rttRecord->Tr4 = RTT_TIME_NONE;
-					rttRecord->TroundA = RTT_TIME_NONE;
-				}
-				DBG_INFO("dopplerR4:%d.\n", rttRecord->dopplerR4);
-				DBG_INFO("Tr4-timeL:%u.\n", rttRecord->Tr4.frac_part);
-				DBG_INFO("Tr4-timeH:%u.\n", rttRecord->Tr4.int_part);
-				DBG_INFO("TroundA-timeL:%u.\n", rttRecord->TroundA.frac_part);
-				DBG_INFO("TroundA-timeH:%u.\n", rttRecord->TroundA.int_part);
-				RTT_StageUpdate(rttFsmPtr, RTT_REQ1);
-				DBG_INFO("RTT procedure end...\n");
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		default:
-			DBG_ERROR("Unexpected RTT FSM stage [%d].\n", rttFsmPtr->rttStage);
-			break;
-		}
-	}
-	// For Member Node: Rx->Tx->Rx->Tx
-	else
-	{
-		switch (rttFsmPtr->rttStage)
-		{
-		case RTT_REQ1:
-			if (torType == L2_TOR_RX)
-			{
-				if (L2_isDataAvail(instPtr) == true)
-				{
-					DBG_INFO("RTT REQ-1 have been received.\n");
-					DBG_INFO("Preparing data for RTT RSP-1.\n");
-					rttFsmPtr->isR2Valid = true;
-					// Update doppler
-					rttRecord->dopplerR2 = (int32_t)Phy_GetCoarseFreqEst(phyRef);
-					// Update Tr1
-					RTT_GetFrameStart(instPtr, &(rttRecord->Tr1), torType);
-				}
-				else
-				{
-					DBG_WARNING("RTT REQ-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set dopplerR1 and Tr1 to dummy value.\n");
-					rttFsmPtr->isR1Valid = false;
-					rttRecord->dopplerR1 = RTT_DOPPLER_NONE;
-					rttRecord->Tr1 = RTT_TIME_NONE;
-				}
-				DBG_INFO("dopplerR1:%d.\n", rttRecord->dopplerR1);
-				DBG_INFO("Tr1-timeL:%u.\n", rttRecord->Tr1.frac_part);
-				DBG_INFO("Tr1-timeH:%u.\n", rttRecord->Tr1.int_part);
-				RTT_StageUpdate(rttFsmPtr, RTT_RSP1);
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		case RTT_RSP1:
-			if (torType == L2_TOR_TX)
-			{
-				DBG_INFO("Prepare data for RTT RSP-1\n");
-				// Update Tt2
-				RTT_GetFrameStart(instPtr, &(rttRecord->Tt2), torType);
-				if (rttFsmPtr->isR1Valid)
-				{
-					// Calculate reply B
-					TimeCtrl_CalculateTimeGap(&(rttRecord->Tr1), &(rttRecord->Tt2), &(rttRecord->TreplyB));
-				}
-				else
-				{
-					rttRecord->TreplyB = RTT_TIME_NONE;
-					DBG_WARNING("RTT REQ-1 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set ReplayB to dummy value.\n");
-				}
-				DBG_INFO("Tt2-timeL:%u.\n", rttRecord->Tt2.frac_part);
-				DBG_INFO("Tt2-timeH:%u.\n", rttRecord->Tt2.int_part);
-				DBG_INFO("TreplyB-timeL:%u.\n", rttRecord->TreplyB.frac_part);
-				DBG_INFO("TreplyB-timeH:%u.\n", rttRecord->TreplyB.int_part);
-
-				// Prepare data for sending.
-				rttFsmPtr->timeStamp = rttRecord->TreplyB;
-				rttFsmPtr->doppler = rttRecord->dopplerR1;
-				RTT_StageUpdate(rttFsmPtr, RTT_REQ2);
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		case RTT_REQ2:
-			if (torType == L2_TOR_RX)
-			{
-				if (L2_isDataAvail(instPtr) == true)
-				{
-					DBG_INFO("RTT REQ-2 have been received.\n");
-					DBG_INFO("Preparing data for RTT RSP-2.\n");
-					rttFsmPtr->isR3Valid = true;
-					// Update doppler
-					rttRecord->dopplerR2 = (int32_t)Phy_GetCoarseFreqEst(phyRef);
-					// Update Tr3
-					RTT_GetFrameStart(instPtr, &(rttRecord->Tr3), torType);
-					// Calculate TroundB
-					TimeCtrl_CalculateTimeGap(&(rttRecord->Tt2), &(rttRecord->Tr3), &(rttRecord->TroundB));
-				}
-				else
-				{
-					DBG_WARNING("RTT REQ-2 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set dopplerR3 and ReplayB to dummy value.\n");
-					rttFsmPtr->isR3Valid = false;
-					rttRecord->dopplerR3 = RTT_DOPPLER_NONE;
-					rttRecord->TroundB = RTT_TIME_NONE;
-				}
-				DBG_INFO("dopplerR3:%d.\n", rttRecord->dopplerR3);
-				DBG_INFO("Tr3-timeL:%u.\n", rttRecord->Tr3.frac_part);
-				DBG_INFO("Tr3-timeH:%u.\n", rttRecord->Tr3.int_part);
-				DBG_INFO("TroundB-timeL:%u.\n", rttRecord->TroundB.frac_part);
-				DBG_INFO("TroundB-timeH:%u.\n", rttRecord->TroundB.int_part);
-				RTT_StageUpdate(rttFsmPtr, RTT_RSP2);
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		case RTT_RSP2:
-			if (torType == L2_TOR_TX)
-			{
-				DBG_INFO("Prepare data for RTT RSP-2\n");
-				// Update Tt4
-				RTT_GetFrameStart(instPtr, &(rttRecord->Tt4), torType);
-				if (rttFsmPtr->isR3Valid)
-				{
-					// Calculate reply B
-					TimeCtrl_CalculateTimeGap(&(rttRecord->Tr3), &(rttRecord->Tt4), &(rttRecord->TreplyB));
-					// TODO: implement a time adjustment.
-				}
-				else
-				{
-					DBG_WARNING("RTT REQ-2 have not been received [Stage: %d].\n", rttFsmPtr->rttStage);
-					DBG_WARNING("Set ReplayB to dummy value.\n");
-					rttRecord->TreplyB = RTT_TIME_NONE;
-				}
-				DBG_INFO("Tt4-timeL:%u.\n", rttRecord->Tt4.frac_part);
-				DBG_INFO("Tt4-timeH:%u.\n", rttRecord->Tt4.int_part);
-				DBG_INFO("TreplyB-timeL:%u.\n", rttRecord->TreplyB.frac_part);
-				DBG_INFO("TreplyB-timeH:%u.\n", rttRecord->TreplyB.int_part);
-
-				// Prepare data for sending.
-				rttFsmPtr->timeStamp = rttRecord->TreplyB;
-				rttFsmPtr->doppler = rttRecord->dopplerR3;
-				RTT_StageUpdate(rttFsmPtr, RTT_REQ1);
-				DBG_INFO("RTT procedure end...\n");
-			}
-			else
-			{
-				DBG_INFO("RTT FSM remain current state [%d].\n", rttFsmPtr->rttStage);
-			}
-			break;
-		default:
-			DBG_ERROR("Unexpected RTT FSM stage [%d].\n", rttFsmPtr->rttStage);
-			break;
-		}
-	}
-	return SUCCESS;
-}
+}

datalink814_ge/src/main.c

@@ -49,7 +49,7 @@ L2_CONFIG l2Config = {
 	.phyInstPtr = NULL,
 	.tmcInstPtr = NULL};
 
-TIMECTRL_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig = {
 	.baseAddr = TIME_CONTROLLER_BASEADDR,
 	.reset = 10};
 
@@ -69,11 +69,11 @@ int SetupInterruptSystem(XScuGic *instPtr, uint32_t devId);
 void PhysicalIntr_Handler(void *callBackRef);
 void PeriodicPull_Handler(void *callBackRef);
 #ifdef _MPC_CTRL
-void MPC_IntrHandler(void *CallBackRef);
+void MPC_IntrHandler(void *callBackRef);
 #endif
 
 /*********************** Driver Instance Definitions **************************/
-TIMECTRL_INST *tmcInstPtr = NULL;
+TMC_INST *tmcInstPtr = NULL;
 PHY_INST *phyInstPtr = NULL;
 L2_INST *linkInstPtr = NULL;
 static XScuGic gicInst; // General interrupt controller intance
@@ -200,12 +200,12 @@ void MPC_PCIESentStart()
 /**
  * @brief   Handler of mater pc contrl interrupt.
  *
- * @param   CallBackRef A pointer to corresponding mpcInstPtr instance.
+ * @param   callBackRef A pointer to corresponding mpcInstPtr instance.
  *
  * @return  None.
  *
  ******************************************************************************/
-void MPC_IntrHandler(void *CallBackRef)
+void MPC_IntrHandler(void *callBackRef)
 {
 	MPC_MsgHandler(mpcInstPtr);
 }
@@ -215,20 +215,15 @@ void MPC_IntrHandler(void *CallBackRef)
 /**
  * @brief   Handler of physical layer interrupt.
  *
- * @param   CallBackRef A pointer to corresponding physical layer instance.
+ * @param   callBackRef A pointer to corresponding physical layer instance.
  *
  * @return  None.
  *
  ******************************************************************************/
 void PhysicalIntr_Handler(void *callBackRef)
 {
-	uint32_t GpioConfig = XGpio_DiscreteRead(&configGpio, 2);
-	if (L2_isDataAvail(linkInstPtr) == true)
-	{
-		GpioConfig ^= 0x00000001;
-	}
 	Phy_UpdateState(phyInstPtr);
-	if (phyInstPtr->TOR.curr == PHY_TOR_TX)
+	if (phyInstPtr->tor.curr == PHY_TOR_TX)
 	{
 		switch (phyInstPtr->frameType.curr)
 		{
@@ -260,7 +255,7 @@ void PhysicalIntr_Handler(void *callBackRef)
 			break;
 		}
 	}
-	if (phyInstPtr->TOR.last == PHY_TOR_RX && phyInstPtr->isFrameSync)
+	if (phyInstPtr->tor.last == PHY_TOR_RX && phyInstPtr->isFrameSync)
 	{
 		switch (phyInstPtr->frameType.last)
 		{
@@ -292,7 +287,6 @@ void PhysicalIntr_Handler(void *callBackRef)
 			break;
 		}
 	}
-	XGpio_DiscreteWrite(&configGpio, 2, GpioConfig);
 }
 
 /****************************************************************************/
@@ -307,7 +301,6 @@ void PhysicalIntr_Handler(void *callBackRef)
 void PeriodicPull_Handler(void *callBackRef)
 {
 	int32_t Status;
-
 	Status = Linklayer_Proc(linkInstPtr);
 	if (Status != SUCCESS)
 	{
@@ -337,7 +330,14 @@ void PeriodicPull_Handler(void *callBackRef)
 		mpcRecord->frame7CntLast = mpcRecord->frame7Recv;
 		mpcRecord->frame8CntLast = mpcRecord->frame8Recv;
 	}
-} // PhyIntr_Handler
+
+	uint32_t GpioConfig = XGpio_DiscreteRead(&configGpio, 2);
+	if (L2_isDataAvail(linkInstPtr) == true)
+	{
+		GpioConfig ^= 0x00000001;
+	}
+	XGpio_DiscreteWrite(&configGpio, 2, GpioConfig);
+} // PeriodicPull_Handler
 
 /*****************************************************************************/
 /**
@@ -449,12 +449,12 @@ int main(void)
 			if (linkInstPtr->buffSwitch == 0)
 			{
 				MPC_StateUpload(mpcInstPtr, linkInstPtr->mgmtMsgRecvBuff1, linkInstPtr->mgmtMsgRecvCnt1,
-								linkInstPtr->svcMsgRecvBuff1, linkInstPtr->svcMsgRecvCnt1, &(linkInstPtr->mgmtNetFSM->mgmtMsgLog));
+								linkInstPtr->svcMsgRecvBuff1, linkInstPtr->svcMsgRecvCnt1, &(linkInstPtr->mgmtFSM->mgmtMsgLog));
 			}
 			else
 			{
 				MPC_StateUpload(mpcInstPtr, linkInstPtr->mgmtMsgRecvBuff0, linkInstPtr->mgmtMsgRecvCnt0,
-								linkInstPtr->svcMsgRecvBuff0, linkInstPtr->svcMsgRecvCnt0, &(linkInstPtr->mgmtNetFSM->mgmtMsgLog));
+								linkInstPtr->svcMsgRecvBuff0, linkInstPtr->svcMsgRecvCnt0, &(linkInstPtr->mgmtFSM->mgmtMsgLog));
 			}
 		}
 	}

datalink814_ge/src/phy_ctrl/antenna.c

@@ -1,406 +0,0 @@
-/*****************************************************************************/
-/**
- * Description: Antenna configuration functions.
- *
- * Author: Fan Hao
- * Date: 2022-06-18 16:37
- * LastEditors: Fan Hao
- * LastEditTime: 2022-06-18 17:15
- * Revisions: Rev 0.0
- * History:
- * [2022-06-18]: Initial version.
- *
- * Copyright(c) 2022 Beijing Institute of Technology.
- * Lab of Communication and Networking
- *
- ******************************************************************************/
-#include <string.h>
-#include <stdint.h>
-#include <math.h>
-#include "phy_ctrl.h"
-#include "../error.h"
-
-#define ANT_PI 3.14159265358979323846
-#define ANT_COINFO_HEAD 0xAA
-#define ANT_COINFO_TAIL 0xCC
-
-#define CTRL_WORD_DEFAULT 0x00
-
-#define ANT_MODE_BEAM_MASK 0xF0
-#define ANT_MODE_NARROR_BEAM 0x00 // 8
-#define ANT_MODE_WIDE_BEAM_1 0x10 // 25
-#define ANT_MODE_WIDE_BEAM_2 0x20 // 60
-#define ANT_MODE_WIDE_BEAM_3 0x30 // 120
-
-#define ANT_MODE_HIGH_POWER 0x00
-#define ANT_MODE_LOWAPOWER 0x04
-#define ANT_MODE_STANDBY 0x0F
-#define ATN_MODE_DEFAULT (ANT_MODE_WIDE_BEAM_1 | ANT_MODE_LOWAPOWER)
-#define ATN_MODE_HIGH (ANT_MODE_WIDE_BEAM_1 | ANT_MODE_HIGH_POWER)
-
-#define DEFAULT_CENTRTAL_FREQ 0x06D7 // 26.25GHz
-
-#define RXTXMODE_RX 0x00
-#define RXTXMODE_TX 0x01
-
-#define CALIBRMODE_NORMAL 0x00
-#define CALIBRMODE_SINGLE_TR_CAL 0x01
-
-#define MODECTRL_DEFAULT 0x00
-
-uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS] = 
-{
-	0
-};
-
-uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS] = 
-{
-	1500
-};
-
-uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] = {
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400
-};
-
-uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] = 
-{
-	1500
-};
-
-uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] = 
-{ 
-	1500, 1600, 1700, 1800, 1900, 2000, 1500, 1600, 
-	1700, 1800, 1900 
-};
-
-uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] = 
-{
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 
-	2400
-};
-
-uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] = 
-{
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
-	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 
-	2400, 2400, 2400
-};
-
-uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] =
-{ 
-	1500, 1600, 1700, 1800, 1900, 2000, 1500, 1600, 
-	1700, 1800, 1900, 2000, 1500, 1600, 1700, 1800, 
-	1900, 2000, 1500, 1500
-};
-
-uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] = 
-{
-	500 , 600 , 700 , 800 , 900 , 1000, 500 , 600 , 
-	700 , 800 , 900 , 1000, 500 , 600 , 700 , 800 , 
-	900 , 1000, 500 , 500
-};
-
-// Pair by regex
-// Regex: ((\{\.oaxis = [0-9]+[ ,]+\.raxis = [0-9]+[ ]*\}, ){2})
-#if defined(PHY_BEAM_SET_PRESET)
-ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN] = {
-	{.oaxis = 0 , .raxis = 222}, {.oaxis = 10, .raxis = 85 },
-	{.oaxis = 14, .raxis = 307}, {.oaxis = 17, .raxis = 170},
-	{.oaxis = 19, .raxis = 32 }, {.oaxis = 21, .raxis = 255},
-	{.oaxis = 24, .raxis = 117}, {.oaxis = 25, .raxis = 340},
-	{.oaxis = 27, .raxis = 202}, {.oaxis = 29, .raxis = 65 },
-	{.oaxis = 31, .raxis = 287}, {.oaxis = 32, .raxis = 150},
-	{.oaxis = 34, .raxis = 12 }, {.oaxis = 35, .raxis = 235},
-	{.oaxis = 36, .raxis = 97 }, {.oaxis = 38, .raxis = 320},
-	{.oaxis = 39, .raxis = 182}, {.oaxis = 40, .raxis = 45 },
-	{.oaxis = 41, .raxis = 267}, {.oaxis = 43, .raxis = 130},
-	{.oaxis = 44, .raxis = 352}, {.oaxis = 45, .raxis = 215},
-	{.oaxis = 46, .raxis = 77 }, {.oaxis = 47, .raxis = 300},
-	{.oaxis = 48, .raxis = 162}, {.oaxis = 49, .raxis = 25 },
-	{.oaxis = 50, .raxis = 247}, {.oaxis = 51, .raxis = 110},
-	{.oaxis = 52, .raxis = 332}, {.oaxis = 53, .raxis = 195},
-	{.oaxis = 54, .raxis = 57 }, {.oaxis = 55, .raxis = 280},
-	{.oaxis = 56, .raxis = 142}, {.oaxis = 57, .raxis = 5  },
-	{.oaxis = 58, .raxis = 227}, {.oaxis = 59, .raxis = 90 },
-	{.oaxis = 60, .raxis = 312}
-};
-ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] = {
-	{.oaxis = 0 , .raxis = 222}, {.oaxis = 7 , .raxis = 85 },
-	{.oaxis = 10, .raxis = 307}, {.oaxis = 13, .raxis = 170},
-	{.oaxis = 15, .raxis = 32 }, {.oaxis = 17, .raxis = 255},
-	{.oaxis = 18, .raxis = 117}, {.oaxis = 20, .raxis = 340},
-	{.oaxis = 21, .raxis = 202}, {.oaxis = 22, .raxis = 65 },
-	{.oaxis = 24, .raxis = 287}, {.oaxis = 25, .raxis = 150},
-	{.oaxis = 26, .raxis = 12 }, {.oaxis = 27, .raxis = 235},
-	{.oaxis = 28, .raxis = 97 }, {.oaxis = 29, .raxis = 320},
-	{.oaxis = 30, .raxis = 182}, {.oaxis = 31, .raxis = 45 },
-	{.oaxis = 32, .raxis = 267}, {.oaxis = 33, .raxis = 130},
-	{.oaxis = 34, .raxis = 352}, {.oaxis = 34, .raxis = 215},
-	{.oaxis = 35, .raxis = 77 }, {.oaxis = 36, .raxis = 300},
-	{.oaxis = 37, .raxis = 162}, {.oaxis = 38, .raxis = 25 },
-	{.oaxis = 38, .raxis = 247}, {.oaxis = 39, .raxis = 110},
-	{.oaxis = 40, .raxis = 332}, {.oaxis = 41, .raxis = 195},
-	{.oaxis = 41, .raxis = 57 }, {.oaxis = 42, .raxis = 280},
-	{.oaxis = 43, .raxis = 142}, {.oaxis = 44, .raxis = 5  },
-	{.oaxis = 44, .raxis = 227}, {.oaxis = 45, .raxis = 90 },
-	{.oaxis = 46, .raxis = 312}, {.oaxis = 46, .raxis = 175},
-	{.oaxis = 47, .raxis = 37 }, {.oaxis = 48, .raxis = 260},
-	{.oaxis = 48, .raxis = 122}, {.oaxis = 49, .raxis = 345},
-	{.oaxis = 49, .raxis = 207}, {.oaxis = 50, .raxis = 70 },
-	{.oaxis = 51, .raxis = 292}, {.oaxis = 51, .raxis = 155},
-	{.oaxis = 52, .raxis = 17 }, {.oaxis = 53, .raxis = 240},
-	{.oaxis = 53, .raxis = 102}, {.oaxis = 54, .raxis = 325},
-	{.oaxis = 54, .raxis = 187}, {.oaxis = 55, .raxis = 50 },
-	{.oaxis = 55, .raxis = 272}, {.oaxis = 56, .raxis = 135},
-	{.oaxis = 57, .raxis = 357}, {.oaxis = 57, .raxis = 220},
-	{.oaxis = 58, .raxis = 82 }, {.oaxis = 58, .raxis = 305},
-	{.oaxis = 59, .raxis = 167}, {.oaxis = 59, .raxis = 30 },
-	{.oaxis = 60, .raxis = 252}
-};
-#elif defined(PHY_BEAM_SET_PRESET_LSX)
-ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN] = {
-	{.oaxis = 0  , .raxis =2225},{.oaxis = 96 , .raxis =850 },
-	{.oaxis = 135, .raxis =3075},{.oaxis = 166, .raxis =1700},
-	{.oaxis = 192, .raxis =325 },{.oaxis = 215, .raxis =2550},
-	{.oaxis = 236, .raxis =1174},{.oaxis = 255, .raxis =3399},
-	{.oaxis = 273, .raxis =2024},{.oaxis = 290, .raxis =649 },
-	{.oaxis = 306, .raxis =2874},{.oaxis = 321, .raxis =1499},
-	{.oaxis = 336, .raxis =124 },{.oaxis = 350, .raxis =2349},
-	{.oaxis = 363, .raxis =974 },{.oaxis = 377, .raxis =3199},
-	{.oaxis = 389, .raxis =1824},{.oaxis = 402, .raxis =449 },
-	{.oaxis = 414, .raxis =2674},{.oaxis = 426, .raxis =1298},
-	{.oaxis = 438, .raxis =3523},{.oaxis = 449, .raxis =2148},
-	{.oaxis = 460, .raxis =773 },{.oaxis = 471, .raxis =2998},
-	{.oaxis = 482, .raxis =1623},{.oaxis = 492, .raxis =248 },
-	{.oaxis = 503, .raxis =2473},{.oaxis = 513, .raxis =1098},
-	{.oaxis = 523, .raxis =3323},{.oaxis = 533, .raxis =1948},
-	{.oaxis = 543, .raxis =573 },{.oaxis = 553, .raxis =2798},
-	{.oaxis = 563, .raxis =1422},{.oaxis = 572, .raxis =47  },
-	{.oaxis = 581, .raxis =2272},{.oaxis = 591, .raxis =897 },
-	{.oaxis = 600, .raxis =3122}
-};
-ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] = {
-	{.oaxis = 0  , .raxis =2225},{.oaxis = 74 , .raxis =850 },
-	{.oaxis = 105, .raxis =3075},{.oaxis = 128, .raxis =1700},
-	{.oaxis = 148, .raxis =325 },{.oaxis = 166, .raxis =2550},
-	{.oaxis = 182, .raxis =1174},{.oaxis = 197, .raxis =3399},
-	{.oaxis = 210, .raxis =2024},{.oaxis = 223, .raxis =649 },
-	{.oaxis = 236, .raxis =2874},{.oaxis = 247, .raxis =1499},
-	{.oaxis = 258, .raxis =124 },{.oaxis = 269, .raxis =2349},
-	{.oaxis = 280, .raxis =974 },{.oaxis = 290, .raxis =3199},
-	{.oaxis = 299, .raxis =1824},{.oaxis = 309, .raxis =449 },
-	{.oaxis = 318, .raxis =2674},{.oaxis = 327, .raxis =1298},
-	{.oaxis = 336, .raxis =3523},{.oaxis = 344, .raxis =2148},
-	{.oaxis = 352, .raxis =773 },{.oaxis = 361, .raxis =2998},
-	{.oaxis = 369, .raxis =1623},{.oaxis = 377, .raxis =248 },
-	{.oaxis = 384, .raxis =2473},{.oaxis = 392, .raxis =1098},
-	{.oaxis = 399, .raxis =3323},{.oaxis = 407, .raxis =1948},
-	{.oaxis = 414, .raxis =573 },{.oaxis = 421, .raxis =2798},
-	{.oaxis = 428, .raxis =1422},{.oaxis = 435, .raxis =47  },
-	{.oaxis = 442, .raxis =2272},{.oaxis = 449, .raxis =897 },
-	{.oaxis = 456, .raxis =3122},{.oaxis = 462, .raxis =1747},
-	{.oaxis = 469, .raxis =372 },{.oaxis = 475, .raxis =2597},
-	{.oaxis = 482, .raxis =1222},{.oaxis = 488, .raxis =3447},
-	{.oaxis = 495, .raxis =2072},{.oaxis = 501, .raxis =697 },
-	{.oaxis = 507, .raxis =2922},{.oaxis = 513, .raxis =1546},
-	{.oaxis = 519, .raxis =171 },{.oaxis = 525, .raxis =2396},
-	{.oaxis = 531, .raxis =1021},{.oaxis = 537, .raxis =3246},
-	{.oaxis = 543, .raxis =1871},{.oaxis = 549, .raxis =496 },
-	{.oaxis = 555, .raxis =2721},{.oaxis = 561, .raxis =1346},
-	{.oaxis = 566, .raxis =3571},{.oaxis = 572, .raxis =2196},
-	{.oaxis = 578, .raxis =821 },{.oaxis = 583, .raxis =3045},
-	{.oaxis = 589, .raxis =1670},{.oaxis = 594, .raxis =295 },
-	{.oaxis = 600, .raxis =2520}
-};
-#else
-PHY_ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN]  = 
-{
-	0
-};
-PHY_ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] = 
-{
-	0
-};
-#endif
-/*****************************************************************************/
-/**
- * @brief
- *
- * @param   antCoinfoPtr
- *
- * @return
- *
- ******************************************************************************/
-int32_t Phy_AntCoinfoInit(PHY_ANT_CONFIG *antCoinfoPtr)
-{
-	if (antCoinfoPtr == NULL)
-	{
-		return FAILURE;
-	}
-	antCoinfoPtr->head = ANT_COINFO_HEAD;
-	antCoinfoPtr->tail = ANT_COINFO_TAIL;
-	antCoinfoPtr->ctrlWord = 0x00;
-#ifdef ANT_HIGH_POWER
-	antCoinfoPtr->antMode = ATN_MODE_HIGH;
-#else
-	antCoinfoPtr->antMode = ATN_MODE_DEFAULT;
-#endif
-
-	// FIXME: Dummy default value.
-	// off axis angle setting
-	antCoinfoPtr->oaxis[0] = 0;
-	antCoinfoPtr->oaxis[1] = 0;
-	// round axis angle setting
-	antCoinfoPtr->raxis[0] = 0;
-	antCoinfoPtr->raxis[1] = 0;
-	// ***********************
-
-	antCoinfoPtr->antFreq[0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
-	antCoinfoPtr->antFreq[1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
-
-	// FIXME: Dummy default value.
-	// trSelect
-	antCoinfoPtr->trSlect = 0;
-	// Antenna attenuation setting
-	antCoinfoPtr->antAtt = 20;
-	// phase setting
-	antCoinfoPtr->phase = 0;
-	// ***********************
-
-	antCoinfoPtr->rxtxMode = RXTXMODE_RX;
-	antCoinfoPtr->calibrMode = CALIBRMODE_NORMAL;
-
-	// FIXME: Dummy default value.
-	// DD enable
-	antCoinfoPtr->ddEn = 0;
-	// DD mgc
-	antCoinfoPtr->ddMgc = 0;
-	// RF mode control
-	antCoinfoPtr->rfCtrl = 0;
-	// RF MGC control
-	antCoinfoPtr->rfMgc = 0;
-	// RF channel 1&2 calibration mgc
-	antCoinfoPtr->rf12CalMgc = 0;
-	// RF channel 2&3 calibration mgc
-	antCoinfoPtr->rf34CalMgc = 0;
-	// Receive channel 1 MGC
-	antCoinfoPtr->rcv1Mgc = 0;
-	// Receive channel 2 MGC
-	antCoinfoPtr->rcv2Mgc = 0;
-	// Receive channel 3 MGC
-	antCoinfoPtr->rcv3Mgc = 0;
-	// Receive channel 4 MGC
-	antCoinfoPtr->rcv4Mgc = 0;
-	// ***********************
-
-	memset(antCoinfoPtr->dummy, 0x00, sizeof(antCoinfoPtr->dummy));
-
-	return SUCCESS;
-}
-
-int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo)
-{
-	if (instPtr->beamWd.next == ANT_BEAM_8)
-	{
-		if (beamNo >= NUM_ANT_NRRW_PATTERN)
-		{
-			return FAILURE;
-		}
-		else
-		{
-			instPtr->beamNo.next = beamNo;
-			instPtr->antCoinfoPtr.oaxis[1] = (uint8_t)(antNrrwPattern[beamNo].oaxis);
-			instPtr->antCoinfoPtr.oaxis[0] = (uint8_t)((antNrrwPattern[beamNo].oaxis) >> 8);
-			instPtr->antCoinfoPtr.raxis[1] = (uint8_t)(antNrrwPattern[beamNo].raxis);
-			instPtr->antCoinfoPtr.raxis[0] = (uint8_t)((antNrrwPattern[beamNo].raxis) >> 8);
-			return SUCCESS;
-		}
-	}
-	else if (instPtr->beamWd.next == ANT_BEAM_25)
-	{
-		if (beamNo >= NUM_ANT_SUBNRRW_PATTERN)
-		{
-			return FAILURE;
-		}
-		else
-		{
-			instPtr->beamNo.next = beamNo;
-			instPtr->antCoinfoPtr.oaxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis);
-			instPtr->antCoinfoPtr.oaxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].oaxis) >> 8);
-			instPtr->antCoinfoPtr.raxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].raxis);
-			instPtr->antCoinfoPtr.raxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].raxis) >> 8);
-			return SUCCESS;
-		}
-	}
-	else
-	{
-		// Beam number assign not support.
-		// Assign default angle (0,0)
-		instPtr->beamNo.next = 0;
-		instPtr->antCoinfoPtr.oaxis[1] = 0;
-		instPtr->antCoinfoPtr.oaxis[0] = 0;
-		instPtr->antCoinfoPtr.raxis[1] = 0;
-		instPtr->antCoinfoPtr.raxis[0] = 0;
-		DBG_WARNING("Using default beam number...");
-		return SUCCESS;
-	}
-}
-
-int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth)
-{
-	uint8_t beamConfig = instPtr->antCoinfoPtr.antMode & (~ANT_MODE_BEAM_MASK);
-	switch (beamWidth)
-	{
-	case ANT_BEAM_120:
-		beamConfig |= ANT_MODE_WIDE_BEAM_3;
-		break;
-	case ANT_BEAM_60:
-		beamConfig |= ANT_MODE_WIDE_BEAM_2;
-		break;
-	case ANT_BEAM_25:
-		beamConfig |= ANT_MODE_WIDE_BEAM_1;
-		break;
-	case ANT_BEAM_8:
-		beamConfig |= ANT_MODE_NARROR_BEAM;
-		break;
-	default:
-		DBG_ERROR("Beam width code: 0x%08X is illegal.\n\r", beamWidth);
-		return EPARAM;
-		break;
-	}
-	instPtr->antCoinfoPtr.antMode = beamConfig;
-	instPtr->beamWd.next = beamWidth;
-	return SUCCESS;
-}
-
-// Common version radius double input
-int32_t Phy_SetBeamAngle(PHY_INST *instPtr, double offAx, double rndAx)
-{
-	uint16_t offAxDeg = 0;
-	uint16_t rndAxDeg = 0;
-	offAxDeg = (offAx > 0) ? (((int32_t)(offAx * 180 / ANT_PI)) % 360) : (((int32_t)(offAx * 180 / ANT_PI)) % 360 + 360);
-	rndAxDeg = (rndAx > 0) ? (((int32_t)(rndAx * 180 / ANT_PI)) % 360) : (((int32_t)(rndAx * 180 / ANT_PI)) % 360 + 360);
-	if (offAxDeg > 60)
-	{
-		DBG_ERROR("Angle out of range, off axis angle: %u(should be 0~60), round axis angle: %u(should be 0~360).",
-				  offAxDeg, rndAxDeg);
-		return EPARAM;
-	}
-	offAxDeg = offAxDeg * 10;
-	rndAxDeg = rndAxDeg * 10;
-	instPtr->antCoinfoPtr.oaxis[1] = (uint8_t)offAxDeg;
-	instPtr->antCoinfoPtr.oaxis[0] = (uint8_t)(offAxDeg >> 8);
-	instPtr->antCoinfoPtr.raxis[1] = (uint8_t)rndAxDeg;
-	instPtr->antCoinfoPtr.raxis[0] = (uint8_t)(rndAxDeg >> 8);
-	return SUCCESS;
-}

datalink814_ge/src/phy_ctrl/phy_antenna.c

@@ -0,0 +1,446 @@
+/*****************************************************************************/
+/**
+ * Description: Antenna configuration functions.
+ *
+ * Author: Fan Hao
+ * Date: 2022-06-18 16:37
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-06-18 17:15
+ * Revisions: Rev 0.0
+ * History:
+ * [2022-06-18]: Initial version.
+ *
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+#include <string.h>
+#include <stdint.h>
+#include <math.h>
+#include "phy_ctrl.h"
+#include "../error.h"
+
+#define ANT_PI 3.14159265358979323846
+
+#define ANT_COINFO_HEAD 0xAA
+#define ANT_COINFO_TAIL 0xCC
+
+#define CTRL_WORD_DEFAULT 0x00
+
+#define ANT_MODE_BEAM_MASK 0xF0
+#define ANT_BEAM_NARROR 0x00	  // 8
+#define ANT_BEAM_SUBNARROR_0 0x10 // 25
+#define ANT_BEAM_SUBNARROR_1 0x20 // 60
+#define ANT_BEAM_WIDE 0x30		  // 120
+
+#define ANT_MODE_POWER_MASK 0x0F
+#define ANT_POWER_FULL 0x00
+#define ANT_POWER_LOW 0x04
+#define ANT_POWER_STANDBY 0x0F
+#define ATN_MODE_SILENT (ANT_BEAM_SUBNARROR_0 | ANT_POWER_STANDBY)
+#define ATN_MODE_LOWPOWER (ANT_BEAM_SUBNARROR_0 | ANT_POWER_LOW)
+#define ATN_MODE_FULLPOWER (ANT_BEAM_SUBNARROR_0 | ANT_POWER_FULL)
+#define ATN_MODE_DEFAULT ATN_MODE_SILENT
+
+#define ATN_ATTENUATION_MAX 0x1F
+#define ATN_ATTENUATION_SKIP 0xFF
+
+#define DEFAULT_CARRIER_FREQ 0x06D7 // 26.25GHz
+
+#define TORMODE_RX 0x00
+#define TORMODE_TX 0x01
+#define TORMODE_DEFAULT 0x00
+
+#define CALIMODE_NORMAL 0x00
+#define CALIMODE_SINGLE_TR_CAL 0x01
+
+#define RF_CTRL_DEFAULT 0x00
+
+// Pair by regex
+// Regex: (([0-9]+, ){8})
+uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS] =
+{
+	0
+};
+
+uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS] =
+{
+	1500
+};
+
+uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] =
+{
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400
+};
+
+uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] =
+{
+	1500
+};
+
+uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] =
+{
+	1500, 1600, 1700, 1800, 1900, 2000, 1500, 1600,
+	1700, 1800, 1900
+};
+
+uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] =
+{
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400
+};
+
+uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] =
+{
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+	2400, 2400, 2400
+};
+
+uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] =
+{
+	1500, 1600, 1700, 1800, 1900, 2000, 1500, 1600,
+	1700, 1800, 1900, 2000, 1500, 1600, 1700, 1800,
+	1900, 2000, 1500, 1500
+};
+
+uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] =
+{
+	500 , 600 , 700 , 800 , 900 , 1000, 500 , 600 ,
+	700 , 800 , 900 , 1000, 500 , 600 , 700 , 800 ,
+	900 , 1000, 500 , 500
+};
+
+// Pair by regex
+// Regex: ((\{\.oaxis = [0-9]+[ ,]+\.raxis = [0-9]+[ ]*\}, ){2})
+#if defined(PHY_BEAM_SET_PRESET)
+ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN] = {
+	{.oaxis = 0  , .raxis =2225},{.oaxis = 96 , .raxis =850 },
+	{.oaxis = 135, .raxis =3075},{.oaxis = 166, .raxis =1700},
+	{.oaxis = 192, .raxis =325 },{.oaxis = 215, .raxis =2550},
+	{.oaxis = 236, .raxis =1174},{.oaxis = 255, .raxis =3399},
+	{.oaxis = 273, .raxis =2024},{.oaxis = 290, .raxis =649 },
+	{.oaxis = 306, .raxis =2874},{.oaxis = 321, .raxis =1499},
+	{.oaxis = 336, .raxis =124 },{.oaxis = 350, .raxis =2349},
+	{.oaxis = 363, .raxis =974 },{.oaxis = 377, .raxis =3199},
+	{.oaxis = 389, .raxis =1824},{.oaxis = 402, .raxis =449 },
+	{.oaxis = 414, .raxis =2674},{.oaxis = 426, .raxis =1298},
+	{.oaxis = 438, .raxis =3523},{.oaxis = 449, .raxis =2148},
+	{.oaxis = 460, .raxis =773 },{.oaxis = 471, .raxis =2998},
+	{.oaxis = 482, .raxis =1623},{.oaxis = 492, .raxis =248 },
+	{.oaxis = 503, .raxis =2473},{.oaxis = 513, .raxis =1098},
+	{.oaxis = 523, .raxis =3323},{.oaxis = 533, .raxis =1948},
+	{.oaxis = 543, .raxis =573 },{.oaxis = 553, .raxis =2798},
+	{.oaxis = 563, .raxis =1422},{.oaxis = 572, .raxis =47  },
+	{.oaxis = 581, .raxis =2272},{.oaxis = 591, .raxis =897 },
+	{.oaxis = 600, .raxis =3122}
+};
+ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN] = {
+	{.oaxis = 0  , .raxis =2225},{.oaxis = 74 , .raxis =850 },
+	{.oaxis = 105, .raxis =3075},{.oaxis = 128, .raxis =1700},
+	{.oaxis = 148, .raxis =325 },{.oaxis = 166, .raxis =2550},
+	{.oaxis = 182, .raxis =1174},{.oaxis = 197, .raxis =3399},
+	{.oaxis = 210, .raxis =2024},{.oaxis = 223, .raxis =649 },
+	{.oaxis = 236, .raxis =2874},{.oaxis = 247, .raxis =1499},
+	{.oaxis = 258, .raxis =124 },{.oaxis = 269, .raxis =2349},
+	{.oaxis = 280, .raxis =974 },{.oaxis = 290, .raxis =3199},
+	{.oaxis = 299, .raxis =1824},{.oaxis = 309, .raxis =449 },
+	{.oaxis = 318, .raxis =2674},{.oaxis = 327, .raxis =1298},
+	{.oaxis = 336, .raxis =3523},{.oaxis = 344, .raxis =2148},
+	{.oaxis = 352, .raxis =773 },{.oaxis = 361, .raxis =2998},
+	{.oaxis = 369, .raxis =1623},{.oaxis = 377, .raxis =248 },
+	{.oaxis = 384, .raxis =2473},{.oaxis = 392, .raxis =1098},
+	{.oaxis = 399, .raxis =3323},{.oaxis = 407, .raxis =1948},
+	{.oaxis = 414, .raxis =573 },{.oaxis = 421, .raxis =2798},
+	{.oaxis = 428, .raxis =1422},{.oaxis = 435, .raxis =47  },
+	{.oaxis = 442, .raxis =2272},{.oaxis = 449, .raxis =897 },
+	{.oaxis = 456, .raxis =3122},{.oaxis = 462, .raxis =1747},
+	{.oaxis = 469, .raxis =372 },{.oaxis = 475, .raxis =2597},
+	{.oaxis = 482, .raxis =1222},{.oaxis = 488, .raxis =3447},
+	{.oaxis = 495, .raxis =2072},{.oaxis = 501, .raxis =697 },
+	{.oaxis = 507, .raxis =2922},{.oaxis = 513, .raxis =1546},
+	{.oaxis = 519, .raxis =171 },{.oaxis = 525, .raxis =2396},
+	{.oaxis = 531, .raxis =1021},{.oaxis = 537, .raxis =3246},
+	{.oaxis = 543, .raxis =1871},{.oaxis = 549, .raxis =496 },
+	{.oaxis = 555, .raxis =2721},{.oaxis = 561, .raxis =1346},
+	{.oaxis = 566, .raxis =3571},{.oaxis = 572, .raxis =2196},
+	{.oaxis = 578, .raxis =821 },{.oaxis = 583, .raxis =3045},
+	{.oaxis = 589, .raxis =1670},{.oaxis = 594, .raxis =295 },
+	{.oaxis = 600, .raxis =2520}
+};
+#else
+PHY_ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN]  =
+{
+	0
+};
+PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN] =
+{
+	0
+};
+#endif
+/*****************************************************************************/
+/**
+ * @brief
+ *
+ * @param   antConfig
+ *
+ * @return
+ *
+ ******************************************************************************/
+void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig)
+{
+	ASSERT(antConfig != NULL);
+	antConfig->ctrlWord = CTRL_WORD_DEFAULT;
+	antConfig->antMode = ATN_MODE_DEFAULT;
+
+	// FIXME: Dummy default value.
+	// off axis angle setting
+	antConfig->oaxis[0] = 0;
+	antConfig->oaxis[1] = 0;
+	// round axis angle setting
+	antConfig->raxis[0] = 0;
+	antConfig->raxis[1] = 0;
+
+	antConfig->antFreq[0] = (uint8_t)(DEFAULT_CARRIER_FREQ);
+	antConfig->antFreq[1] = (uint8_t)(DEFAULT_CARRIER_FREQ >> 8);
+
+	// FIXME: Dummy default value.
+	// trSelect
+	antConfig->trSelect = 0;
+	// Antenna attenuation setting
+	antConfig->antAtt = 20;
+	// phase setting
+	antConfig->phase = 0;
+
+	antConfig->torMode = TORMODE_DEFAULT;
+	antConfig->caliMode = CALIMODE_NORMAL;
+	antConfig->antReserved = 0x00;
+	// ***********************
+
+	// FIXME: Dummy default value.
+	// RF mode control
+	antConfig->rfCtrl = RF_CTRL_DEFAULT;
+	// RF frequency
+	antConfig->rfFreq[0] = (uint8_t)(DEFAULT_CARRIER_FREQ);
+	antConfig->rfFreq[1] = (uint8_t)(DEFAULT_CARRIER_FREQ >> 8);
+	// RF MGC control
+	antConfig->rfTxMgc = 0;
+	// RF channel 1&2 calibration mgc
+	antConfig->rf12CalMgc = 0;
+	// RF channel 2&3 calibration mgc
+	antConfig->rf34CalMgc = 0;
+	// Receive channel 1-4 MGC
+	antConfig->rfRxMgc = 0;
+	antConfig->rfReserved0 = 0x00;
+	antConfig->rfReserved1 = 0x00;
+}
+
+/*****************************************************************************/
+/**
+ * @brief	Update antenna power mode setting
+ *
+ * @param   instPtr	pointer to physical layer instance
+ * @param   mode	new antenna mode
+ *
+ * @return	None.
+ *
+ ******************************************************************************/
+void Phy_AntConfigMode(PHY_INST *instPtr, PHY_ANT_MODE mode)
+{
+	ASSERT(instPtr != NULL);
+	uint8_t config = instPtr->antConfig.antMode & ANT_MODE_BEAM_MASK;
+	switch (mode)
+	{
+	case PHY_ANT_MODE_STANDBY:
+		config |= ANT_POWER_STANDBY;
+		break;
+	case PHY_ANT_MODE_POWER_LOW:
+		config |= ANT_POWER_LOW;
+		break;
+	case PHY_ANT_MODE_POWER_FULL:
+		config |= ANT_POWER_FULL;
+		break;
+	default:
+		DBG_ERROR("Unknown antenna mode: %" PRIu8 ", remain previous mode.\n", mode);
+		return;
+	}
+	instPtr->antConfig.antMode = config;
+}
+
+/*****************************************************************************/
+/**
+ * @brief	Update antenna attenuation
+ *
+ * @param   instPtr	pointer to physical layer instance
+ * @param   rxAtt	rx attenuation
+ * @param   txAtt	tx attenuation
+ *
+ * @return	None.
+ *
+ ******************************************************************************/
+void Phy_AntConfigAttenuation(PHY_INST *instPtr, uint8_t rxAtt, uint8_t txAtt)
+{
+	ASSERT(instPtr != NULL);
+	if(rxAtt <= ATN_ATTENUATION_MAX)
+	{
+		instPtr->antConfig.rfRxMgc = rxAtt;
+	}
+	else if(rxAtt != ATN_ATTENUATION_SKIP)
+	{
+		DBG_ERROR("RX Attenuation exceeds range, %u.", rxAtt);
+	}
+
+	if(txAtt <= ATN_ATTENUATION_MAX)
+	{
+		instPtr->antConfig.rfTxMgc = txAtt;
+	}
+	else if(txAtt != ATN_ATTENUATION_SKIP)
+	{
+		DBG_ERROR("TX Attenuation exceeds range, %u.", txAtt);
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief	Update antenna point direction using predefined beam table
+ *
+ * @param   instPtr	pointer to physical layer instance
+ * @param   beamNo	new beam index
+ *
+ * @return	SUCCESS.
+ * 			FAILURE beamNo exceeds the table size
+ *
+ ******************************************************************************/
+int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo, PHY_ANT_BEAM_WIDTH beamWidth)
+{
+	if (beamWidth == PHY_ANT_BEAM_16)
+	{
+		if (beamNo >= L1_NUM_ANT_NRRW_PATTERN)
+		{
+			return FAILURE;
+		}
+		else
+		{
+			instPtr->beamNo.next = beamNo;
+			instPtr->antConfig.oaxis[1] = (uint8_t)(antNrrwPattern[beamNo].oaxis);
+			instPtr->antConfig.oaxis[0] = (uint8_t)((antNrrwPattern[beamNo].oaxis) >> 8);
+			instPtr->antConfig.raxis[1] = (uint8_t)(antNrrwPattern[beamNo].raxis);
+			instPtr->antConfig.raxis[0] = (uint8_t)((antNrrwPattern[beamNo].raxis) >> 8);
+			return SUCCESS;
+		}
+	}
+	else if (beamWidth == PHY_ANT_BEAM_25)
+	{
+		if (beamNo >= L1_NUM_ANT_SUBNRRW_PATTERN)
+		{
+			return FAILURE;
+		}
+		else
+		{
+			instPtr->beamNo.next = beamNo;
+			instPtr->antConfig.oaxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis);
+			instPtr->antConfig.oaxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].oaxis) >> 8);
+			instPtr->antConfig.raxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].raxis);
+			instPtr->antConfig.raxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].raxis) >> 8);
+			return SUCCESS;
+		}
+	}
+	else if(beamWidth == PHY_ANT_BEAM_120)
+	{
+		// Beam number assign not support.
+		// Assign default angle (0,0)
+		instPtr->beamNo.next = 0;
+		instPtr->antConfig.oaxis[1] = 0;
+		instPtr->antConfig.oaxis[0] = 0;
+		instPtr->antConfig.raxis[1] = 0;
+		instPtr->antConfig.raxis[0] = 0;
+		DBG_WARNING("Using default beam number...\n");
+		return SUCCESS;
+	}
+	else
+	{
+		return FAILURE;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief	Update antenna beam width setting
+ *
+ * @param   instPtr		pointer to physical layer instance
+ * @param   beamWidth	new beam width
+ *
+ * @return	SUCCESS.
+ * 			EPARAM
+ *
+ ******************************************************************************/
+int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth)
+{
+	uint8_t beamConfig = instPtr->antConfig.antMode & (~ANT_MODE_BEAM_MASK);
+	switch (beamWidth)
+	{
+	case PHY_ANT_BEAM_120:
+		beamConfig |= ANT_BEAM_WIDE;
+		break;
+	case PHY_ANT_BEAM_60:
+		beamConfig |= ANT_BEAM_SUBNARROR_1;
+		break;
+	case PHY_ANT_BEAM_25:
+		beamConfig |= ANT_BEAM_SUBNARROR_0;
+		break;
+	case PHY_ANT_BEAM_16:
+		beamConfig |= ANT_BEAM_NARROR;
+		break;
+	default:
+		DBG_ERROR("Beam width code: 0x%08X is illegal.\n", beamWidth);
+		return EPARAM;
+		break;
+	}
+	instPtr->antConfig.antMode = beamConfig;
+	instPtr->beamWd.next = beamWidth;
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief	Set antenna to a specific direction
+ *
+ * @param   instPtr	pointer to physical layer instance
+ * @param   offAx	elevation angle
+ * @param   rndAx	azimuth angle
+ *
+ * @return	SUCCESS.
+ * 			EPARAM - the direction is exceeds predefined range
+ *
+ ******************************************************************************/
+int32_t Phy_SetBeamAngle(PHY_INST *instPtr, double offAx, double rndAx)
+{
+	uint16_t offAxDeg = 0;
+	uint16_t rndAxDeg = 0;
+	offAxDeg = (offAx >= 0) ? (((int32_t)(offAx * 180 / ANT_PI)) % 360) : (((int32_t)(offAx * 180 / ANT_PI)) % 360 + 360);
+	rndAxDeg = (rndAx >= 0) ? (((int32_t)(rndAx * 180 / ANT_PI)) % 360) : (((int32_t)(rndAx * 180 / ANT_PI)) % 360 + 360);
+	if (offAxDeg > 60)
+	{
+		DBG_ERROR("Angle out of range, off axis angle: %u (should be 0~60), round axis angle: %u (should be 0~360).\n",
+				  offAxDeg, rndAxDeg);
+		return EPARAM;
+	}
+	offAxDeg = offAxDeg * 10;
+	rndAxDeg = rndAxDeg * 10;
+	instPtr->antConfig.oaxis[1] = (uint8_t)offAxDeg;
+	instPtr->antConfig.oaxis[0] = (uint8_t)(offAxDeg >> 8);
+	instPtr->antConfig.raxis[1] = (uint8_t)rndAxDeg;
+	instPtr->antConfig.raxis[0] = (uint8_t)(rndAxDeg >> 8);
+	return SUCCESS;
+}

datalink814_ge/src/phy_ctrl/phy_ctrl.c

@@ -30,7 +30,30 @@
 #ifndef EMULATION
 #include "xbram.h"
 #endif
+
 /************************** Constant Definitions *****************************/
+#define L1_FRAME_LEN_MAX (8192 / 8)			// byte
+#define L1_FRAME_2KBPS_20MS_LEN 0			// byte
+#define L1_FRAME_2KBPS_100MS_LEN (312 / 8)	// byte
+#define L1_FRAME_10KBPS_10MS_LEN 0			// byte
+#define L1_FRAME_10KBPS_20MS_LEN (232 / 8)	// byte
+#define L1_FRAME_40KBPS_20MS_LEN (2152 / 8) // byte
+#define L1_FRAME_40KBPS_10MS_LEN (712 / 8)	// byte
+#define L1_FRAME_200KBPS_5MS_LEN (2040 / 8) // byte
+#define L1_FRAME_1M2BPS_5MS_LEN (8176 / 8)	// byte
+
+#define L1_FRAME_2KBPS_20MS_COMP 1841158  // *10ns(Timer_L)
+#define L1_FRAME_2KBPS_100MS_COMP 1841158 // *10ns(Timer_L)
+#define L1_FRAME_10KBPS_10MS_COMP 850950  // *10ns(Timer_L)
+#define L1_FRAME_10KBPS_20MS_COMP 850950  // *10ns(Timer_L)
+#define L1_FRAME_40KBPS_20MS_COMP 111485  // *10ns(Timer_L)
+#define L1_FRAME_40KBPS_10MS_COMP 111485  // *10ns(Timer_L)
+#define L1_FRAME_200KBPS_5MS_COMP 22493	  // *10ns(Timer_L)
+#define L1_FRAME_1M2BPS_5MS_COMP 22493	  // *10ns(Timer_L)
+
+#define ANT_CONFIG_LEN 32 // bytes
+#define L1_ANTCONFIG_MAX_LEN 8192
+
 /***************** Macros (Inline Functions) Definitions *********************/
 /************************** Function Prototypes ******************************/
 static void Phy_RcdShift(PHY_RCD *rcd, int32_t netxVal);
@@ -39,7 +62,19 @@ static int32_t Phy_SetSendData(PHY_INST *instPtr, L1_FRAME_TYPE frameType, uint8
 /**************************** Type Definitions *******************************/
 
 /************************** Variable Definitions *****************************/
+extern uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS];
+extern uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS];
+extern uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS];
+extern uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS];
+extern uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS];
+extern uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS];
+extern uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS];
 
+extern uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
+extern uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
+
+extern PHY_ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN];
+extern PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN];
 /*****************************************************************************/
 /**
  * @brief   Setup data will be sent in next slot.
@@ -63,7 +98,7 @@ static int32_t Phy_SetSendData(PHY_INST *instPtr, L1_FRAME_TYPE frameType, uint8
 		DBG_ERROR("Invalid frame length.\n");
 		return EPARAM;
 	}
-	instPtr->sendDataOffset = (TXRXDATA_MAX_LEN >> 1) - instPtr->sendDataOffset;
+	instPtr->sendDataOffset = (L1_TXRXDATA_MAX_LEN >> 1) - instPtr->sendDataOffset;
 	memcpy((uint8_t *)(instPtr->sendDataAddr + instPtr->sendDataOffset), dataBuff, frameLen);
 
 	sendCmd = frameLen & SEND_DATA_CMD_LEN_MASK;
@@ -155,11 +190,27 @@ inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
 	{
 		return L1_NONE_FRAME;
 	}
-	int32_t frame_type = (PhyRead(instPtr, PHY_MODE_CTRL) & PHY_MODE_CTRL_FRAME_MASK) >> PHY_MODE_CTRL_FRAME_SHIFT;
-	if (frame_type < L1_1M2BPS_5MS_FRAME)
-		return frame_type;
-	else
+	int32_t frame_type = (PhyRead(instPtr, COASE_FREQEST) & COASE_TYPE_MASK);
+	switch (frame_type) {
+		case COASE_TYPE_2KBPS_20MS:
+		return L1_2KBPS_20MS_FRAME;
+		case COASE_TYPE_2KBPS_100MS:
+		return L1_2KBPS_100MS_FRAME;
+		case COASE_TYPE_10KBPS_10MS:
+		return L1_10KBPS_10MS_FRAME;
+		case COASE_TYPE_10KBPS_20MS:
+		return L1_10KBPS_20MS_FRAME;
+		case COASE_TYPE_40KBPS_20MS:
+		return L1_40KBPS_20MS_FRAME;
+		case COASE_TYPE_40KBPS_10MS:
+		return L1_40KBPS_10MS_FRAME;
+		case COASE_TYPE_200KBPS_5MS:
+		return L1_200KBPS_5MS_FRAME;
+		case COASE_TYPE_1M2BPS_5MS:
+		return L1_1M2BPS_5MS_FRAME;
+		default:
 		return L1_NONE_FRAME;
+	}
 }
 
 /*****************************************************************************/
@@ -174,7 +225,7 @@ inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
 inline L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
-	if (instPtr->TOR.last != PHY_TOR_TX)
+	if (instPtr->tor.last != PHY_TOR_TX)
 	{
 		return L1_NONE_FRAME;
 	}
@@ -271,7 +322,8 @@ void Phy_UpdateState(PHY_INST *instPtr)
 
 /*****************************************************************************/
 /**
- * @brief   Initialize physical layer instance accordingly.
+ * @brief   Initialize Physical Layer instance, allocate memory for buffers,
+ * 			apply a self test.
  *
  * @param   instPtr  a pointer to physical instance
  * @param   phyConfig a pointer to configuration structure.
@@ -290,42 +342,42 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	{
 		return EALLOC;
 	}
-	memcpy(&(*instPtr)->phyCofig, phyConfig, sizeof(PHY_CONFIG));
 
+	memcpy(&(*instPtr)->phyCofig, phyConfig, sizeof(PHY_CONFIG));
 	(*instPtr)->isPhyEn = false;
 	(*instPtr)->isAcq = false;
 	(*instPtr)->isFrameSync = false;
 	(*instPtr)->isDecode = false;
 	(*instPtr)->isValid = false;
+	(*instPtr)->isPresetHop = true;
 	(*instPtr)->recvFsTime.int_part = UINT32_MAX;
 	(*instPtr)->recvFsTime.frac_part = UINT32_MAX;
 	(*instPtr)->recvSlotTime.int_part = UINT32_MAX;
 	(*instPtr)->recvSlotTime.frac_part = UINT32_MAX;
-	(*instPtr)->isPresetHop = false;
 	(*instPtr)->antConfigOffset = 0;
 	(*instPtr)->sendDataOffset = 0;
-	Phy_AntCoinfoInit(&((*instPtr)->antCoinfoPtr));
+	Phy_AntConfigInit(&((*instPtr)->antConfig));
 
-	memset(&((*instPtr))->TOR, PHY_TOR_SUSPEND, sizeof(PHY_RCD));
+	memset(&((*instPtr))->tor, PHY_TOR_SUSPEND, sizeof(PHY_RCD));
 	memset(&((*instPtr)->frameType), L1_NONE_FRAME, sizeof(PHY_RCD));
-	memset(&((*instPtr)->antNo), (int32_t)INIT_BEAM_NO, sizeof(PHY_RCD));
-	memset(&((*instPtr)->beamNo), (int32_t)INIT_ANT_NO, sizeof(PHY_RCD));
-	memset(&((*instPtr)->beamWd), (int32_t)INIT_ANT_WD, sizeof(PHY_RCD));
+	memset(&((*instPtr)->antNo), (int32_t)L1_INIT_BEAM_NO, sizeof(PHY_RCD));
+	memset(&((*instPtr)->beamNo), (int32_t)L1_INIT_ANT_NO, sizeof(PHY_RCD));
+	memset(&((*instPtr)->beamWd), (int32_t)L1_INIT_ANT_WD, sizeof(PHY_RCD));
 
 #ifndef EMULATION
-	XBram antInfoBram;
-	XBram txFrameBram;
-	XBram rxFrameBram;
+	XBram_Config *bramConfigPtr;
+	XBram antConfigBram;
+	XBram txDataBram;
+	XBram rxDataBram;
 
-	XBram_Config *ConfigPtr;
-	ConfigPtr = XBram_LookupConfig(phyConfig->antBramId);
-	if (ConfigPtr == NULL)
+	bramConfigPtr = XBram_LookupConfig(phyConfig->antBramId);
+	if (bramConfigPtr == NULL)
 	{
 		Status = EDINVAL;
 		goto error;
 	}
-	Status = XBram_CfgInitialize(&antInfoBram, ConfigPtr,
-								 ConfigPtr->CtrlBaseAddress);
+	Status = XBram_CfgInitialize(&antConfigBram, bramConfigPtr,
+								 bramConfigPtr->CtrlBaseAddress);
 	if (Status != SUCCESS)
 	{
 		goto error;
@@ -333,20 +385,20 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	/*
 	 * Execute the BRAM driver selftest.
 	 */
-	Status = XBram_SelfTest(&antInfoBram, 0);
+	Status = XBram_SelfTest(&antConfigBram, 0);
 	if (Status != SUCCESS)
 	{
 		goto error;
 	}
 
-	ConfigPtr = XBram_LookupConfig(phyConfig->txBramId);
-	if (ConfigPtr == NULL)
+	bramConfigPtr = XBram_LookupConfig(phyConfig->txBramId);
+	if (bramConfigPtr == NULL)
 	{
 		Status = EDINVAL;
 		goto error;
 	}
-	Status = XBram_CfgInitialize(&txFrameBram, ConfigPtr,
-								 ConfigPtr->CtrlBaseAddress);
+	Status = XBram_CfgInitialize(&txDataBram, bramConfigPtr,
+								 bramConfigPtr->CtrlBaseAddress);
 	if (Status != SUCCESS)
 	{
 		goto error;
@@ -354,20 +406,20 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	/*
 	 * Execute the BRAM driver selftest.
 	 */
-	Status = XBram_SelfTest(&txFrameBram, 0);
+	Status = XBram_SelfTest(&txDataBram, 0);
 	if (Status != SUCCESS)
 	{
 		goto error;
 	}
 
-	ConfigPtr = XBram_LookupConfig(phyConfig->rxBramId);
-	if (ConfigPtr == NULL)
+	bramConfigPtr = XBram_LookupConfig(phyConfig->rxBramId);
+	if (bramConfigPtr == NULL)
 	{
 		Status = EDINVAL;
 		goto error;
 	}
-	Status = XBram_CfgInitialize(&rxFrameBram, ConfigPtr,
-								 ConfigPtr->CtrlBaseAddress);
+	Status = XBram_CfgInitialize(&rxDataBram, bramConfigPtr,
+								 bramConfigPtr->CtrlBaseAddress);
 	if (Status != SUCCESS)
 	{
 		goto error;
@@ -375,29 +427,29 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	/*
 	 * Execute the BRAM driver selftest.
 	 */
-	Status = XBram_SelfTest(&rxFrameBram, 0);
+	Status = XBram_SelfTest(&rxDataBram, 0);
 	if (Status != SUCCESS)
 	{
 		goto error;
 	}
 
-	(*instPtr)->antConfigAddr = antInfoBram.Config.MemBaseAddress;
-	(*instPtr)->recvDataAddr = rxFrameBram.Config.MemBaseAddress;
-	(*instPtr)->sendDataAddr = txFrameBram.Config.MemBaseAddress;
+	(*instPtr)->antConfigAddr = antConfigBram.Config.MemBaseAddress;
+	(*instPtr)->recvDataAddr = rxDataBram.Config.MemBaseAddress;
+	(*instPtr)->sendDataAddr = txDataBram.Config.MemBaseAddress;
 #else
-	(*instPtr)->antConfigAddr = (uintptr_t)calloc(ANTCONFIG_MAX_LEN / sizeof(uint64_t), sizeof(uint64_t));
+	(*instPtr)->antConfigAddr = (uintptr_t)calloc(L1_ANTCONFIG_MAX_LEN / sizeof(uint64_t), sizeof(uint64_t));
 	if ((*instPtr)->antConfigAddr == (uintptr_t)NULL)
 	{
 		Status = EALLOC;
 		goto error;
 	}
-	(*instPtr)->recvDataAddr = (uintptr_t)calloc(TXRXDATA_MAX_LEN / sizeof(uint64_t), sizeof(uint64_t));
+	(*instPtr)->recvDataAddr = (uintptr_t)calloc(L1_TXRXDATA_MAX_LEN / sizeof(uint64_t), sizeof(uint64_t));
 	if ((*instPtr)->recvDataAddr == (uintptr_t)NULL)
 	{
 		Status = EALLOC;
 		goto error;
 	}
-	(*instPtr)->sendDataAddr = (uintptr_t)calloc(TXRXDATA_MAX_LEN / sizeof(uint64_t), sizeof(uint64_t));
+	(*instPtr)->sendDataAddr = (uintptr_t)calloc(L1_TXRXDATA_MAX_LEN / sizeof(uint64_t), sizeof(uint64_t));
 	if ((*instPtr)->sendDataAddr == (uintptr_t)NULL)
 	{
 		Status = EALLOC;
@@ -448,7 +500,7 @@ void Phy_Start(PHY_INST *instPtr)
 	uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL);
 	if ((phyMainCtrl & PHY_MAIN_CTRL_EN_MASK) == PHY_MAIN_CTRL_EN_EN)
 	{
-		DBG_WARNING("Physical layer was allready enabled.\n");
+		DBG_WARNING("Physical layer was already enabled.\n");
 	}
 	instPtr->isPhyEn = true;
 	// Enable CRC check automatically
@@ -532,14 +584,11 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 	ASSERT(instPtr != NULL);
 	int32_t Status;
 	uint32_t phyModeCtrl, hopNum;
-	uint16_t *hopPattern = NULL;
+	uint16_t *hopPattern;
 	// Implement a ping-pong flow, offset always is 0 or half of buffer depth.
-	instPtr->antConfigOffset = (ANTCONFIG_MAX_LEN >> 1) - instPtr->antConfigOffset;
+	instPtr->antConfigOffset = (L1_ANTCONFIG_MAX_LEN >> 1) - instPtr->antConfigOffset;
 	uint32_t antConfigAddr = instPtr->antConfigAddr + instPtr->antConfigOffset;
 
-	instPtr->TOR.next = txrxMode;
-	instPtr->frameType.next = frameType;
-
 	switch (txrxMode)
 	{
 	case PHY_TOR_SUSPEND:
@@ -554,6 +603,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 	default:
 		return EPARAM;
 	}
+
 	switch (frameType)
 	{
 	case L1_2KBPS_20MS_FRAME:
@@ -600,28 +650,30 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 		return EPARAM;
 		break;
 	}
-	hopPattern = (instPtr->isPresetHop) ? hopPattern : hopPattern_Config;
+	if (instPtr->isPresetHop == false)
+	{
+		hopPattern = hopPattern_Config;
+	}
 
-	uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antCoinfoPtr));
+	PhyWrite(instPtr, PHY_MODE_CTRL, phyModeCtrl | PHY_MODE_CTRL_CRC_EN);
+
+	uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfig));
 	for (int32_t i = 0; i < hopNum; i++)
 	{
-		instPtr->antCoinfoPtr.antFreq[1] = (uint8_t)(hopPattern[i] & 0x00FF);
-		instPtr->antCoinfoPtr.antFreq[0] = (uint8_t)((hopPattern[i] >> 8) & 0x00FF);
+		instPtr->antConfig.antFreq[1] = (uint8_t)hopPattern[i];
+		instPtr->antConfig.antFreq[0] = (uint8_t)(hopPattern[i] >> 8);
+		instPtr->antConfig.rfFreq[1] = (uint8_t)hopPattern[i];
+		instPtr->antConfig.rfFreq[0] = (uint8_t)(hopPattern[i] >> 8);
 		memcpy((uint8_t *)(antConfigAddr + i * sizeof(PHY_ANT_CONFIG)),
-			   dataSrcPtr, sizeof(PHY_ANT_CONFIG));
+			   dataSrcPtr, ANT_CONFIG_LEN);
 	}
-	uint32_t antCtrl = (instPtr->antConfigOffset & ANT_CONFIG_OFFSET_MASK) | ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK) | ((sizeof(PHY_ANT_CONFIG) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
+	uint32_t antCtrl = (instPtr->antConfigOffset & ANT_CONFIG_OFFSET_MASK)
+						| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
+						| ((ANT_CONFIG_LEN << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
+
 
-	/*
-		memcpy((uint8_t*)antConfigDataAddr, hopPattern, hopNum*sizeof(uint16_t));
-		uint32_t antCtrl = (instPtr->antCoinfigOffset & ANT_CONFIG_OFFSET_MASK)
-				| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
-				| ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
-	*/
-	PhyWrite(instPtr, PHY_MODE_CTRL, phyModeCtrl | PHY_MODE_CTRL_CRC_EN);
 	PhyWrite(instPtr, ANT_CONFIG, antCtrl);
 
-	// Trigger physical configuration.
 	if (txrxMode == PHY_TOR_TX)
 	{
 		Status = Phy_SetSendData(instPtr, frameType, dataBuff);
@@ -631,59 +683,20 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 			return Status;
 		}
 	}
-	PhyWrite(instPtr, SLOT_CMD, SLOT_CMD_KEY); // Phy statr fetching data.
 
-	Phy_RcdShift(&(instPtr->TOR), txrxMode);
+	// Trigger physical configuration.
+	// Indicate physical layer that all the configurations were done.
+	PhyWrite(instPtr, SLOT_CMD, SLOT_CMD_KEY);
+
+	Phy_RcdShift(&(instPtr->tor), txrxMode);
 	Phy_RcdShift(&(instPtr->frameType), frameType);
 	// TODO:
-	Phy_RcdShift(&(instPtr->antNo), INIT_ANT_NO);
-	Phy_RcdShift(&(instPtr->beamNo), INIT_BEAM_NO);
-	Phy_RcdShift(&(instPtr->beamWd), INIT_ANT_WD);
+	Phy_RcdShift(&(instPtr->antNo), L1_INIT_ANT_NO);
+	Phy_RcdShift(&(instPtr->beamNo), L1_INIT_BEAM_NO);
+	Phy_RcdShift(&(instPtr->beamWd), L1_INIT_ANT_WD);
 	return SUCCESS;
 }
 
-/*****************************************************************************/
-/**
- * @brief   Get coarse frequency estimation of last valid frame.
- *
- * @param   instPtr  a pointer to physical instance
- *
- * @return  frequency estimation
- *
- ******************************************************************************/
-double Phy_GetCoarseFreqEst(PHY_INST *instPtr)
-{
-	ASSERT(instPtr != NULL);
-	uint32_t regValue;
-	uint8_t acqFreqIdx;
-	int8_t syncFreqIdx;
-	L1_FRAME_TYPE frameType;
-	double freqEst;
-
-	frameType = Phy_GetLastRecvFrameType(instPtr);
-	if (frameType > L1_1M2BPS_5MS_FRAME || frameType == L1_NONE_FRAME)
-	{
-		return INFINITY; // FIXME
-	}
-	regValue = PhyRead(instPtr, COASE_FREQEST);
-	acqFreqIdx = (regValue >> COASE_FREQEST_ACQ_SHIFT) && COASE_FREQEST_ACQ_MASK;
-	acqFreqIdx = 80 - acqFreqIdx;
-	syncFreqIdx = (regValue >> COASE_FREQEST_SYNC_SHIFT) && COASE_FREQEST_SYNC_MASK;
-	syncFreqIdx = 8 - syncFreqIdx;
-	if (frameType >= L1_200KBPS_5MS_FRAME)
-	{
-		freqEst = (double)acqFreqIdx * (250e3 / 4);
-		freqEst += (double)syncFreqIdx * 1.5e6 / 64 / 128;
-	}
-	else
-	{
-		freqEst = acqFreqIdx * (250e3 / 4);
-		freqEst += (double)syncFreqIdx * 12e6 / 64 / 128;
-	}
-
-	return freqEst;
-}
-
 /*****************************************************************************/
 /**
  * @brief   Get the corresponding frequency hopping pattern length of a
@@ -727,8 +740,7 @@ uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType)
  *
  * @param   frameType	a L1 frame type enumeration.
  *
- * @return  SUCCESS
- * 			FAILURE	frame type cannot be recognized
+ * @return  32bit unsigned integer (10ns)
  *
  ******************************************************************************/
 uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
@@ -756,6 +768,138 @@ uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
 	}
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Get frequency estimation of last valid frame.
+ *
+ * @param   instPtr  a pointer to physical instance
+ *
+ * @return  frequency estimation
+ *
+ ******************************************************************************/
+double Phy_GetFreqEst(PHY_INST *instPtr)
+{
+	ASSERT(instPtr != NULL);
+	uint32_t coarseReg, fineReg, estAbs;
+	uint8_t acqFreqIdx;
+	int8_t syncFreqIdx;
+	L1_FRAME_TYPE frameType;
+	double coarse, fine;
+
+
+	frameType = Phy_GetLastRecvFrameType(instPtr);
+	if (frameType > L1_1M2BPS_5MS_FRAME || frameType <= L1_NONE_FRAME)
+	{
+		return INFINITY; // FIXME
+	}
+
+	coarseReg = PhyRead(instPtr, COASE_FREQEST);
+	acqFreqIdx = (coarseReg & COASE_FREQEST_ACQ_MASK) >> COASE_FREQEST_ACQ_SHIFT;
+	syncFreqIdx = (coarseReg & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
+	fineReg = PhyRead(instPtr, FINE_FREQEST);
+	estAbs = fineReg & FINE_FREQEST_VAL_MASK;
+	if (frameType >= L1_200KBPS_5MS_FRAME)
+	{
+		// 1.5M Rc
+		coarse = (double)(80 - acqFreqIdx) * (31.25e3 / 4);
+		coarse += (double)syncFreqIdx * 1.5e6 / 64 / 128;
+
+		fine = 12e6/2048*((double)estAbs)/8192.0;
+	}
+	else
+	{
+		// 12M Rc
+		coarse = (double)(8 - acqFreqIdx) * (250e3 / 4);
+		coarse += (double)syncFreqIdx * 12e6 / 64 / 128;
+
+		fine = 48e6/2048*((double)estAbs)/8192.0;
+	}
+
+	fine = ((fineReg & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
+			-fine : fine;
+
+	return (coarse + fine);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get coarse frequency estimation of last valid frame.
+ *
+ * @param   instPtr  a pointer to physical instance
+ *
+ * @return  frequency estimation
+ *
+ ******************************************************************************/
+double Phy_GetCoarseFreqEst(PHY_INST *instPtr)
+{
+	ASSERT(instPtr != NULL);
+	uint32_t regValue;
+	uint8_t acqFreqIdx;
+	int8_t syncFreqIdx;
+	L1_FRAME_TYPE frameType;
+	double freqEst;
+
+	frameType = Phy_GetLastRecvFrameType(instPtr);
+	if (frameType > L1_1M2BPS_5MS_FRAME || frameType <= L1_NONE_FRAME)
+	{
+		return INFINITY; // FIXME
+	}
+	regValue = PhyRead(instPtr, COASE_FREQEST);
+	acqFreqIdx = (regValue & COASE_FREQEST_ACQ_MASK) >> COASE_FREQEST_ACQ_SHIFT;
+	syncFreqIdx = (regValue & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
+	if (frameType >= L1_200KBPS_5MS_FRAME)
+	{
+		// 1.5M Rc
+		freqEst = (double)(80 - acqFreqIdx) * (31.25e3 / 4);
+		freqEst += (double)syncFreqIdx * 1.5e6 / 64 / 128;
+	}
+	else
+	{
+		// 12M Rc
+		freqEst = (double)(8 - acqFreqIdx) * (250e3 / 4);
+		freqEst += (double)syncFreqIdx * 12e6 / 64 / 128;
+	}
+
+	return freqEst;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get fine frequency estimation of last valid frame.
+ *
+ * @param   instPtr  a pointer to physical instance
+ *
+ * @return  frequency estimation
+ *
+ ******************************************************************************/
+double Phy_GetFineFreqEst(PHY_INST *instPtr)
+{
+	uint32_t regValue, estAbs;
+	double freqEst;
+	L1_FRAME_TYPE frameType;
+	frameType = Phy_GetLastRecvFrameType(instPtr);
+	if (frameType > L1_1M2BPS_5MS_FRAME || frameType <= L1_NONE_FRAME)
+	{
+		return INFINITY; // FIXME
+	}
+
+	regValue = PhyRead(instPtr, FINE_FREQEST);
+	estAbs = regValue & FINE_FREQEST_VAL_MASK;
+	if (frameType >= L1_200KBPS_5MS_FRAME)
+	{
+		// 1.5M Rc
+		freqEst = 12e6/2048*((double)estAbs)/8192.0;
+	}
+	else
+	{
+		// 12M Rc
+		freqEst = 48e6/2048*((double)estAbs)/8192.0;
+	}
+	freqEst = ((regValue & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
+			-freqEst : freqEst;
+	return freqEst;
+}
+
 /*****************************************************************************/
 /**
  * @brief   Setup a frequency hopping pattern.
@@ -782,8 +926,9 @@ int32_t Phy_SetHopPattern(void *patternBuff, uint32_t patternLen)
 /**
  * @brief   Setup a specific timer word register in physical controller.
  *
- * @param   patternBuff	a pointer to hopping pattern buffer
- * @param   patternLen	a integer indicate the length of hopping pattern.
+ * @param	instPtr
+ * @param   tmWord
+ * @param   tmType
  *
  * @return  SUCCESS
  * 			FAILURE	pattern length exceeds maximum length.
@@ -792,17 +937,17 @@ int32_t Phy_SetHopPattern(void *patternBuff, uint32_t patternLen)
 int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType)
 {
 	ASSERT(instPtr != NULL);
-	if (tmWord->frac_part >= PHY_TIME_WORD_L_MAX)
+	if (tmWord->frac_part >= TIME_FRAC_MAX)
 	{
 		return EPARAM;
 	}
 	switch (tmType)
 	{
-	case TIME_WORD_POLL:
+	case PHY_TIME_WORD_POLL:
 		PhyWrite(instPtr, POLLTIME_L, tmWord->frac_part);
 		PhyWrite(instPtr, POLLTIME_H, tmWord->int_part);
 		break;
-	case TIME_WORD_LISTEN_TIMEOUT:
+	case PHY_TIME_WORD_LISTEN_TIMEOUT:
 		PhyWrite(instPtr, LISTENTIMEOUT_L, tmWord->frac_part);
 		PhyWrite(instPtr, LISTENTIMEOUT_H, tmWord->int_part);
 		break;

datalink814_ge/src/phy_ctrl/phy_ctrl.h

@@ -24,19 +24,27 @@
 
 /***************************** Include Files *********************************/
 #include <stdint.h>
-#include "phy_ctrlreg.h"
+#include "phy_reg.h"
 #include "../common.h"
 #include "../time_ctrl/time_ctrl.h"
-/************************** Constant Definitions *****************************/
-#define TMWORD_FRAC_MAX 500000
-#define ANTCONFIG_MAX_LEN 8192
-#define TXRXDATA_MAX_LEN 2048
-#define NUM_ANT_SUBNRRW_PATTERN 37
-#define NUM_ANT_NRRW_PATTERN 61
-#define INIT_BEAM_NO 0
-#define INIT_ANT_WD ANT_BEAM_120
-#define INIT_ANT_NO 0
 
+/***************** Macros (Inline Functions) Definitions *********************/
+/************************** Constant Definitions *****************************/
+/**
+ * @name PhysicalLayer_Common_Constant
+ * @{
+ */
+#define L1_NUM_ANT_SUBNRRW_PATTERN 37
+#define L1_NUM_ANT_NRRW_PATTERN 61
+#define L1_INIT_BEAM_NO 0
+#define L1_INIT_ANT_WD PHY_ANT_BEAM_120
+#define L1_INIT_ANT_NO 0
+
+#define L1_ANT_NUM_CH 4
+#define L1_TXRXDATA_MAX_LEN 2048
+
+#define L1_FRAME_NONE_LEN UINT32_MAX  // byte
+#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
 #define L1_FRAME_NONE_HOPS UINT32_MAX
 #define L1_FRAME_MAX_HOPS 81
 #define L1_FRAME_2KBPS_20MS_HOPS 1
@@ -47,34 +55,12 @@
 #define L1_FRAME_40KBPS_10MS_HOPS 9
 #define L1_FRAME_200KBPS_5MS_HOPS 20
 #define L1_FRAME_1M2BPS_5MS_HOPS 20
-
-#define L1_FRAME_NONE_LEN UINT32_MAX		// byte
-#define L1_FRAME_LEN_MAX (8192 / 8)			// byte
-#define L1_FRAME_2KBPS_20MS_LEN 1			// byte
-#define L1_FRAME_2KBPS_100MS_LEN 312 / 8	// byte
-#define L1_FRAME_10KBPS_10MS_LEN 1			// byte
-#define L1_FRAME_10KBPS_20MS_LEN (232 / 8)	// byte
-#define L1_FRAME_40KBPS_20MS_LEN (2152 / 8) // byte
-#define L1_FRAME_40KBPS_10MS_LEN (712 / 8)	// byte
-#define L1_FRAME_200KBPS_5MS_LEN (2040 / 8) // byte
-#define L1_FRAME_1M2BPS_5MS_LEN (8176 / 8)	// byte
-
-#define L1_FRAME_NONE_COMP UINT32_MAX	  // *10ns(Timer_L)
-#define L1_FRAME_2KBPS_20MS_COMP 1841158  // *10ns(Timer_L)
-#define L1_FRAME_2KBPS_100MS_COMP 1841158 // *10ns(Timer_L)
-#define L1_FRAME_10KBPS_10MS_COMP 847733  // *10ns(Timer_L)
-#define L1_FRAME_10KBPS_20MS_COMP 847733  // *10ns(Timer_L)
-#define L1_FRAME_40KBPS_20MS_COMP 110667  // *10ns(Timer_L)
-#define L1_FRAME_40KBPS_10MS_COMP 110667  // *10ns(Timer_L)
-#define L1_FRAME_200KBPS_5MS_COMP 19725	  // *10ns(Timer_L)
-#define L1_FRAME_1M2BPS_5MS_COMP 19725	  // *10ns(Timer_L)
-
-#define PHY_TIME_WORD_H_MAX UINT32_MAX
-#define PHY_TIME_WORD_L_MAX 0x0007A120 // 5ms/10ns
-
+/** @} */
 /***************** Macros (Inline Functions) Definitions *********************/
-
 /**************************** Type Definitions *******************************/
+/**
+ * @enum L1_FRAME_TYPE
+ */
 typedef enum
 {
 	L1_NONE_FRAME = 0,
@@ -88,91 +74,89 @@ typedef enum
 	L1_1M2BPS_5MS_FRAME = 8
 } L1_FRAME_TYPE;
 
+/**
+ * @struct PHY_ANT_CONFIG
+ * @brief PhysicalLayer antenna config
+ */
 typedef struct
 {
-	/* Antenna control frame head 0xAA */
-	uint8_t head;
-	/* default 0, reserved for further use */
-	uint8_t ctrlWord;
-	/* high 4 bits specified beam mode.
-	 * low 4 bits specified power control */
-	uint8_t antMode;
-	/* off-axis angle range is 0~60,
-	 * 0.1 degree each LSB */
-	uint8_t oaxis[2];
-	/* round-axis angle range is 0~360,
-	 * 0.1 degree each LSB */
-	uint8_t raxis[2];
-	/* 0~3500Mhz, step 1MHz */
-	uint8_t antFreq[2];
-	/* in single tr mode, 0~63 specified tr channel
-	 * in single subarray mode, 0~3 specified the subarray
-	 * Only in debug mode*/
-	uint8_t trSlect;
-	/* Antenna attenuation 0~31, 0.5dB each LSB, Only in debug mode */
-	uint8_t antAtt;
-	/* 0~63, 5.625 degree each LSB, Only in debug mode*/
-	uint8_t phase;
-	/* 0x00 Nromal RX, 0x01 Normal TX
-	 * 0x11~0xA1 beam debug mode (TR duty 1%~10%)*/
-	uint8_t rxtxMode;
-	/* 0x00 Normal, 0x01 single tr calibration */
-	uint8_t calibrMode;
-	/* reserved for further use */
-	uint8_t reserved;
-	/* DD enable */
-	uint8_t ddEn;
-	/* DD mgc */
-	uint8_t ddMgc;
-	/* [7:4]RF enable: 0-On, 1-Off(Default); [3:0]Work mode: 0(default) */
-	uint8_t rfCtrl;
-	/* RF MGC control: 0~31, 1dB each LSB*/
-	uint8_t rfMgc;
-	/* RF channel 1&2 calibration mgc: [7:4] Channle1 - max 15db, 1dB each LSB
-	 * 								   [3:0] Channle2 - max 15db, 1dB each LSB*/
-	uint8_t rf12CalMgc;
-	/* RF channel 3&4 calibration mgc: [7:4] Channle3 - max 15db, 1dB each LSB
-	 * 								   [3:0] Channle4 - max 15db, 1dB each LSB*/
-	uint8_t rf34CalMgc;
-	/* Receive channel 1 MGC: 0~31, 1dB each LSB */
-	uint8_t rcv1Mgc;
-	/* Receive channel 2 MGC: 0~31, 1dB each LSB */
-	uint8_t rcv2Mgc;
-	/* Receive channel 3 MGC: 0~31, 1dB each LSB */
-	uint8_t rcv3Mgc;
-	/* Receive channel 4 MGC: 0~31, 1dB each LSB */
-	uint8_t rcv4Mgc;
-	/* Antenna control frame tail 0xCC */
-	uint8_t tail;
-	uint8_t dummy[6];
+	/*** Ant Control ***/
+	uint8_t ctrlWord;	 ///< Antenna control frame head 0xAA\n
+						 /// default 0, reserved for further use
+	uint8_t antMode;	 ///< high 4 bits specified beam mode.\n
+						 /// low 4 bits specified power control
+	uint8_t oaxis[2];	 ///< off-axis angle range is 0~60 \n
+						 /// 0.1 degree each LSB
+	uint8_t raxis[2];	 ///< round-axis angle range is 0~360, \n
+						 /// 0.1 degree each LSB
+	uint8_t antFreq[2];	 ///< 0~3500Mhz, step 1MHz
+	uint8_t trSelect;	 ///< in single tr mode, 0~63 specified tr channel \n
+						 /// in single subarray mode, 0~3 specified the subarray
+						 /// ! Only in debug mode!
+	uint8_t antAtt;		 ///< Antenna attenuation 0~31, 0.5dB each LSB, Only in debug mode
+	uint8_t phase;		 ///< 0~63, 5.625 degree each LSB, Only in debug mode
+	uint8_t torMode;	 ///< Only for debug \n
+						 /// default 0x00
+	uint8_t caliMode;	 ///< 0x00 Normal, 0x01 single tr calibration
+	uint8_t antReserved; ///< reserved for further use
+
+	/*** RF Control ***/
+	uint8_t rfCtrl;		 ///< [7:4]RF enable: 0-On, 1-Off(Default); [3:0]Work mode: 0(default)
+	uint8_t rfFreq[2];	 ///< 0~3500Mhz, step 1MHz
+	uint8_t rfTxMgc;	 ///< RF MGC control: 0~31, 1dB each LSB
+	uint8_t rf12CalMgc;	 ///< RF channel 1&2 calibration mgc\n
+						 /// [7:4] Channle1 - max 15db, 1dB each LSB \n
+						 /// [3:0] Channle2 - max 15db, 1dB each LSB
+	uint8_t rf34CalMgc;	 ///< RF channel 3&4 calibration mgc\n
+						 /// [7:4] Channle3 - max 15db, 1dB each LSB
+						 /// [3:0] Channle4 - max 15db, 1dB each LSB
+	uint8_t rfRxMgc;	 ///< Receive channel 1-4 MGC: 0~31, 1dB each LSB
+	uint8_t rfMonitor;	 ///< Receive monitor, 0-normal, 1-switch to monitor port
+	uint8_t rfReserved0; ///< reserved for further use
+	uint8_t rfReserved1; ///< reserved for further use
+	uint8_t ch0Cal[2];
+	uint8_t ch1Cal[2];
+	uint8_t ch2Cal[2];
+	uint8_t ch3Cal[2];
 } PHY_ANT_CONFIG;
 
+/**
+ * @struct PHY_ANT_ANGLE
+ * @brief Describe the PhysicalLayer antenna angle
+ */
 typedef struct
 {
-	/* off-axis angle range is 0~60,
-	 * 0.1 degree each LSB */
-	uint16_t oaxis;
-	/* round-axis angle range is 0~360,
-	 * 0.1 degree each LSB */
-	uint16_t raxis;
+	uint16_t oaxis; ///< off-axis angle range is 0~60
+					/// 0.1 degree each LSB
+	uint16_t raxis; ///< round-axis angle range is 0~360
+					/// 0.1 degree each LSB
 } PHY_ANT_ANGLE;
 
+/**
+ * @enum PHY_TIME_WORD_TYPE
+ */
 typedef enum
 {
-	TIME_WORD_NONE = 0,
-	TIME_WORD_POLL = 1,
-	TIME_WORD_LISTEN_TIMEOUT = 2
+	PHY_TIME_WORD_NONE = 0,
+	PHY_TIME_WORD_POLL = 1,
+	PHY_TIME_WORD_LISTEN_TIMEOUT = 2
 } PHY_TIME_WORD_TYPE;
 
+/**
+ * @enum PHY_ANT_BEAM_WIDTH
+ */
 typedef enum
 {
-	ANT_BEAM_NONE = 0,
-	ANT_BEAM_120 = 1,
-	ANT_BEAM_60 = 2,
-	ANT_BEAM_25 = 3,
-	ANT_BEAM_8 = 4
+	PHY_ANT_BEAM_NONE = 0,
+	PHY_ANT_BEAM_120 = 1,
+	PHY_ANT_BEAM_60 = 2,
+	PHY_ANT_BEAM_25 = 3,
+	PHY_ANT_BEAM_16 = 4
 } PHY_ANT_BEAM_WIDTH;
 
+/**
+ * @enum PHY_TOR_TYPE
+ */
 typedef enum
 {
 	PHY_TOR_SUSPEND = 0,
@@ -180,6 +164,9 @@ typedef enum
 	PHY_TOR_RX = 2
 } PHY_TOR_TYPE;
 
+/**
+ * @enum PHY_MODE
+ */
 typedef enum
 {
 	PHY_MODE_NONE = 0,
@@ -188,6 +175,32 @@ typedef enum
 	PHY_MODE_PULL = 3
 } PHY_MODE;
 
+/**
+ * @enum PHY_ANT_MODE
+ */
+typedef enum
+{
+	PHY_ANT_MODE_NONE = 0,
+	PHY_ANT_MODE_STANDBY = 1,
+	PHY_ANT_MODE_POWER_LOW = 2,
+	PHY_ANT_MODE_POWER_FULL = 3,
+} PHY_ANT_MODE;
+
+/**
+ * @struct PHY_RCD
+ * @brief Physical Layer recode buffer
+ */
+typedef struct
+{
+	int32_t last;
+	int32_t curr;
+	int32_t next;
+} PHY_RCD;
+
+/**
+ * @struct PHY_CONFIG
+ * @brief struct holds all physical layer initialization parameters
+ */
 typedef struct
 {
 	uint32_t devId;
@@ -197,86 +210,70 @@ typedef struct
 	uintptr_t baseAddr;
 } PHY_CONFIG;
 
-typedef struct
-{
-	int32_t last;
-	int32_t curr;
-	int32_t next;
-} PHY_RCD;
-
+/**
+ * @struct PHY_INST
+ * @brief Physical Layer operating instance
+ */
 typedef struct
 {
 	PHY_CONFIG phyCofig; // Device address configs
 	uintptr_t recvDataAddr;
 	uintptr_t sendDataAddr;
 	uintptr_t antConfigAddr;
-	bool isPhyEn;				 // if physical layer running
-	bool isAcq;					 // if last reception acquisition success
-	bool isFrameSync;			 // if last reception frame sync success
-	bool isDecode;				 // if last reception decode success
-	bool isValid;				 // if last reception frame data valid (crc check pass)
-	TIME_WORD recvSlotTime;		 // last slot start time stamp
-	TIME_WORD recvFsTime;		 // last frame sync time stamp
-	bool isPresetHop;			 // if using preset frequency hop
-	PHY_RCD antNo;				 // antenna number record
-	PHY_RCD beamNo;				 // beam number record
-	PHY_RCD beamWd;				 // beam width record
-	PHY_RCD TOR;				 // tx rx state record
-	PHY_RCD frameType;			 // frame type record
-	uint32_t sendDataOffset;	 // antenna configuration bram offset (to implement ping-pong data flow)
-	uint32_t antConfigOffset;	 // antenna configuration bram offset (to implement ping-pong data flow)
-	PHY_ANT_CONFIG antCoinfoPtr; // antenna configuration pointer
+	bool isPhyEn;			  // if physical layer running
+	bool isAcq;				  // if last reception acquisition success
+	bool isFrameSync;		  // if last reception frame sync success
+	bool isDecode;			  // if last reception decode success
+	bool isValid;			  // if last reception frame data valid (crc check pass)
+	bool isPresetHop;		  // if using preset frequency hop
+	TIME_WORD recvSlotTime;	  // last slot start time stamp
+	TIME_WORD recvFsTime;	  // last frame sync time stamp
+	PHY_RCD antNo;			  // antenna number record
+	PHY_RCD beamNo;			  // beam number record
+	PHY_RCD beamWd;			  // beam width record
+	PHY_RCD tor;			  // tx rx state record
+	PHY_RCD frameType;		  // frame type record
+	uint32_t sendDataOffset;  // antenna configuration bram offset (to implement ping-pong data flow)
+	uint32_t antConfigOffset; // antenna configuration bram offset (to implement ping-pong data flow)
+	PHY_ANT_CONFIG antConfig; // antenna configuration pointer
 } PHY_INST;
 
-/************************** Variable Definitions *****************************/
-extern uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS];
-extern uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS];
-extern uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS];
-extern uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS];
-extern uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS];
-extern uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS];
-extern uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS];
-extern uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
-extern uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
-
-extern PHY_ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN];
-extern PHY_ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN];
-
 /************************** Function Prototypes ******************************/
 int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
 void Phy_Destroy(PHY_INST *instPtr);
-
-void Phy_UpdateState(PHY_INST *instPtr);
-
 void Phy_Start(PHY_INST *instPtr);
 void Phy_Halt(PHY_INST *instPtr);
-int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod);
 
+int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod);
+int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType);
 int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode, L1_FRAME_TYPE frameType, uint8_t *dataBuff);
+void Phy_UpdateState(PHY_INST *instPtr);
 void Phy_PeekRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
 void Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
 
 bool Phy_IsFrameDetected(PHY_INST *instPtr);
 bool Phy_IsFrameReceived(PHY_INST *instPtr);
 bool Phy_IsFrameValid(PHY_INST *instPtr);
-uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
-
-L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr);
-L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr);
-
 int32_t Phy_SetHopPattern(void *patternBuff, uint32_t patternLen);
 uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType);
 uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType);
+uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
+L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr);
+L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr);
 
-int32_t Phy_AntCoinfoInit(PHY_ANT_CONFIG *antCoinfoPtr);
-int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth);
-int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo);
-int32_t Phy_SetBeamAngle(PHY_INST *phyInstPtr, double offAx, double rndAx);
-int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType);
-
+double Phy_GetFreqEst(PHY_INST *instPtr);
 double Phy_GetCoarseFreqEst(PHY_INST *instPtr);
+double Phy_GetFineFreqEst(PHY_INST *instPtr);
 void Phy_GetFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
 void Phy_GetLastReceivedFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
 void Phy_GetSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
 void Phy_GetLastReceivedSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
+
+void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig);
+void Phy_AntConfigMode(PHY_INST *instPtr, PHY_ANT_MODE mode);
+void Phy_AntConfigAttenuation(PHY_INST *instPtr, uint8_t rxAtt, uint8_t txAtt);
+int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth);
+int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo, PHY_ANT_BEAM_WIDTH beamWidth);
+int32_t Phy_SetBeamAngle(PHY_INST *phyInstPtr, double offAx, double rndAx);
+
 #endif /* PHY_CTRL_H_ */

datalink814_ge/src/phy_ctrl/phy_reg.h

@@ -18,8 +18,8 @@
  *
  ******************************************************************************/
 
-#ifndef PHY_CTRLREG_H_
-#define PHY_CTRLREG_H_
+#ifndef PHY_REG_H_
+#define PHY_REG_H_
 
 /***************************** Include Files *********************************/
 #include "../util/util.h"
@@ -139,7 +139,7 @@
 #define SEND_DATA_CMD_OFFSET_MASK 0xFFFF0000U
 
 /**
- * Register: SEND_CONFIG_CMD
+ * Register: SLOT_CONFIG_CMD
  */
 #define SLOT_CMD 0x00000020U
 #define SLOT_CMD_SHIFT 0
@@ -186,10 +186,11 @@
 #define RECVDATA_STATE_OFFSET_SHIFT 16
 #define RECVDATA_STATE_OFFSET_WIDTH 16
 #define RECVDATA_STATE_OFFSET_MASK 0xFFFF0000U
+
 /**
  * Register: FSTIME_L
  */
-#define FSTIME_L 0x000002CU
+#define FSTIME_L 0x0000002CU
 #define FSTIME_L_SHIFT 0
 #define FSTIME_L_WIDTH 32
 #define FSTIME_L_MASK 0xFFFFFFFFU
@@ -197,7 +198,7 @@
 /**
  * Register: FSTIME_INT1
  */
-#define FSTIME_H 0x0000030U
+#define FSTIME_H 0x00000030U
 #define FSTIME_H_SHIFT 0
 #define FSTIME_H_WIDTH 32
 #define FSTIME_H_MASK 0xFFFFFFFFU
@@ -205,7 +206,7 @@
 /**
  * Register: TM_TARGET_L
  */
-#define TM_TARGET_L 0x0000064U
+#define TM_TARGET_L 0x00000064U
 #define TM_TARGET_L_SHIFT 0
 #define TM_TARGET_L_WIDTH 32
 #define TM_TARGET_L_MASK 0xFFFFFFFFU
@@ -213,7 +214,7 @@
 /**
  * Register: TM_TARGET_H
  */
-#define TM_TARGET_H 0x0000038U
+#define TM_TARGET_H 0x00000038U
 #define TM_TARGET_H_SHIFT 0
 #define TM_TARGET_H_WIDTH 32
 #define TM_TARGET_H_MASK 0xFFFFFFFFU
@@ -225,17 +226,33 @@
 #define COASE_FREQEST_ACQ_SHIFT 0
 #define COASE_FREQEST_ACQ_WIDTH 8
 #define COASE_FREQEST_ACQ_MASK 0x000000FFU
-#define COASE_FREQEST_SYNC_SHIFT 0
-#define COASE_FREQEST_SYNC_WIDTH 16
-#define COASE_FREQEST_SYNC_MASK 0x000FF00U
+#define COASE_FREQEST_SYNC_SHIFT 8
+#define COASE_FREQEST_SYNC_WIDTH 8
+#define COASE_FREQEST_SYNC_MASK 0x0000FF00U
+#define COASE_TYPE_SHIFT 16
+#define COASE_TYPE_WIDTH 8
+#define COASE_TYPE_MASK 0x00FF0000U
+#define COASE_TYPE_2KBPS_20MS  0x00010000U
+#define COASE_TYPE_2KBPS_100MS 0x00020000U
+#define COASE_TYPE_10KBPS_10MS 0x00030000U
+#define COASE_TYPE_10KBPS_20MS 0x00040000U
+#define COASE_TYPE_40KBPS_20MS 0x00050000U
+#define COASE_TYPE_40KBPS_10MS 0x00060000U
+#define COASE_TYPE_200KBPS_5MS 0x00070000U
+#define COASE_TYPE_1M2BPS_5MS  0x00080000U
 
 /**
  * Register: FINE_FREQEST
  */
 #define FINE_FREQEST 0x00000040U
-#define FINE_FREQEST_SHIFT 0
-#define FINE_FREQEST_WIDTH 32
-#define FINE_FREQEST_MASK 0xFFFFFFFFU
+#define FINE_FREQEST_VAL_SHIFT 0
+#define FINE_FREQEST_VAL_WIDTH 24
+#define FINE_FREQEST_VAL_MASK 0x00FFFFFFU
+#define FINE_FREQEST_SIGN_SHIFT 24
+#define FINE_FREQEST_SIGN_WIDTH 8
+#define FINE_FREQEST_SIGN_MASK 0xFF000000U
+#define FINE_FREQEST_SIGN_POS 0x00000000U
+#define FINE_FREQEST_SIGN_NEG 0x01000000U
 
 /**
  * Register: BEAM_SELECT
@@ -246,7 +263,7 @@
 #define BEAM_SELECT_INDEX_MASK 0xFFFFFFFFU
 
 /**
- * Register: BEAM_SELECT
+ * Register: BEAM_AXIS
  */
 #define BEAM_AXIS 0x00000044U
 #define BEAM_AXIS_EL_SHIFT 0
@@ -257,4 +274,4 @@
 #define BEAM_AXIS_AZ_MASK 0xFFFF0000U
 
 // Reserved.
-#endif /* PHY_CTRLREG_H_ */
+#endif /* PHY_REG_H_ */

datalink814_ge/src/time_ctrl/time_ctrl.c

@@ -51,25 +51,45 @@
  *          FAILURE Initialization failed
  *
  ******************************************************************************/
-int32_t TimeCtrl_Init(TIMECTRL_INST **instPtr, TIMECTRL_CONFIG *config)
+int32_t TimeCtrl_Init(TMC_INST **instPtr, TMC_CONFIG *config)
 {
 	ASSERT(config != NULL);
 	ASSERT(instPtr != NULL);
-	(*instPtr) = malloc(sizeof(TIMECTRL_INST));
-	memcpy(&((*instPtr)->config), config, sizeof(TIMECTRL_CONFIG));
+	(*instPtr) = malloc(sizeof(TMC_INST));
+	memcpy(&((*instPtr)->config), config, sizeof(TMC_CONFIG));
 	(*instPtr)->modelVer = TMC_Read((*instPtr), VERSION_REG);
 	return SUCCESS;
 }
 
-void TimeCtrl_Destroy(TIMECTRL_INST *instPtr)
+/*****************************************************************************/
+/**
+ * @brief   Completely destroy time control instance.
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void TimeCtrl_Destroy(TMC_INST *instPtr)
 {
 	free(instPtr);
 }
 
-uint32_t TimeCtrl_GetVersion(TIMECTRL_INST *instPtr)
+/*****************************************************************************/
+/**
+ * @brief   Read time controller version register.
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  timer controller version.
+ *
+ ******************************************************************************/
+uint32_t TimeCtrl_GetVersion(TMC_INST *instPtr)
 {
+	ASSERT(instPtr != NULL);
 	return TMC_Read(instPtr, VERSION_REG);
 }
+
 /*****************************************************************************/
 /**
  * @brief   Apply a reset process to time controller
@@ -80,7 +100,7 @@ uint32_t TimeCtrl_GetVersion(TIMECTRL_INST *instPtr)
  *          FAILURE Initialization failed
  *
  ******************************************************************************/
-void TimeCtrl_Reset(TIMECTRL_INST *instPtr)
+void TimeCtrl_Reset(TMC_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	TMC_Write(instPtr, CNTSTEP_OPT, TM_RESET_CODE);
@@ -95,7 +115,7 @@ void TimeCtrl_Reset(TIMECTRL_INST *instPtr)
  * @return  NONE
  *
  ******************************************************************************/
-void TimeCtrl_ResetHigh(TIMECTRL_INST *instPtr)
+void TimeCtrl_ResetHigh(TMC_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	// TODO:
@@ -110,7 +130,7 @@ void TimeCtrl_ResetHigh(TIMECTRL_INST *instPtr)
  * @return  NONE
  *
  ******************************************************************************/
-void TimeCtrl_ResetLow(TIMECTRL_INST *instPtr)
+void TimeCtrl_ResetLow(TMC_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	// TODO:
@@ -125,7 +145,7 @@ void TimeCtrl_ResetLow(TIMECTRL_INST *instPtr)
  * @return  integer value
  *
  ******************************************************************************/
-inline TIME_INT TimeCtrl_GetIntCnt(TIMECTRL_INST *instPtr)
+inline TIME_INT TimeCtrl_GetIntCnt(TMC_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	return TMC_Read(instPtr, TIME_INT_REG);
@@ -140,7 +160,7 @@ inline TIME_INT TimeCtrl_GetIntCnt(TIMECTRL_INST *instPtr)
  * @return  fractional value
  *
  ******************************************************************************/
-inline TIME_FRAC TimeCtrl_GetFracCnt(TIMECTRL_INST *instPtr)
+inline TIME_FRAC TimeCtrl_GetFracCnt(TMC_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	return TMC_Read(instPtr, TIME_FRAC_REG);
@@ -156,7 +176,7 @@ inline TIME_FRAC TimeCtrl_GetFracCnt(TIMECTRL_INST *instPtr)
  * @return  NONE
  *
  ******************************************************************************/
-void TimeCtrl_GetCurrentTime(TIMECTRL_INST *instPtr, TIME_WORD *tmWord)
+void TimeCtrl_GetCurrentTime(TMC_INST *instPtr, TIME_WORD *tmWord)
 {
 	ASSERT(instPtr != NULL);
 	ASSERT(tmWord != NULL);
@@ -174,7 +194,7 @@ void TimeCtrl_GetCurrentTime(TIMECTRL_INST *instPtr, TIME_WORD *tmWord)
  * @return  NONE.
  *
  ******************************************************************************/
-void TimeCtrl_GetCurrentStep(TIMECTRL_INST *instPtr, TIME_FRAC *tmFrac)
+void TimeCtrl_GetCurrentStep(TMC_INST *instPtr, TIME_FRAC *tmFrac)
 {
 	ASSERT(instPtr != NULL);
 	ASSERT(tmFrac != NULL);
@@ -192,7 +212,7 @@ void TimeCtrl_GetCurrentStep(TIMECTRL_INST *instPtr, TIME_FRAC *tmFrac)
  * @return  NONE.
  *
  ******************************************************************************/
-void TimeCtrl_TimeAdjust(TIMECTRL_INST *instPtr, const TIME_WORD *tmWord, TIMECTRL_ADJ_TYPE type)
+void TimeCtrl_TimeAdjust(TMC_INST *instPtr, const TIME_WORD *tmWord, TIMECTRL_ADJ_TYPE type)
 {
 	ASSERT(instPtr != NULL);
 	ASSERT(tmWord != NULL);
@@ -223,7 +243,7 @@ void TimeCtrl_TimeAdjust(TIMECTRL_INST *instPtr, const TIME_WORD *tmWord, TIMECT
  * @return  NONE.
  *
  ******************************************************************************/
-void TimeCtrl_SetOptimizeStep(TIMECTRL_INST *instPtr, TIME_FRAC *tmFrac)
+void TimeCtrl_SetOptimizeStep(TMC_INST *instPtr, TIME_FRAC *tmFrac)
 {
 	ASSERT(instPtr != NULL);
 	ASSERT(tmFrac != NULL);

datalink814_ge/src/time_ctrl/time_ctrl.h

@@ -45,30 +45,30 @@ typedef struct
 {
 	uintptr_t baseAddr;
 	uint32_t reset; // time for reset (unit: us)
-} TIMECTRL_CONFIG;
+} TMC_CONFIG;
 
 typedef struct
 {
-	TIMECTRL_CONFIG config;
+	TMC_CONFIG config;
 	uint32_t modelVer;
-} TIMECTRL_INST;
+} TMC_INST;
 
 /************************** Function Prototypes ******************************/
-int32_t TimeCtrl_Init(TIMECTRL_INST **instPtr, TIMECTRL_CONFIG *config);
-uint32_t TimeCtrl_GetVersion(TIMECTRL_INST *instPtr);
-void TimeCtrl_Destroy(TIMECTRL_INST *instPtr);
-void TimeCtrl_Reset(TIMECTRL_INST *instPtr);
-void TimeCtrl_ResetLow(TIMECTRL_INST *instPtr);
-void TimeCtrl_ResetHigh(TIMECTRL_INST *instPtr);
+int32_t TimeCtrl_Init(TMC_INST **instPtr, TMC_CONFIG *config);
+uint32_t TimeCtrl_GetVersion(TMC_INST *instPtr);
+void TimeCtrl_Destroy(TMC_INST *instPtr);
+void TimeCtrl_Reset(TMC_INST *instPtr);
+void TimeCtrl_ResetLow(TMC_INST *instPtr);
+void TimeCtrl_ResetHigh(TMC_INST *instPtr);
 
-TIME_INT TimeCtrl_GetIntCnt(TIMECTRL_INST *instPtr);
-TIME_FRAC TimeCtrl_GetFracCnt(TIMECTRL_INST *instPtr);
+TIME_INT TimeCtrl_GetIntCnt(TMC_INST *instPtr);
+TIME_FRAC TimeCtrl_GetFracCnt(TMC_INST *instPtr);
 
-void TimeCtrl_GetCurrentTime(TIMECTRL_INST *instPtr, TIME_WORD *tmWord);
-void TimeCtrl_GetCurrentStep(TIMECTRL_INST *instPtr, TIME_FRAC *tmFrac);
+void TimeCtrl_GetCurrentTime(TMC_INST *instPtr, TIME_WORD *tmWord);
+void TimeCtrl_GetCurrentStep(TMC_INST *instPtr, TIME_FRAC *tmFrac);
 
-void TimeCtrl_SetOptimizeStep(TIMECTRL_INST *instPtr, TIME_FRAC *tmFrac);
-void TimeCtrl_TimeAdjust(TIMECTRL_INST *instPtr, const TIME_WORD *tmWord, TIMECTRL_ADJ_TYPE type);
+void TimeCtrl_SetOptimizeStep(TMC_INST *instPtr, TIME_FRAC *tmFrac);
+void TimeCtrl_TimeAdjust(TMC_INST *instPtr, const TIME_WORD *tmWord, TIMECTRL_ADJ_TYPE type);
 void TimeCtrl_CalculateTimeGap(const TIME_WORD *a, const TIME_WORD *b, TIME_WORD *gap);
 
 #endif /* TIME_SYNC_H_ */

datalink814_ge/src/util/circ_queue.c

@@ -30,7 +30,7 @@
  ******************************************************************************/
 
 #include "circ_queue.h"
-#include "common.h"
+#include "../common.h"
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>

datalink814_ge/src/util/clist.c

@@ -13,17 +13,17 @@
 //
 
 #include <stdint.h>
-#include "list.h"
+#include "clist.h"
 
 /*
- * Allocates a new list_node_t. NULL on failure.
+ * Allocates a new clist_node_t. NULL on failure.
  */
 
-list_node_t *
-list_node_new(void *val)
+clist_node_t *
+clist_node_new(void *val)
 {
-  list_node_t *self;
-  if (!(self = LIST_MALLOC(sizeof(list_node_t))))
+  clist_node_t *self;
+  if (!(self = LIST_MALLOC(sizeof(clist_node_t))))
     return NULL;
   self->prev = NULL;
   self->next = NULL;
@@ -32,14 +32,14 @@ list_node_new(void *val)
 }
 
 /*
- * Allocate a new list_t. NULL on failure.
+ * Allocate a new clist_t. NULL on failure.
  */
 
-list_t *
-list_new(void)
+clist_t *
+clist_new(void)
 {
-  list_t *self;
-  if (!(self = LIST_MALLOC(sizeof(list_t))))
+  clist_t *self;
+  if (!(self = LIST_MALLOC(sizeof(clist_t))))
     return NULL;
   self->head = NULL;
   self->tail = NULL;
@@ -54,21 +54,21 @@ list_new(void)
  * @self: Pointer to the list
  */
 
-void list_clear(list_t *self)
+void clist_clear(clist_t *self)
 {
-  uint32_t len = self->len;
-  list_node_t *next;
-  list_node_t *curr = self->head;
+  clist_node_t *next;
+  clist_node_t *curr = self->head;
 
-  while (len)
+  while (curr != NULL)
   {
     next = curr->next;
     if (self->free)
       self->free(curr->val);
     LIST_FREE(curr);
     curr = next;
-    len--;
   }
+  self->len = 0;
+  self->head = NULL;
 }
 
 /*
@@ -76,9 +76,9 @@ void list_clear(list_t *self)
  * @self: Pointer to the list
  */
 
-void list_destroy(list_t *self)
+void clist_destroy(clist_t *self)
 {
-  list_clear(self);
+  clist_clear(self);
   LIST_FREE(self);
 }
 
@@ -89,8 +89,8 @@ void list_destroy(list_t *self)
  * @node: the node to push
  */
 
-list_node_t *
-list_rpush(list_t *self, list_node_t *node)
+clist_node_t *
+clist_rpush(clist_t *self, clist_node_t *node)
 {
   if (!node)
     return NULL;
@@ -117,13 +117,13 @@ list_rpush(list_t *self, list_node_t *node)
  * @self: Pointer to the list for popping node
  */
 
-list_node_t *
-list_rpop(list_t *self)
+clist_node_t *
+clist_rpop(clist_t *self)
 {
   if (!self->len)
     return NULL;
 
-  list_node_t *node = self->tail;
+  clist_node_t *node = self->tail;
 
   if (--self->len)
   {
@@ -143,13 +143,13 @@ list_rpop(list_t *self)
  * @self: Pointer to the list for popping node
  */
 
-list_node_t *
-list_lpop(list_t *self)
+clist_node_t *
+clist_lpop(clist_t *self)
 {
   if (!self->len)
     return NULL;
 
-  list_node_t *node = self->head;
+  clist_node_t *node = self->head;
 
   if (--self->len)
   {
@@ -171,8 +171,8 @@ list_lpop(list_t *self)
  * @node: the node to push
  */
 
-list_node_t *
-list_lpush(list_t *self, list_node_t *node)
+clist_node_t *
+clist_lpush(clist_t *self, clist_node_t *node)
 {
   if (!node)
     return NULL;
@@ -200,19 +200,19 @@ list_lpush(list_t *self, list_node_t *node)
  * @val: Value to find
  */
 
-list_node_t *
-list_find(list_t *self, void *val)
+clist_node_t *
+clist_find(clist_t *self, void *val)
 {
-  list_iterator_t *it = list_iterator_new(self, LIST_HEAD);
-  list_node_t *node;
+  clist_iterator_t *it = clist_iterator_new(self, LIST_HEAD);
+  clist_node_t *node;
 
-  while ((node = list_iterator_next(it)))
+  while ((node = clist_iterator_next(it)))
   {
     if (self->compare)
     {
       if (self->compare(val, node->val) == 0)
       {
-        list_iterator_destroy(it);
+        clist_iterator_destroy(it);
         return node;
       }
     }
@@ -220,13 +220,13 @@ list_find(list_t *self, void *val)
     {
       if (val == node->val)
       {
-        list_iterator_destroy(it);
+        clist_iterator_destroy(it);
         return node;
       }
     }
   }
 
-  list_iterator_destroy(it);
+  clist_iterator_destroy(it);
   return NULL;
 }
 
@@ -236,10 +236,10 @@ list_find(list_t *self, void *val)
  * @index: the index of node in the list
  */
 
-list_node_t *
-list_at(list_t *self, int index)
+clist_node_t *
+clist_at(clist_t *self, int index)
 {
-  list_direction_t direction = LIST_HEAD;
+  clist_direction_t direction = LIST_HEAD;
 
   if (index < 0)
   {
@@ -249,11 +249,11 @@ list_at(list_t *self, int index)
 
   if ((unsigned)index < self->len)
   {
-    list_iterator_t *it = list_iterator_new(self, direction);
-    list_node_t *node = list_iterator_next(it);
+    clist_iterator_t *it = clist_iterator_new(self, direction);
+    clist_node_t *node = clist_iterator_next(it);
     while (index--)
-      node = list_iterator_next(it);
-    list_iterator_destroy(it);
+      node = clist_iterator_next(it);
+    clist_iterator_destroy(it);
     return node;
   }
 
@@ -266,7 +266,7 @@ list_at(list_t *self, int index)
  * @node: Pointer the node to be deleted
  */
 
-void list_remove(list_t *self, list_node_t *node)
+void clist_remove(clist_t *self, clist_node_t *node)
 {
   node->prev
       ? (node->prev->next = node->next)
@@ -284,29 +284,29 @@ void list_remove(list_t *self, list_node_t *node)
 }
 
 /*
- * Allocate a new list_iterator_t. NULL on failure.
+ * Allocate a new clist_iterator_t. NULL on failure.
  * Accepts a direction, which may be LIST_HEAD or LIST_TAIL.
  */
 
-list_iterator_t *
-list_iterator_new(list_t *list, list_direction_t direction)
+clist_iterator_t *
+clist_iterator_new(clist_t *list, clist_direction_t direction)
 {
-  list_node_t *node = direction == LIST_HEAD
+  clist_node_t *node = direction == LIST_HEAD
                           ? list->head
                           : list->tail;
-  return list_iterator_new_from_node(node, direction);
+  return clist_iterator_new_from_node(node, direction);
 }
 
 /*
- * Allocate a new list_iterator_t with the given start
+ * Allocate a new clist_iterator_t with the given start
  * node. NULL on failure.
  */
 
-list_iterator_t *
-list_iterator_new_from_node(list_node_t *node, list_direction_t direction)
+clist_iterator_t *
+clist_iterator_new_from_node(clist_node_t *node, clist_direction_t direction)
 {
-  list_iterator_t *self;
-  if (!(self = LIST_MALLOC(sizeof(list_iterator_t))))
+  clist_iterator_t *self;
+  if (!(self = LIST_MALLOC(sizeof(clist_iterator_t))))
     return NULL;
   self->next = node;
   self->direction = direction;
@@ -314,14 +314,14 @@ list_iterator_new_from_node(list_node_t *node, list_direction_t direction)
 }
 
 /*
- * Return the next list_node_t or NULL when no more
+ * Return the next clist_node_t or NULL when no more
  * nodes remain in the list.
  */
 
-list_node_t *
-list_iterator_next(list_iterator_t *self)
+clist_node_t *
+clist_iterator_next(clist_iterator_t *self)
 {
-  list_node_t *curr = self->next;
+  clist_node_t *curr = self->next;
   if (curr)
   {
     self->next = self->direction == LIST_HEAD
@@ -335,7 +335,7 @@ list_iterator_next(list_iterator_t *self)
  * Free the list iterator.
  */
 
-void list_iterator_destroy(list_iterator_t *self)
+void clist_iterator_destroy(clist_iterator_t *self)
 {
   LIST_FREE(self);
   self = NULL;

datalink814_ge/src/util/clist.h

@@ -0,0 +1,118 @@
+
+//
+// clist.h
+//
+// Copyright (c) 2010 TJ Holowaychuk <[email protected]>
+//
+
+#ifndef __CLIST_H__
+#define __CLIST_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdlib.h>
+#include <stdint.h>
+
+  /*
+   * clist_t iterator direction.
+   */
+
+  typedef enum
+  {
+    LIST_HEAD,
+    LIST_TAIL
+  } clist_direction_t;
+
+  /*
+   * clist_t node struct.
+   */
+
+  typedef struct clist_node
+  {
+    struct clist_node *prev;
+    struct clist_node *next;
+    void *val;
+  } clist_node_t;
+
+  /*
+   * clist_t struct.
+   */
+
+  typedef struct
+  {
+    clist_node_t *head;
+    clist_node_t *tail;
+    uint32_t len;
+    void (*free)(void *val);
+    int8_t (*compare)(void *a, void *b);
+  } clist_t;
+
+  /*
+   * clist_t iterator struct.
+   */
+
+  typedef struct
+  {
+    clist_node_t *next;
+    clist_direction_t direction;
+  } clist_iterator_t;
+
+  // Node prototypes.
+
+  clist_node_t *
+  clist_node_new(void *val);
+
+  // clist_t prototypes.
+
+  clist_t *
+  clist_new(void);
+
+  clist_node_t *
+  clist_rpush(clist_t *self, clist_node_t *node);
+
+  clist_node_t *
+  clist_lpush(clist_t *self, clist_node_t *node);
+
+  clist_node_t *
+  clist_find(clist_t *self, void *val);
+
+  clist_node_t *
+  clist_at(clist_t *self, int index);
+
+  clist_node_t *
+  clist_rpop(clist_t *self);
+
+  clist_node_t *
+  clist_lpop(clist_t *self);
+
+  void
+  clist_remove(clist_t *self, clist_node_t *node);
+
+  void
+  clist_clear(clist_t *self);
+
+  void
+  clist_destroy(clist_t *self);
+
+  // clist_t iterator prototypes.
+
+  clist_iterator_t *
+  clist_iterator_new(clist_t *list, clist_direction_t direction);
+
+  clist_iterator_t *
+  clist_iterator_new_from_node(clist_node_t *node, clist_direction_t direction);
+
+  clist_node_t *
+  clist_iterator_next(clist_iterator_t *self);
+
+  void
+  clist_iterator_destroy(clist_iterator_t *self);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLIBS_LIST_H__ */

datalink814_ge/src/util/list.h

@@ -1,118 +0,0 @@
-
-//
-// list.h
-//
-// Copyright (c) 2010 TJ Holowaychuk <[email protected]>
-//
-
-#ifndef __LIST_H__
-#define __LIST_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include <stdlib.h>
-#include <stdint.h>
-
-  /*
-   * list_t iterator direction.
-   */
-
-  typedef enum
-  {
-    LIST_HEAD,
-    LIST_TAIL
-  } list_direction_t;
-
-  /*
-   * list_t node struct.
-   */
-
-  typedef struct list_node
-  {
-    struct list_node *prev;
-    struct list_node *next;
-    void *val;
-  } list_node_t;
-
-  /*
-   * list_t struct.
-   */
-
-  typedef struct
-  {
-    list_node_t *head;
-    list_node_t *tail;
-    uint32_t len;
-    void (*free)(void *val);
-    int8_t (*compare)(void *a, void *b);
-  } list_t;
-
-  /*
-   * list_t iterator struct.
-   */
-
-  typedef struct
-  {
-    list_node_t *next;
-    list_direction_t direction;
-  } list_iterator_t;
-
-  // Node prototypes.
-
-  list_node_t *
-  list_node_new(void *val);
-
-  // list_t prototypes.
-
-  list_t *
-  list_new(void);
-
-  list_node_t *
-  list_rpush(list_t *self, list_node_t *node);
-
-  list_node_t *
-  list_lpush(list_t *self, list_node_t *node);
-
-  list_node_t *
-  list_find(list_t *self, void *val);
-
-  list_node_t *
-  list_at(list_t *self, int index);
-
-  list_node_t *
-  list_rpop(list_t *self);
-
-  list_node_t *
-  list_lpop(list_t *self);
-
-  void
-  list_remove(list_t *self, list_node_t *node);
-
-  void
-  list_clear(list_t *self);
-
-  void
-  list_destroy(list_t *self);
-
-  // list_t iterator prototypes.
-
-  list_iterator_t *
-  list_iterator_new(list_t *list, list_direction_t direction);
-
-  list_iterator_t *
-  list_iterator_new_from_node(list_node_t *node, list_direction_t direction);
-
-  list_node_t *
-  list_iterator_next(list_iterator_t *self);
-
-  void
-  list_iterator_destroy(list_iterator_t *self);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CLIBS_LIST_H__ */

datalink814_ge/src/util/util.h

@@ -1,5 +1,4 @@
-/***************************************************************************
-//**
+/*******************************************************************************
  *   @file   util.h
  *   @brief  Implementation of utility functions.
  *   @author DBogdan ([email protected])

datalink814_ge/unit_test/linklayer_emulate_unit_test.c

@@ -8,27 +8,31 @@
 #include "linklayer/linklayer814.h"
 #include "linklayer/msg_def.h"
 
-#define TIME_INT_REG	(0x00000008>>2)
-#define TIME_FRAC_REG	(0x0000000C>>2)
-#define TIME_ADJ_INT	(0x0000001C>>2)
-#define TIME_ADJ_FRAC	(0x00000020>>2)
-#define TIME_ADJ_TRIG	(0x00000024>>2)
-#define CNTSTEP_OPT		(0x00000028>>2)
+#define TIME_INT_REG (0x00000008 >> 2)
+#define TIME_FRAC_REG (0x0000000C >> 2)
+#define TIME_ADJ_INT (0x0000001C >> 2)
+#define TIME_ADJ_FRAC (0x00000020 >> 2)
+#define TIME_ADJ_TRIG (0x00000024 >> 2)
+#define CNTSTEP_OPT (0x00000028 >> 2)
 
-TIMECTRL_INST* tmcInstPtr = NULL;
-PHY_INST* phyInstPtr = NULL;
-L2_INST* linkInstPtr = NULL;
+TMC_INST *tmcInstPtr = NULL;
+PHY_INST *phyInstPtr = NULL;
+L2_INST *linkInstPtr = NULL;
 
 uint32_t tmcReg[32] = {0};
 uint32_t phycReg[512] = {0};
 
-uint8_t bmTemplate[INTRA_BM_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = {
+
+uint8_t bmTemplate[INTRA_BM_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = 
+{
 	0x08, 0x21, 0x04, 0x06, 0x00, 0xF3, 0xA8, 0xCB, 
 	0x00, 0xA0, 0x49, 0x00, 0x9A, 0x04, 0x13, 0x1E, 
 	0x45, 0xE7, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 
 	0xAA, 0xAA, 0xAA, 0xAA, 0xAA
 };
-uint8_t w2acqTemplate[INTRA_W2ACQ_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = {
+
+uint8_t w2acqTemplate[INTRA_W2ACQ_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = 
+{
 	0xCC, 0x71, 0x21, 0xA8, 0x0A, 0x00, 0x00, 0x00, 
 	0x00, 0x1A, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 
 	0xF0, 0xF0, 0x2A, 0x0F, 0x0F, 0xF0, 0x0F, 0x00, 
@@ -62,7 +66,9 @@ uint8_t w2acqTemplate[INTRA_W2ACQ_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))
 	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 
 	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA
 };
-uint8_t mgmtTemplate[INTRA_MGMT_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = {
+
+uint8_t mgmtTemplate[INTRA_MGMT_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = 
+{
 	0xCC, 0xC3, 0x99, 0x99, 0x83, 0x99, 0x99, 0x99, 
 	0x99, 0xA5, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xBA, 
 	0xBB, 0x9B, 0x19, 0xCC, 0xCC, 0xDD, 0xDD, 0xEE, 
@@ -96,7 +102,9 @@ uint8_t mgmtTemplate[INTRA_MGMT_FRAME_LENGTH_MAX] __attribute__ ((aligned (8)))
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
-uint8_t rttTemplate[INTRA_RTT_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = {
+
+uint8_t rttTemplate[INTRA_RTT_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = 
+{
 	0xDC, 0xA3, 0x10, 0x44, 0x98, 0x99, 0x99, 0x99, 
 	0x99, 0x05, 0x00, 0x00, 0x00, 0x50, 0x32, 0x01, 
 	0x00, 0x90, 0x99, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 
@@ -130,7 +138,9 @@ uint8_t rttTemplate[INTRA_RTT_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) =
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
-uint8_t svcTemplate[INTRA_SVC_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = {
+
+uint8_t svcTemplate[INTRA_SVC_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) = 
+{
 	0xF0, 0xFF, 0x00, 0x21, 0x88, 0x00, 0x00, 0xF0,
 	0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0x56, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -165,8 +175,8 @@ uint8_t svcTemplate[INTRA_SVC_FRAME_LENGTH_MAX] __attribute__ ((aligned (8))) =
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xB5,
 };
 
-
-L2_CONFIG l2Config = {
+L2_CONFIG l2Config = 
+{
 	.myType = L2_NODE_HEAD,
 	.isInterHead = false,
 	.myId = 1,
@@ -178,7 +188,8 @@ L2_CONFIG l2Config = {
 	.tmcInstPtr = NULL
 };
 
-PHY_CONFIG l1Config = {
+PHY_CONFIG l1Config = 
+{
 	.devId = 0,
 	.txBramId = 0,
 	.rxBramId = 0,
@@ -186,17 +197,21 @@ PHY_CONFIG l1Config = {
 	.baseAddr = (uintptr_t)phycReg
 };
 
-TIMECTRL_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig = 
+{
 	.baseAddr = (uintptr_t)tmcReg,
 	.reset = 10
 };
 
-inline uint32_t rand_range(uint32_t a, uint32_t b){
+int32_t rand_range(uint32_t a, uint32_t b);
+inline int32_t rand_range(uint32_t a, uint32_t b)
+{
 	ASSERT(b > a);
 	return (rand() % (b + 1 - a) + a);
 }
 
-void linklayer_setup(void){
+void linklayer_setup(void)
+{
 	int32_t Status;
 	Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
 	ASSERT_EQUAL(SUCCESS, Status);
@@ -211,18 +226,20 @@ void linklayer_setup(void){
 	ASSERT_EQUAL(SUCCESS, Status);
 }
 
-void linklayer_teardown(void){
+void linklayer_teardown(void)
+{
 	Linklayer_Destroy(linkInstPtr);
 	Phy_Destroy(phyInstPtr);
 	TimeCtrl_Destroy(tmcInstPtr);
 }
 
-void forge_bm_frame(uint8_t* buff, uint8_t nodeId, uint16_t clustId, uint16_t headId, uint64_t time) {
+void forge_bm_frame(uint8_t *buff, uint8_t nodeId, uint16_t clustId, uint16_t headId, uint64_t time)
+{
 	BIT_ARRAY bitarr = {
-		.words = (uint64_t*)buff,
-		.num_of_bits = INTRA_BM_FRAME_LENGTH_MAX*8,
-		.num_of_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX*8),
-		.capacity_in_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX*8),
+		.words = (uint64_t *)buff,
+		.num_of_bits = INTRA_BM_FRAME_LENGTH_MAX * 8,
+		.num_of_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX * 8),
+		.capacity_in_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX * 8),
 	};
 	memcpy(buff, bmTemplate, INTRA_BM_FRAME_LENGTH_MAX);
 	uint64_t dataChunk;
@@ -249,13 +266,14 @@ void forge_bm_frame(uint8_t* buff, uint8_t nodeId, uint16_t clustId, uint16_t he
 	L2_CrcAppend(buff, BM_MSG_CRC_OFFSET / 8, BM_MSG_CRC_OFFSET / 8, L2_CRC8_31);
 }
 
-void forge_w2acq_frame(uint8_t* buff, L2_NODE_TYPE nodeType, uint16_t srcId, uint16_t destId, 
-						uint16_t clustId, uint32_t netStartTime, L2_NODE_STATE state) {
+void forge_w2acq_frame(uint8_t *buff, L2_NODE_TYPE nodeType, uint16_t srcId, uint16_t destId,
+					   uint16_t clustId, uint32_t netStartTime, L2_NODE_STATE state)
+{
 	BIT_ARRAY bitarr = {
-		.words = (uint64_t*)buff,
-		.num_of_bits = INTRA_W2ACQ_FRAME_LENGTH_MAX*8,
-		.num_of_words = roundup_bits2words64(INTRA_W2ACQ_FRAME_LENGTH_MAX*8),
-		.capacity_in_words = roundup_bits2words64(INTRA_W2ACQ_FRAME_LENGTH_MAX*8),
+		.words = (uint64_t *)buff,
+		.num_of_bits = INTRA_W2ACQ_FRAME_LENGTH_MAX * 8,
+		.num_of_words = roundup_bits2words64(INTRA_W2ACQ_FRAME_LENGTH_MAX * 8),
+		.capacity_in_words = roundup_bits2words64(INTRA_W2ACQ_FRAME_LENGTH_MAX * 8),
 	};
 	memcpy(buff, w2acqTemplate, INTRA_W2ACQ_FRAME_LENGTH_MAX);
 
@@ -272,7 +290,8 @@ void forge_w2acq_frame(uint8_t* buff, L2_NODE_TYPE nodeType, uint16_t srcId, uin
 	dataChunk = (destId & 0x001F) | ((clustId & 0x001F) << 5);
 	FrameInsertChunk(&bitarr, NS_MSG_INI_LEN_OFFSET, NS_MSG_INI_LEN_LEN, dataChunk);
 	/* current net stage */
-	switch (state) {
+	switch (state)
+	{
 	case L2_INIT_STATE:
 		dataChunk = NET_INI_STAGE;
 		break;
@@ -296,17 +315,19 @@ void forge_w2acq_frame(uint8_t* buff, L2_NODE_TYPE nodeType, uint16_t srcId, uin
 	L2_CrcAppend(buff, W2ACQ_FRAME_CRC_DLEN, W2ACQ_FRAME_CRC_POS, L2_CRC16_8005);
 }
 
-void forge_mgmt_frame(uint8_t* buff, L2_NODE_STATE state) {
+void forge_mgmt_frame(uint8_t *buff, L2_NODE_STATE state)
+{
 	BIT_ARRAY bitarr = {
-		.words = (uint64_t*)buff,
-		.num_of_bits = INTRA_MGMT_FRAME_LENGTH_MAX*8,
-		.num_of_words = roundup_bits2words64(INTRA_MGMT_FRAME_LENGTH_MAX*8),
-		.capacity_in_words = roundup_bits2words64(INTRA_MGMT_FRAME_LENGTH_MAX*8),
+		.words = (uint64_t *)buff,
+		.num_of_bits = INTRA_MGMT_FRAME_LENGTH_MAX * 8,
+		.num_of_words = roundup_bits2words64(INTRA_MGMT_FRAME_LENGTH_MAX * 8),
+		.capacity_in_words = roundup_bits2words64(INTRA_MGMT_FRAME_LENGTH_MAX * 8),
 	};
 	memcpy(buff, mgmtTemplate, INTRA_MGMT_FRAME_LENGTH_MAX);
 
 	uint64_t dataChunk;
-	switch (state) {
+	switch (state)
+	{
 	case L2_INIT_STATE:
 		dataChunk = NET_INI_STAGE;
 		break;
@@ -325,17 +346,18 @@ void forge_mgmt_frame(uint8_t* buff, L2_NODE_STATE state) {
 	default:
 		dataChunk = NET_ERROR_STAGE;
 		break;
-	FrameInsertChunk(&bitarr, TK_MSG_INI_NET_STATE_OFFSET, TK_MSG_INI_NET_STATE_LEN, dataChunk);
+		FrameInsertChunk(&bitarr, TK_MSG_INI_NET_STATE_OFFSET, TK_MSG_INI_NET_STATE_LEN, dataChunk);
 	}
 }
 
-void forge_rtt_frame(uint8_t* buff, uint16_t srcId, uint16_t destId, 
-					uint16_t clustId, const TIME_WORD* timeStamp, uint32_t doppler) {
+void forge_rtt_frame(uint8_t *buff, uint16_t srcId, uint16_t destId,
+					 uint16_t clustId, const TIME_WORD *timeStamp, uint32_t doppler)
+{
 	BIT_ARRAY bitarr = {
-		.words = (uint64_t*)buff,
-		.num_of_bits = INTRA_BM_FRAME_LENGTH_MAX*8,
-		.num_of_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX*8),
-		.capacity_in_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX*8),
+		.words = (uint64_t *)buff,
+		.num_of_bits = INTRA_BM_FRAME_LENGTH_MAX * 8,
+		.num_of_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX * 8),
+		.capacity_in_words = roundup_bits2words64(INTRA_BM_FRAME_LENGTH_MAX * 8),
 	};
 	memcpy(buff, rttTemplate, INTRA_BM_FRAME_LENGTH_MAX);
 	uint64_t dataChunk;
@@ -362,46 +384,63 @@ void forge_rtt_frame(uint8_t* buff, uint16_t srcId, uint16_t destId,
 	return;
 }
 
-TEST(linklayer_master_routine) {
+TEST(linklayer_reconfig)
+{
+	int32_t Status;
+	Status = Linklayer_Reconfig(linkInstPtr, &l2Config);
+	ASSERT_EQUAL(SUCCESS, Status);
+	ASSERT_EQUAL(false, linkInstPtr->isEnable);
+	ASSERT_EQUAL(false, linkInstPtr->isEnable);
+	ASSERT_EQUAL(0, linkInstPtr->nodeList->len);
+	ASSERT_EQUAL(0, linkInstPtr->schdEventPool->envCnt);
+}
+
+TEST(linklayer_master_routine)
+{
 	int32_t Status;
-	Linklayer_Start(linkInstPtr);
 	TIME_WORD timeStampA, timeStampB, timeGap;
 	uint32_t timeDiff;
+	l2Config.myType = L2_NODE_HEAD;
+	l2Config.myId = 1;
+	Status = Linklayer_Reconfig(linkInstPtr, &l2Config);
+	ASSERT_EQUAL(SUCCESS, Status);
 	// 30 seconds
-	for(int i = 0; i < 200*30; i++) {
+	Linklayer_Start(linkInstPtr);
+	for (int i = 0; i < 30 * L2_SLOTS_PER_FRAME; i++)
+	{
 		tmcReg[TIME_INT_REG]++;
 
-		if (L2_GetNextTor(linkInstPtr) == L2_TOR_TX) 
+		if (L2_GetNextTor(linkInstPtr) == L2_TOR_TX)
 		{
 			if (L2_GetNextFrameType(linkInstPtr) == L2_INTRA_TSYNC_FRAME)
 			{
 				TimeCtrl_GetCurrentTime(tmcInstPtr, &timeStampA);
-				// ASSERT_EQUAL(linkInstPtr->rttFSM->rttRecord.Tt1.int_part + linkInstPtr->netStartTime*L2_SLOTS_PER_FRAME, 
+				// ASSERT_EQUAL(linkInstPtr->rttFSM->rttRecord.Tt1.int_part + linkInstPtr->netStartTime*L2_SLOTS_PER_FRAME,
 				// 				timeStampA.int_part);
 				// ASSERT_EQUAL(linkInstPtr->rttFSM->rttRecord.Tt1.frac_part, timeStampA.frac_part);
-				timeStampA.frac_part = rand()%1000; // 10us deviation.
-				
+				timeStampA.frac_part = rand_range(0, 1000); // up to 10us deviation.
 			}
 		}
 		if (L2_GetCurrentTor(linkInstPtr) == L2_TOR_RX)
 		{
-			if(L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_W2_ACQ_FRAME) {
-				forge_w2acq_frame((uint8_t*)phyInstPtr->recvDataAddr, L2_NODE_MEMBER, 2, 1, 1, -1, L2_INIT_STATE);
+			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_W2_ACQ_FRAME)
+			{
+				forge_w2acq_frame((uint8_t *)phyInstPtr->recvDataAddr, L2_NODE_MEMBER, 2, 1, 1, -1, L2_INIT_STATE);
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
 				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_W2ACQ_FRAME_LENGTH_MAX);
 			}
 
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_MGMT_FRAME)
 			{
-				forge_mgmt_frame((uint8_t*)phyInstPtr->recvDataAddr, L2_NORMAL_STATE);
+				forge_mgmt_frame((uint8_t *)phyInstPtr->recvDataAddr, L2_NORMAL_STATE);
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
 				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_MGMT_FRAME_LENGTH_MAX);
 			}
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_TSYNC_FRAME)
 			{
-				timeDiff = Phy_GetTimeComp(L2_L2frame2L1frame(L2_INTRA_TSYNC_FRAME)) + (rand()-RAND_MAX)%1000;
+				timeDiff = Phy_GetTimeComp(L2_L2frame2L1frame(L2_INTRA_TSYNC_FRAME)) + (rand() - RAND_MAX) % 1000;
 				TimeCtrl_CalculateTimeGap(&timeStampA, &timeStampB, &timeGap);
-				forge_rtt_frame((uint8_t*)phyInstPtr->recvDataAddr, 2, 1, 1, &timeGap , rand()%200000);
+				forge_rtt_frame((uint8_t *)phyInstPtr->recvDataAddr, 2, 1, 1, &timeGap, rand() % 200000);
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
 				PhyWrite(phyInstPtr, FSTIME_H, L2_GetLastFrameNum(linkInstPtr));
 				PhyWrite(phyInstPtr, FSTIME_L, timeDiff);
@@ -410,12 +449,13 @@ TEST(linklayer_master_routine) {
 
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_SVC_FRAME)
 			{
-				forge_mgmt_frame((uint8_t*)phyInstPtr->recvDataAddr, L2_NORMAL_STATE);
+				forge_mgmt_frame((uint8_t *)phyInstPtr->recvDataAddr, L2_NORMAL_STATE);
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
 				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_MGMT_FRAME_LENGTH_MAX);
 			}
 		}
-		else {
+		else
+		{
 			PhyWrite(phyInstPtr, TXRX_STATE, 0x02020202);
 		}
 
@@ -423,15 +463,19 @@ TEST(linklayer_master_routine) {
 
 		Status = Linklayer_Proc(linkInstPtr);
 
-		if((tmcReg[TIME_INT_REG]+1)/200 < linkInstPtr->netStartTime) {
+		if ((tmcReg[TIME_INT_REG] + 1) / 200 < linkInstPtr->netStartTime)
+		{
 			ASSERT_EQUAL(EIGNORE, Status);
 		}
-		else{
+		else
+		{
 			ASSERT_EQUAL(SUCCESS, Status);
 		}
 
-		if(L2_isDataAvail(linkInstPtr)) {
-			if(L2_GetLastFrameType(linkInstPtr) == L2_INTRA_W2_ACQ_FRAME) {
+		if (L2_isDataAvail(linkInstPtr))
+		{
+			if (L2_GetLastFrameType(linkInstPtr) == L2_INTRA_W2_ACQ_FRAME)
+			{
 				ASSERT_EQUAL(1, L2_GetNodeListLen(linkInstPtr->nodeList));
 				ASSERT_TRUE(L2_isNodeInList(linkInstPtr->nodeList, 2));
 			}
@@ -439,23 +483,126 @@ TEST(linklayer_master_routine) {
 	}
 }
 
-
-TEST(linklayer_reconfig) {
+TEST(linklayer_slave_netsetup)
+{
 	int32_t Status;
+	TIME_WORD timeStampA, timeStampB, timeGap;
+	TIME_WORD bmTime;
+	uint32_t netStart, timeDiff;
+	// 30 seconds
+	l2Config.myType = L2_NODE_MEMBER;
+	l2Config.myId = 2;
 	Status = Linklayer_Reconfig(linkInstPtr, &l2Config);
-	ASSERT_EQUAL(SUCCESS, Status);
+	tmcReg[TIME_FRAC_REG] = rand_range(0, TIME_FRAC_MAX);
+	tmcReg[TIME_INT_REG] = rand_range(0, 60 * L2_SLOTS_PER_FRAME); // 0~60s
+	bmTime.frac_part = rand_range(0, TIME_FRAC_MAX);
+	bmTime.int_part = rand_range(tmcReg[TIME_INT_REG], tmcReg[TIME_INT_REG] + 5 * L2_SLOTS_PER_FRAME);
+
+	// 74 is the index of bm frame in routine table.
+	netStart = bmTime.int_part % L2_SLOTS_PER_FRAME + rand_range(-12, 12);
+
+	Linklayer_Start(linkInstPtr);
+	for (int i = 0; i < 12 * L2_SLOTS_PER_FRAME * TIME_FRAC_MAX; i++)
+	{
+		tmcReg[TIME_FRAC_REG]++;
+		if (tmcReg[TIME_FRAC_REG] >= TIME_FRAC_MAX)
+		{
+			tmcReg[TIME_FRAC_REG] = 0;
+			tmcReg[TIME_INT_REG]++;
+		}
+
+		if (tmcReg[TIME_FRAC_REG] == bmTime.frac_part && tmcReg[TIME_INT_REG] == bmTime.int_part)
+		{
+			forge_bm_frame((uint8_t *)phyInstPtr->recvDataAddr, 1, 1, 1, netStart);
+			PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
+			PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_BM_FRAME_LENGTH_MAX);
+		}
+
+		if (L2_GetNextTor(linkInstPtr) == L2_TOR_TX)
+		{
+			if (L2_GetNextFrameType(linkInstPtr) == L2_INTRA_TSYNC_FRAME)
+			{
+				TimeCtrl_GetCurrentTime(tmcInstPtr, &timeStampA);
+				timeStampA.frac_part = rand_range(0, 1000); // up to 10us deviation.
+			}
+		}
+		if (L2_GetCurrentTor(linkInstPtr) == L2_TOR_RX)
+		{
+			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_W2_ACQ_FRAME)
+			{
+				forge_w2acq_frame((uint8_t *)phyInstPtr->recvDataAddr, L2_NODE_MEMBER, 2, 1, 1, -1, L2_INIT_STATE);
+				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
+				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_W2ACQ_FRAME_LENGTH_MAX);
+			}
+
+			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_MGMT_FRAME)
+			{
+				forge_mgmt_frame((uint8_t *)phyInstPtr->recvDataAddr, L2_NORMAL_STATE);
+				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
+				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_MGMT_FRAME_LENGTH_MAX);
+			}
+			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_TSYNC_FRAME)
+			{
+				timeDiff = Phy_GetTimeComp(L2_L2frame2L1frame(L2_INTRA_TSYNC_FRAME)) + (rand() - RAND_MAX) % 1000;
+				TimeCtrl_CalculateTimeGap(&timeStampA, &timeStampB, &timeGap);
+				forge_rtt_frame((uint8_t *)phyInstPtr->recvDataAddr, 2, 1, 1, &timeGap, rand() % 200000);
+				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
+				PhyWrite(phyInstPtr, FSTIME_H, L2_GetLastFrameNum(linkInstPtr));
+				PhyWrite(phyInstPtr, FSTIME_L, timeDiff);
+				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_MGMT_FRAME_LENGTH_MAX);
+			}
+
+			if (L2_GetCurrentFrameType(linkInstPtr) == L2_INTRA_SVC_FRAME)
+			{
+				forge_mgmt_frame((uint8_t *)phyInstPtr->recvDataAddr, L2_NORMAL_STATE);
+				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
+				PhyWrite(phyInstPtr, RECVDATA_STATE, INTRA_MGMT_FRAME_LENGTH_MAX);
+			}
+		}
+		else
+		{
+			PhyWrite(phyInstPtr, TXRX_STATE, 0x02020202);
+		}
+		if (PhyRead(phyInstPtr, TXRX_STATE) != 0x02020202)
+		{
+			Phy_UpdateState(phyInstPtr);
+		}
+
+		if (tmcReg[TIME_FRAC_REG] == 200000)
+		{ // 2ms
+			Status = Linklayer_Proc(linkInstPtr);
+			if ((tmcReg[TIME_INT_REG] + 1) / 200 < linkInstPtr->netStartTime)
+			{
+				ASSERT_EQUAL(EIGNORE, Status);
+			}
+			else
+			{
+				ASSERT_EQUAL(SUCCESS, Status);
+			}
+
+			if (L2_isDataAvail(linkInstPtr))
+			{
+				if (L2_GetLastFrameType(linkInstPtr) == L2_INTRA_W2_ACQ_FRAME)
+				{
+					ASSERT_EQUAL(1, L2_GetNodeListLen(linkInstPtr->nodeList));
+					ASSERT_TRUE(L2_isNodeInList(linkInstPtr->nodeList, 2));
+				}
+			}
+		}
+	}
 }
 
-TEST_SUITE(linklayer_unit_test) {
+TEST_SUITE(linklayer_unit_test)
+{
 	TEST_SUITE_CONFIGURE(linklayer_setup, linklayer_teardown);
-	RUN_TEST(linklayer_master_routine);
 	RUN_TEST(linklayer_reconfig);
+	RUN_TEST(linklayer_master_routine);
+	RUN_TEST(linklayer_slave_netsetup);
 }
 
-int main(void) {
+int main(void)
+{
 	RUN_TEST_SUITE(linklayer_unit_test);
 	TEST_REPORT();
 	return TEST_EXIT_CODE;
 }
-
-

datalink814_ge/unit_test/tmc_board_unit_test.c

@@ -7,11 +7,11 @@
 #define HARDWARE_VERSION 0x00000001
 #define MAX_OPT_DELAY 100 // 1us = 100*10ns
 
-TIMECTRL_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig = {
 	.baseAddr = 0 /*TODO: fill withe real base address*/,
 	.reset = 10};
 
-TIMECTRL_INST *tmcInstPtr = NULL;
+TMC_INST *tmcInstPtr = NULL;
 
 void tmc_setup(void)
 {

datalink814_ge/unit_test/tmc_emulate_unit_test.c

@@ -11,11 +11,11 @@
 
 uint32_t tmcReg[32] = {0};
 
-TIMECTRL_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig = {
 	.baseAddr = 0,
 	.reset = 10};
 
-TIMECTRL_INST *tmcInstPtr = NULL;
+TMC_INST *tmcInstPtr = NULL;
 
 void tmc_setup(void)
 {

datalink814_sp/build/src/phy_ctrl/subdir.mk

@@ -3,17 +3,13 @@
 ################################################################################
 
 # Add inputs and outputs from these tool invocations to the build variables 
-C_SRCS += \
-../src/phy_ctrl/antenna.c \
-../src/phy_ctrl/phy_ctrl.c 
+PHY_CTRL_SRC := $(wildcard ../src/phy_ctrl/*.c)
 
-OBJS += \
-./src/phy_ctrl/antenna.o \
-./src/phy_ctrl/phy_ctrl.o 
+C_SRCS += $(PHY_CTRL_SRC)
 
-C_DEPS += \
-./src/phy_ctrl/antenna.d \
-./src/phy_ctrl/phy_ctrl.d 
+OBJS += $(patsubst ../src/phy_ctrl/%.c, ./src/phy_ctrl/%.o, $(PHY_CTRL_SRC))
+
+C_DEPS += $(patsubst ../src/phy_ctrl/%.c, ./src/phy_ctrl/%.d, $(PHY_CTRL_SRC))
 
 
 # Each subdirectory must supply rules for building sources it contributes

datalink814_sp/build/src/time_ctrl/subdir.mk

@@ -3,14 +3,13 @@
 ################################################################################
 
 # Add inputs and outputs from these tool invocations to the build variables 
-C_SRCS += \
-../src/time_ctrl/time_ctrl.c 
+TIME_CTRL_SRC := $(wildcard ../src/time_ctrl/*.c)
 
-OBJS += \
-./src/time_ctrl/time_ctrl.o 
+C_SRCS += $(TIME_CTRL_SRC)
 
-C_DEPS += \
-./src/time_ctrl/time_ctrl.d 
+OBJS += $(patsubst ../src/time_ctrl/%.c, ./src/time_ctrl/%.o, $(TIME_CTRL_SRC))
+
+C_DEPS += $(patsubst ../src/time_ctrl/%.c, ./src/time_ctrl/%.d, $(TIME_CTRL_SRC))
 
 
 # Each subdirectory must supply rules for building sources it contributes

datalink814_sp/src/inter_comm/inter_comm.c

@@ -1,18 +1,18 @@
 /*****************************************************************************/
 /**
  * Description: Inter-Communication protocol implementation.
- * 
+ *
  * Date: 2022-06-18 16:37
  * LastEditTime: 2023-04-24 17:38
  * Revisions: Rev 0.1
- * History: 
+ * History:
  * [2022-06-18]: Initial version.
  * [2023-04-24]: Bug fix:
  * 				- Read frame type from PL status register.
  *
  * Copyright(c) 2022 Beijing Institute of Technology.
  * Lab of Communication and Networking
- * 
+ *
 ******************************************************************************/
 /***************************** Include Files *********************************/
 #include <stdint.h>
@@ -113,7 +113,7 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 	PHY_INST* phyRef = instPtr->phyInstPtr;
 	L1_FRAME_TYPE frameType = L1_NONE_FRAME;
 	PHY_TOR_TYPE torState = PHY_TOR_SUSPEND;
-	PHY_ANT_BEAM_WIDTH beamWidth = ANT_BEAM_NONE;
+	PHY_ANT_BEAM_WIDTH beamWidth = PHY_ANT_BEAM_NONE;
 	uint32_t beamNo = 0;
 
 	uint16_t msg_Recv = 0;
@@ -130,7 +130,7 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 		torState = PHY_TOR_RX;
 	}
 	else{
-		DBG_ERROR("[PHY Control] Tx/Rx state cannot be recognized...\n\r");
+		DBG_ERROR("[PHY Control] Tx/Rx state cannot be recognized...\n");
 		return EIGNORE;
 	}
 	instPtr->lastCtrlTimeTag = GetTimeWord(msgPtr+CTRL_TIME_OFFSET);
@@ -165,7 +165,7 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 		frameType = L1_40KBPS_20MS_FRAME;
 		break;
 	default:
-		DBG_ERROR("[PHY Control] Frame Type cannot be recognized...\n\r");
+		DBG_ERROR("[PHY Control] Frame Type cannot be recognized...\n");
 		return EIGNORE;
 		break;
 	}
@@ -187,8 +187,8 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 		phyRef->isPresetHop = false;
 	}
 	else{
-		DBG_ERROR("[PHY Control] Hopping Pattern Configure cannot be recognized...\n\r");
-		DBG_WARNING("[PHY Control] Using default preset hopping pattern instead...\n\r");
+		DBG_ERROR("[PHY Control] Hopping Pattern Configure cannot be recognized...\n");
+		DBG_WARNING("[PHY Control] Using default preset hopping pattern instead...\n");
 		return EIGNORE;
 	}
 	if(phyRef->isPresetHop == false){
@@ -199,17 +199,17 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 		}
 	}
 	if(msgPtr[INTER_MSG_CTRL_BEAM_MODE_OFFSET] == BEAM_MODE_WIDE){
-		beamWidth = ANT_BEAM_120;
+		beamWidth = PHY_ANT_BEAM_120;
 	}
 	else if(msgPtr[INTER_MSG_CTRL_BEAM_MODE_OFFSET] == BEAM_MODE_SUBNRW){
-		beamWidth = ANT_BEAM_25;
+		beamWidth = PHY_ANT_BEAM_25;
 	}
 	else if(msgPtr[INTER_MSG_CTRL_BEAM_MODE_OFFSET] == BEAM_MODE_NRW){
-		beamWidth = ANT_BEAM_8;
+		beamWidth = PHY_ANT_BEAM_16;
 	}
 	else{
-		DBG_ERROR("[PHY Control] Beam Width Configure cannot be recognized...\n\r");
-		DBG_WARNING("[PHY Control] Using default WILD beam (120 deg) instead...\n\r");
+		DBG_ERROR("[PHY Control] Beam Width Configure cannot be recognized...\n");
+		DBG_WARNING("[PHY Control] Using default WILD beam (120 deg) instead...\n");
 		return EIGNORE;
 	}
 	Status = Phy_SetBeamWidth(phyRef, beamWidth);
@@ -217,15 +217,15 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 		return Status;
 	}
 	beamNo = (uint32_t)msgPtr[INTER_MSG_CTRL_BEAM_NO_OFFSET];
-	if((beamNo<NUM_ANT_SUBNRRW_PATTERN && beamWidth == ANT_BEAM_25)
-		||(beamNo<NUM_ANT_NRRW_PATTERN && beamWidth == ANT_BEAM_8)
-		|| (beamNo == 0 && beamWidth == ANT_BEAM_120)){
-		Phy_SetBeamNo(phyRef, beamNo);
+	if((beamNo<L1_NUM_ANT_SUBNRRW_PATTERN && beamWidth == PHY_ANT_BEAM_25)
+		||(beamNo<L1_NUM_ANT_NRRW_PATTERN && beamWidth == PHY_ANT_BEAM_16)
+		|| (beamNo == 0 && beamWidth == PHY_ANT_BEAM_120)){
+		Phy_SetBeamNo(phyRef, beamNo, beamWidth);
 	}
 	else{
 		if(beamNo != 0x000000FF){
-			DBG_ERROR("[PHY Control] Beam Number Configure cannot be recognized...\n\r");
-			DBG_WARNING("[PHY Control] Using Beam Angle configure instead...\n\r");
+			DBG_ERROR("[PHY Control] Beam Number Configure cannot be recognized...\n");
+			DBG_WARNING("[PHY Control] Using Beam Angle configure instead...\n");
 			return EIGNORE;
 		}
 		// the angle config is a 16 bit fixed point data
@@ -242,10 +242,39 @@ static int32_t EvalPhyConfig(INTER_COMM_INST* instPtr, uint8_t* msgPtr){
 		}
 	}
 
+	// Power Mode and Attenuation control
+	if (msgPtr[INTER_MSG_CTRL_POWER_OFFSET] == CTRL_POWER_LOW)
+	{
+		Phy_AntConfigMode(phyRef, PHY_ANT_MODE_POWER_LOW);
+	}
+	else if (msgPtr[INTER_MSG_CTRL_POWER_OFFSET] == CTRL_POWER_FULL)
+	{
+		Phy_AntConfigMode(phyRef, PHY_ANT_MODE_POWER_FULL);
+	}
+	else
+	{
+		DBG_ERROR("[PHY Control] Unsupported power mode [0x%02X]\n",
+				msgPtr[INTER_MSG_CTRL_POWER_OFFSET]);
+		return FAILURE;
+	}
+	if(msgPtr[INTER_MSG_CTRL_RXATT_OFFSET] <= INTER_MSG_CTRL_RXATT_MAX
+		&& msgPtr[INTER_MSG_CTRL_TXATT_OFFSET] <= INTER_MSG_CTRL_TXATT_MAX)
+	{
+		Phy_AntConfigAttenuation(phyRef,
+								msgPtr[INTER_MSG_CTRL_RXATT_OFFSET],
+								msgPtr[INTER_MSG_CTRL_TXATT_OFFSET]
+		);
+	}
+	else
+	{
+		DBG_ERROR("[PHY Control] Attenuation exceeds max range.\n");
+		return FAILURE;
+	}
+
 	TIME_WORD tmWord = {0};
 	tmWord.int_part = (uint32_t)(instPtr->lastCtrlTimeTag >> 32);
 	tmWord.frac_part = (uint32_t)(instPtr->lastCtrlTimeTag);
-	Status = Phy_SetTimeWord(phyRef, &tmWord, TIME_WORD_POLL);
+	Status = Phy_SetTimeWord(phyRef, &tmWord, PHY_TIME_WORD_POLL);
 	Status = Phy_SetMode(phyRef, PHY_MODE_PULL);
 	Status = Phy_SetupNextSlot(phyRef, torState, frameType, instPtr->phySendBuff);
 
@@ -305,13 +334,13 @@ int32_t InterComm_Init(INTER_COMM_INST** instPtr, INTER_COMM_CONFIG* configPtr){
 	}
 
 	// Initial physical buffer
-	(*instPtr)->phyRecvBuff = calloc(TXRXDATA_MAX_LEN/sizeof(uint32_t), sizeof(uint32_t));
+	(*instPtr)->phyRecvBuff = calloc(L1_TXRXDATA_MAX_LEN/sizeof(uint32_t), sizeof(uint32_t));
 	if ((*instPtr)->phyRecvBuff == NULL) {
 		Status = EALLOC;
 		goto init_failed;
 	}
 
-	(*instPtr)->phySendBuff = calloc(TXRXDATA_MAX_LEN/sizeof(uint32_t), sizeof(uint32_t));
+	(*instPtr)->phySendBuff = calloc(L1_TXRXDATA_MAX_LEN/sizeof(uint32_t), sizeof(uint32_t));
 	if ((*instPtr)->phySendBuff == NULL) {
 		Status = EALLOC;
 		goto init_failed;
@@ -499,16 +528,42 @@ int32_t InterComm_MsgHandler(INTER_COMM_INST* instPtr){
 		break;
 	}
 	case INTER_MSG_MODESW_CODE:{
-		if(msgRecvPtr[MODESW_MODE_OFFSET] == MODESW_MODE_NORMAL){
+		if(msgRecvPtr[MODESW_MODE_OFFSET] == MODESW_MODE_NORMAL)
+		{
 			Phy_SetMode(instPtr->phyInstPtr, PHY_MODE_PULL);
 		}
-		else if(msgRecvPtr[MODESW_MODE_OFFSET] == MODESW_MODE_NETSET){
+		else if(msgRecvPtr[MODESW_MODE_OFFSET] == MODESW_MODE_NETSET)
+		{
+			PHY_INST* phyRef = instPtr->phyInstPtr;
+			// Power Mode and Attenuation control
+			if (msgRecvPtr[MODESW_POWER_OFFSET] == CTRL_POWER_LOW)
+			{
+				Phy_AntConfigMode(phyRef, PHY_ANT_MODE_POWER_LOW);
+			}
+			else if (msgRecvPtr[MODESW_POWER_OFFSET] == CTRL_POWER_FULL)
+			{
+				Phy_AntConfigMode(phyRef, PHY_ANT_MODE_POWER_FULL);
+			}
+			else
+			{
+				DBG_ERROR("[PHY Control] Unsupported power mode [0x%02X]\n",
+						msgRecvPtr[MODESW_POWER_OFFSET]);
+				break;
+			}
+			if(msgRecvPtr[MODESW_RXATT_OFFSET] <= MODESW_RXATT_MAX)
+			{
+				Phy_AntConfigAttenuation(phyRef, msgRecvPtr[MODESW_RXATT_OFFSET], MODESW_TXATT_SKIP);
+			}
+			else
+			{
+				DBG_ERROR("[PHY Control] Attenuation exceeds max range.\n");
+			}
 			uint64_t timeTemp;
 			TIME_WORD tmWord;
 			timeTemp = GetTimeWord(msgRecvPtr + MODESW_START_TIME_OFFSET);
 			tmWord.int_part = (uint32_t)(timeTemp>>32);;
 			tmWord.frac_part = (uint32_t)(timeTemp);
-			Status = Phy_SetTimeWord(instPtr->phyInstPtr, &tmWord, TIME_WORD_POLL);
+			Status = Phy_SetTimeWord(phyRef, &tmWord, PHY_TIME_WORD_POLL);
 			if(Status != SUCCESS){
 				return EPARAM;
 			}
@@ -516,7 +571,7 @@ int32_t InterComm_MsgHandler(INTER_COMM_INST* instPtr){
 			if(timeTemp == 0){
 				tmWord.frac_part = 0;
 				tmWord.int_part = 0;
-				Status = Phy_SetTimeWord(instPtr->phyInstPtr, &tmWord, TIME_WORD_LISTEN_TIMEOUT);
+				Status = Phy_SetTimeWord(phyRef, &tmWord, PHY_TIME_WORD_LISTEN_TIMEOUT);
 				if(Status != SUCCESS){
 					return EPARAM;
 				}
@@ -524,16 +579,16 @@ int32_t InterComm_MsgHandler(INTER_COMM_INST* instPtr){
 			else{
 				tmWord.frac_part += (uint32_t)(timeTemp);
 				tmWord.int_part += (uint32_t)(timeTemp>>32);
-				tmWord.int_part = (tmWord.frac_part >= TMWORD_FRAC_MAX) ? tmWord.int_part + 1:tmWord.int_part;
-				tmWord.frac_part %= TMWORD_FRAC_MAX;
-				Status = Phy_SetTimeWord(instPtr->phyInstPtr, &tmWord, TIME_WORD_LISTEN_TIMEOUT);
+				tmWord.int_part = (tmWord.frac_part >= TIME_FRAC_MAX) ? tmWord.int_part + 1:tmWord.int_part;
+				tmWord.frac_part %= TIME_FRAC_MAX;
+				Status = Phy_SetTimeWord(phyRef, &tmWord, PHY_TIME_WORD_LISTEN_TIMEOUT);
 				if(Status != SUCCESS){
 					return EPARAM;
 				}
 			}
-			instPtr->phyInstPtr->isPresetHop = true ;
-			Status = Phy_SetMode(instPtr->phyInstPtr, PHY_MODE_LISTEN);
-			Status = Phy_SetupNextSlot(instPtr->phyInstPtr, PHY_TOR_RX, L1_10KBPS_20MS_FRAME, NULL);
+			phyRef->isPresetHop = true ;
+			Status = Phy_SetMode(phyRef, PHY_MODE_LISTEN);
+			Status = Phy_SetupNextSlot(phyRef, PHY_TOR_RX, L1_10KBPS_20MS_FRAME, NULL);
 		}
 		else{
 			return EPARAM;
@@ -702,18 +757,18 @@ int32_t InterComm_PhyDataUpload(INTER_COMM_INST* instPtr){
 	instPtr->lastPhyTimeTag = fsTimeL;
 	instPtr->lastPhyTimeTag |= ((uint64_t)fsTimeH)<<32;
 	uint32_t timeComp = Phy_GetTimeComp(lastFrameType);
-	if(timeComp == L1_FRAME_NONE_COMP){
+	if(timeComp == TIME_FRAC_MAX){
 		return FAILURE;
 	}
-	fsTimeH -= timeComp/TMWORD_FRAC_MAX;
-	timeComp %= TMWORD_FRAC_MAX;
+	fsTimeH -= timeComp/TIME_FRAC_MAX;
+	timeComp %= TIME_FRAC_MAX;
 	fsTimeH = (fsTimeL < timeComp)?(fsTimeH - 1):fsTimeH;
-	fsTimeL = (fsTimeL < timeComp)?(TMWORD_FRAC_MAX + fsTimeL - timeComp) : (fsTimeL - timeComp);
+	fsTimeL = (fsTimeL < timeComp)?(TIME_FRAC_MAX + fsTimeL - timeComp) : (fsTimeL - timeComp);
 	memcpy(txMsgBuff+DSEGRD_TIME_OFFSET, &fsTimeL, DSEGRD_TIME_LEN/2);
 	memcpy(txMsgBuff+DSEGRD_TIME_OFFSET + DSEGRD_TIME_LEN/2, &fsTimeH, DSEGRD_TIME_LEN/2);
 
 	// Doppler Estimate
-	double doppler = Phy_GetCoarseFreqEst(instPtr->phyInstPtr);
+	double doppler = Phy_GetFreqEst(instPtr->phyInstPtr);
 	// LSB = 0.001Hz
 	int64_t dopplerQnt = doppler*1000;
 	memcpy(txMsgBuff+DSEGRD_DPL_OFFSET, &dopplerQnt, DSEGRD_DPL_LEN);
@@ -787,13 +842,13 @@ int32_t InterComm_PhyDataUpload(INTER_COMM_INST* instPtr){
 /*****************************************************************************/
 /**
  * @brief   Append frame CRC-16 result to frame data buffer.
- * 
+ *
  * @param   buffPtr
  * @param   dataLen
- * 
+ *
  * @return  SUCCESS append successfully
  *          Other frame cannot be recognized.
- * 
+ *
  ******************************************************************************/
 int AppendCrc(uint8_t* buffPtr, uint32_t dataLen) {
 	ASSERT(buffPtr != NULL);
@@ -822,13 +877,13 @@ int AppendCrc(uint8_t* buffPtr, uint32_t dataLen) {
 /**
  * @brief   Check the frame CRC-16, witch can infer the frame should be dump
  *          or not.
- * 
+ *
  * @param   frameBuffPtr
  * @param   frameType
- * 
+ *
  * @return  true CRC check passed, good frame.
  *          false CRC check failed, bad frame.
- * 
+ *
  ******************************************************************************/
 bool CrcCheck(uint8_t* buffPtr, uint32_t dataLen){
 	if (dataLen == 0) {

datalink814_sp/src/inter_comm/inter_comm.h

@@ -1,19 +1,19 @@
 /*****************************************************************************/
 /**
- * Description: Inter-Communication protocol, definitions and function 
+ * Description: Inter-Communication protocol, definitions and function
  * prototypes.
- * 
+ *
  * Date: 2022-06-18 16:37
  * LastEditTime: 2023-04-24 17:38
  * Revisions: Rev 0.2
- * History: 
+ * History:
  * [2022-06-18]: Initial version.
  * [2023-04-24]: Bug fix:
  * 				- Read frame type from PL status register.
- * 
+ *
  * Copyright(c) 2022 Beijing Institute of Technology.
  * Lab of Communication and Networking
- * 
+ *
 ******************************************************************************/
 #ifndef INTER_COMM_H_
 #define INTER_COMM_H_
@@ -65,7 +65,7 @@
 #define WAKE_CMD_LPW_UP		0xCCCC
 
 // mode swicth command
-#define INTER_MSG_MODESW_LEN	0x0016 // 20byte + crc
+#define INTER_MSG_MODESW_LEN	0x0018 // 22byte + crc
 #define INTER_MSG_MODESW_CODE	0x0041
 #define MODESW_START_TIME_OFFSET	0x0002
 #define MODESW_START_TIME_LEN		0x0008
@@ -75,6 +75,14 @@
 #define MODESW_MODE_LEN				0x0002
 #define MODESW_MODE_NORMAL			0x0001
 #define MODESW_MODE_NETSET			0x0002
+#define MODESW_POWER_OFFSET			0x0014
+#define MODESW_POWER_LEN			0x0001
+#define MODESW_POWER_LOW			0xAA
+#define MODESW_POWER_FULL			0xCC
+#define MODESW_RXATT_OFFSET			0x0015
+#define MODESW_RXATT_LEN			0x0001
+#define MODESW_RXATT_MAX			0x1F
+#define MODESW_TXATT_SKIP			0xFF
 
 // physical layer control
 #define INTER_MSG_CTRL_LEN	0x00BC // 186byte + 2byte crc
@@ -108,11 +116,10 @@
 #define CTRL_TOR_TX				0xAA
 #define CTRL_TOR_RX				0xCC
 
-#define INTER_MSG_CTRL_SW_OFFSET	0x000D
-#define INTER_MSG_CTRL_SW_LEN	0x0001
-#define CTRL_SW_PW	BIT(0)
-#define CTRL_SW_TR	BIT(1)
-#define CTRL_SW_TOR	BIT(2)
+#define INTER_MSG_CTRL_POWER_OFFSET	0x000D
+#define INTER_MSG_CTRL_POWER_LEN	0x0001
+#define CTRL_POWER_LOW	0xAA
+#define CTRL_POWER_FULL	0xCC
 
 #define INTER_MSG_CTRL_HOP_MODE_OFFSET	0x000E
 #define INTER_MSG_CTRL_HOP_MODE_LEN		0x0002
@@ -132,8 +139,12 @@
 #define INTER_MSG_CTRL_BEAM_NO_OFFSET 0x00B3
 #define INTER_MSG_CTRL_BEAM_NO_LEN	0x0001
 
-#define INTER_MSG_CTRL_AMP_WT_OFFSET 0x00B4
-#define INTER_MSG_CTRL_AMP_WT_LEN	0x0002
+#define INTER_MSG_CTRL_RXATT_OFFSET 0x00B4
+#define INTER_MSG_CTRL_RXATT_LEN 0x0001
+#define INTER_MSG_CTRL_RXATT_MAX 0x1F
+#define INTER_MSG_CTRL_TXATT_OFFSET 0x00B5
+#define INTER_MSG_CTRL_TXATT_LEN 0x0001
+#define INTER_MSG_CTRL_TXATT_MAX 0x1F
 
 #define INTER_MSG_CTRL_OFFAX_OFFSET 0x00B6
 #define INTER_MSG_CTRL_OFFAX_LEN	0x0002

datalink814_sp/src/main.c

@@ -429,7 +429,7 @@ int32_t Intercom_C2cRecvData(void* buffPtr, int32_t buffSize){
 			return FAILURE;
 		}
 	}
-	
+
 	uint32_t recvLen = IO_In32((uintptr_t)(c2cRecvDataPtr + C2C_DLEN_OFFSET)) - C2C_HEADER_LEN;
 	memcpy(buffPtr, c2cRecvDataPtr + C2C_PLOAD_OFFSET, recvLen);
 
@@ -747,7 +747,7 @@ int main(void) {
 			else{
 				Status = InterComm_MsgHandler(intrCommInstPtr);
 				if(Status != SUCCESS){
-					DBG_PRINT("####\tInterComm message handler finished with code: %d\n\r", Status);
+					DBG_PRINT("####\tInterComm message handler finished with code: %d\n", Status);
 					continue;
 				}
 			}

df_datalink/bsp/Makefile

@@ -1,35 +0,0 @@
-# Makefile generated by Xilinx.
-
-PROCESSOR = ps7_cortexa9_0
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
-SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
-
-ifneq (,$(findstring win,$(RDI_PLATFORM)))
- SHELL = CMD
-endif
-
-all: libs
-	@echo 'Finished building libraries'
-
-include: $(addsuffix /make.include,$(SUBDIRS))
-
-libs: $(addsuffix /make.libs,$(SUBDIRS))
-
-clean: $(addsuffix /make.clean,$(SUBDIRS))
-
-$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
-	cp -f $< $@
-
-%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
-	@echo "Running Make include in $(subst /make.include,,$@)"
-	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=$(CC)" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-DDEBUG -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wformat=2 -Wextra"
-
-%/make.libs: include
-	@echo "Running Make libs in $(subst /make.libs,,$@)"
-	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=$(CC)" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-DDEBUG -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wformat=2 -Wextra"
-
-%/make.clean: 
-	$(MAKE) -C $(subst /make.clean,,$@) -s clean 
-clean:
-	rm -f ${PROCESSOR}/lib/libxil.a

df_datalink/bsp/ps7_cortexa9_0/include/_profile_timer_hw.h

@@ -1,308 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_timer_hw.h:
-*	Timer related functions
-*
-******************************************************************************/
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-#  define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-#  define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
-	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
-			   (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
-	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
-	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
-					   (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
-	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif	/* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- *	1. XTime_PITDisableInterrupt() ;
- *	2. Store the remaining timer clk tick
- *	3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() 		\
-	{				\
-		u32 val;	\
-		val=mfspr(XREG_SPR_TCR);	\
-		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
-		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
-		mtspr(XREG_SPR_PIT, 0);	\
-	}
-#else
-#define disable_timer() 	\
-   { \
-      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
-      u32 tmp_v = ProfIo_In32(addr); \
-      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
-      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
-   }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- *	1. Load the remaining timer clk ticks
- *	2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer()				\
-	{					\
-		u32 val;		\
-		val=mfspr(XREG_SPR_TCR);	\
-		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
-		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
-	}
-#else
-#define enable_timer()						\
-	{							\
-      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
-      u32 tmp_v = ProfIo_In32(addr); \
-      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
-      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
-	}
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 	1. Load the timer clk ticks
- *	2. Enable AutoReload and Interrupt
- *	3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack()							\
-	{								\
-		u32 val;					\
-		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
-		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
-		val=mfspr(XREG_SPR_TCR);				\
-		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
-	}
-#else
-#define timer_ack()				\
-	{						\
-		u32 csr;			\
-		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
-		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
-	}
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif	/* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer()					\
-	{						\
-      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
-	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
-	  Addr += (u32)XTC_TCSR_OFFSET; \
-      u32 tmp_v = ProfIo_In32(Addr); \
-      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
-      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
-      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
-      OutAddr += (u32)XTC_TCSR_OFFSET; \
-      ProfIo_Out32(OutAddr, (u32)tmp_v); \
-    }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer()					\
-	{						\
-      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
-	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
-	  Addr += (u32)XTC_TCSR_OFFSET; \
-      u32 tmp_v = (u32)ProfIo_In32(Addr); \
-      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
-      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
-	}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack()				\
-	{						\
-		u32 csr;			\
-		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
-		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
-	}
-
-/*-------------------------------------------------------------------- */
-#endif	/* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer()							\
-{								\
-	u32 Reg;							\
-	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
-	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
-	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer()							\
-{								\
-	u32 Reg;							\
-	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
-	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
-	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack()						\
-{							\
-	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
-		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif	/* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

df_datalink/bsp/ps7_cortexa9_0/include/bspconfig.h

@@ -1,44 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2019.1.3
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-* 
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-* 
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H  /* prevent circular inclusions */
-#define BSPCONFIG_H  /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-/* Definition for hard-float ABI */
-#define FPU_HARD_FLOAT_ABI_ENABLED 1
-
-#endif /*end of __BSPCONFIG_H_*/

df_datalink/bsp/ps7_cortexa9_0/include/mblaze_nt_types.h

@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char            byte;
-typedef short           half;
-typedef int             word;
-typedef unsigned char   ubyte;
-typedef unsigned short  uhalf;
-typedef unsigned int    uword;
-typedef ubyte           boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

df_datalink/bsp/ps7_cortexa9_0/include/profile.h

@@ -1,127 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef	PROFILE_H
-#define	PROFILE_H	1
-
-#include <stdio.h>
-#include "xil_types.h"
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(u32 frompc, u32 selfpc);
-void profile_intr_handler( void ) ;
-void _profile_init( void );
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define	HISTCOUNTER	u16
-
-struct tostruct {
-	u32  selfpc;
-	s32	 count;
-	s16  link;
-	u16	 pad;
-};
-
-struct fromstruct {
-	u32 frompc ;
-	s16 link ;
-	u16 pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
-#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
-	s32		state;
-
-	/* Histogram Information */
-	u16		*kcount;	/* No. of bins in histogram */
-	u32		kcountsize;	/* Histogram samples */
-
-	/* Call-graph Information */
-	struct fromstruct	*froms;
-	u32		fromssize;
-	struct tostruct		*tos;
-	u32		tossize;
-
-	/* Initialization I/Ps */
-	u32    	lowpc;
-	u32		highpc;
-	u32		textsize;
-	/* u32 		cg_froms, */
-	/* u32 		cg_tos, */
-};
-extern struct gmonparam *_gmonparam;
-extern s32 n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define	GMON_PROF_ON	0
-#define	GMON_PROF_BUSY	1
-#define	GMON_PROF_ERROR	2
-#define	GMON_PROF_OFF	3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define	GPROF_STATE	0	/* int: profiling enabling variable */
-#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
-#define	GPROF_FROMS	2	/* struct: from location hash bucket */
-#define	GPROF_TOS	3	/* struct: destination/count structure */
-#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif 		/* PROFILE_H */

df_datalink/bsp/ps7_cortexa9_0/include/sleep.h

@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-*  This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-*  related APIs.
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6   srm  11/02/17 Added processor specific sleep rountines
-*								 function prototypes.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param            IO_func - accessor function to read the register contents.
-*                   Depends on the register width.
-* @param            ADDR - Address to be polled
-* @param            VALUE - variable to read the value
-* @param            COND - Condition to checked (usually involves VALUE)
-* @param            TIMEOUT_US - timeout in micro seconds
-*
-* @return           0 - when the condition is met
-*                   -1 - when the condition is not met till the timeout period
-*
-* @note             none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( {	  \
-	u64 timeout = TIMEOUT_US/100;    \
-	if(TIMEOUT_US%100!=0)	\
-		timeout++;   \
-	for(;;) { \
-		VALUE = IO_func(ADDR); \
-		if(COND) \
-			break; \
-		else {    \
-			usleep(100);  \
-			timeout--; \
-			if(timeout==0) \
-			break;  \
-		}  \
-	}    \
-	(timeout>0) ? 0 : -1;  \
- }  )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

df_datalink/bsp/ps7_cortexa9_0/include/smc.h

@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm  11/03/09 Initial release.
-* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-*					  as smc.c is removed
-* </pre>
-*
-* @note		None.
-*
-******************************************************************************/
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS		0x000U	/* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG	0x004U	/* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG		0x008U	/* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG		0x00CU	/* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD		0x010U	/* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES		0x014U	/* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE		0x018U	/* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020U	/* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024U	/* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100U	/* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120U	/* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140U	/* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160U	/* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180U	/* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0U	/* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0U	/* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0U	/* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET	0x200U	/* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET	0x204U	/* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET		0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET	0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */

df_datalink/bsp/ps7_cortexa9_0/include/vectors.h

@@ -1,84 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
-* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-#if !defined (__aarch64__)
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-void UndefinedException(void);
-#else
-void SynchronousInterrupt(void);
-void SErrorInterrupt(void);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xadcps.h

@@ -1,589 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps.h
-* @addtogroup xadcps_v2_3
-* @{
-* @details
-*
-* The XAdcPs driver supports the Xilinx XADC/ADC device.
-*
-* The XADC/ADC device has the following features:
-*	- 10-bit, 200-KSPS (kilo samples per second)
-*		Analog-to-Digital Converter (ADC)
-*	- Monitoring of on-chip supply voltages and temperature
-*	- 1 dedicated differential analog-input pair and
-*	  16 auxiliary differential analog-input pairs
-*	- Automatic alarms based on user defined limits for the on-chip
-*	  supply voltages and temperature
-*	- Automatic Channel Sequencer, programmable averaging, programmable
-*	  acquisition time for the external inputs, unipolar or differential
-*	  input selection for the external inputs
-*	- Inbuilt Calibration
-*	- Optional interrupt request generation
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the XADC/ADC device.
-*
-*
-* <b> XADC Channel Sequencer Modes </b>
-*
-* The  XADC Channel Sequencer supports the following operating modes:
-*
-*   - <b> Default </b>: This is the default mode after power up.
-*		In this mode of operation the XADC operates in
-*		a sequence mode, monitoring the on chip sensors:
-*		Temperature, VCCINT, and VCCAUX.
-*   - <b> One pass through sequence </b>: In this mode the XADC
-*		converts the channels enabled in the Sequencer Channel Enable
-*		registers for a single pass and then stops.
-*   - <b> Continuous cycling of sequence </b>: In this mode the XADC
-*		converts the channels enabled in the Sequencer Channel Enable
-*		registers continuously.
-*   - <b> Single channel mode</b>: In this mode the XADC Channel
-*		Sequencer is disabled and the XADC operates in a
-*		Single Channel Mode.
-*		The XADC can operate either in a Continuous or Event
-*		driven sampling mode in the single channel mode.
-*   - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
-*		Sequencer will automatically sequence through eight fixed pairs
-*		of auxiliary analog input channels for simulataneous conversion.
-*   - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
-*		is used to implement a fixed monitoring mode similar to the
-*		default mode but the alarm fucntions ar eenabled.
-*		The second ADC (B) is available to be used with external analog
-*		input channels only.
-*
-* Read the XADC spec for more information about the sequencer modes.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the XADC/ADC device.
-*
-* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
-* device. The user needs to first call the XAdcPs_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAdcPs_CfgInitialize() API.
-*
-*
-* <b>Interrupts</b>
-*
-* The XADC/ADC device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* The interrupt mode is available only if hardware is configured to support
-* interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* <b> Building the driver </b>
-*
-* The XAdcPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <b> Limitations of the driver </b>
-*
-* XADC/ADC device can be accessed through the JTAG port and the PLB
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to care of this situation
-* in the user application code.
-*
-* <br><br>
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-*			in xadcps.c to fix CR #693371
-* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
-*			CR#749687
-* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-*			functions.
-*			Modified Assert for XAdcPs_SetSingleChParams in
-*			xadcps.c to fix CR #807563.
-* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
-*						xadcps.c (CR#854437).
-*       ms     01/23/17 Added xil_printf statement in main function for all
-*                       examples to ensure that "Successfully ran" and "Failed"
-*                       strings are available in all examples. This is a fix
-*                       for CR-965028.
-*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
-*                       generation.
-*       ms     04/05/17 Modified Comment lines in functions of xadcps
-*                       examples to recognize it as documentation block
-*                       for doxygen generation.
-* 2.3   mn     07/09/18 Fix Doxygen warning
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros  */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
-#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
-#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP		0x4  /**< VREFP */
-#define XADCPS_CH_VREFN		0x5  /**< VREFN */
-#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
-#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
-#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
-#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
-	u16  DeviceId;		/**< Unique ID of device */
-	u32  BaseAddress;	/**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
-	u32  IsReady;		/**< Device is initialized and ready  */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param	InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-*		- TRUE if the device is in Event Sampling Mode.
-*		- FALSE if the device is in Continuous Sampling Mode.
-*
-* @note		C-Style signature:
-*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
-	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
-			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
-			TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param	InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-*		- TRUE if the device is in External Mux Mode.
-*		- FALSE if the device is NOT in External Mux Mode.
-*
-* @note		C-Style signature:
-*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
-	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
-			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
-			TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param	AdcData is the Raw ADC Data from XADC.
-*
-* @return 	The Temperature in centigrades.
-*
-* @note		C-Style signature:
-*		float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData)				\
-	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param	AdcData is the XADC/ADC Raw Data.
-*
-* @return 	The Voltage in volts.
-*
-* @note		C-Style signature:
-*		float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) 					\
-	((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param	Temperature is the Temperature in centigrades to be
-*		converted to XADC/ADC Raw Data.
-*
-* @return 	The XADC/ADC Raw Data.
-*
-* @note		C-Style signature:
-*		int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature)				\
-	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param	Voltage is the Voltage in volts to be converted to
-*		XADC/ADC Raw Data.
-*
-* @return 	The XADC/ADC Raw Data.
-*
-* @note		C-Style signature:
-*		int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage)			 		\
-	((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param	InstancePtr is a pointer to the XAdcPs instance.
-* @param	Data is the value to be written to XADC register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data)				\
-	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
-			  XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param	InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return	Data read from the FIFO
-*
-* @note		C-Style signature:
-*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr)				\
-	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
-			  XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
-				XAdcPs_Config *ConfigPtr,
-				u32 EffectiveAddr);
-
-
-u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
-				u8 Channel,
-				int IncreaseAcqCycles,
-				int IsEventMode,
-				int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* End of protection macro. */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xadcps_hw.h

@@ -1,498 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_3
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note	 None.
-*
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- -----  -------- -----------------------------------------------------
-* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
-*			CR#749687
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros  */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
-  * @{
- */
-#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
-						* successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
-  *
-  * The definitions are same for the Interrupt Status Register and
-  * Interrupt Mask Register. They are defined only once.
-  * @{
- */
-#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
-#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
-#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
-#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
-#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
-#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
-#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
-#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
-  * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
-#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
-#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
-#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
-#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
-#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
-  * @{
- */
-#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
-#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
-#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
-						 *  Continuous mode selection
-						 */
-#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
-							Supply Gain/Offset
-							Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
-							Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
-							Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
-							Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**<Clock Divisor bit Mask   */
-#define XADCPS_CFR2_CD_SHIFT		8	/**<Num of shift on division */
-#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
-#define XADCPS_CFR2_CD_MAX		255	/**<Maximum value of divisor */
-
-#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
-#define XADCPS_CFR2_PD_MASK		0x0030	/**<Power Down Mask */
-#define XADCPS_CFR2_PD_XADC_MASK	0x0030	/**<Power Down XADC Mask */
-#define XADCPS_CFR2_PD_ADC1_MASK	0x0020	/**<Power Down ADC1 Mask */
-#define XADCPS_CFR2_PD_SHIFT		4	/**<Power Down Shift */
-/*@}*/
-
-/**
- * @name Sequence Register (SEQ) Bit Definitions
- * @{
- */
-#define XADCPS_SEQ_CH_CALIB	0x00000001 /**< ADC Calibration Channel */
-#define XADCPS_SEQ_CH_VCCPINT	0x00000020 /**< VCCPINT, Zynq Only */
-#define XADCPS_SEQ_CH_VCCPAUX	0x00000040 /**< VCCPAUX, Zynq Only */
-#define XADCPS_SEQ_CH_VCCPDRO	0x00000080 /**< VCCPDRO, Zynq Only */
-#define XADCPS_SEQ_CH_TEMP	0x00000100 /**< On Chip Temperature Channel */
-#define XADCPS_SEQ_CH_VCCINT	0x00000200 /**< VCCINT Channel */
-#define XADCPS_SEQ_CH_VCCAUX	0x00000400 /**< VCCAUX Channel */
-#define XADCPS_SEQ_CH_VPVN	0x00000800 /**< VP/VN analog inputs Channel */
-#define XADCPS_SEQ_CH_VREFP	0x00001000 /**< VREFP Channel */
-#define XADCPS_SEQ_CH_VREFN	0x00002000 /**< VREFN Channel */
-#define XADCPS_SEQ_CH_VBRAM	0x00004000 /**< VBRAM Channel, 7 series */
-#define XADCPS_SEQ_CH_AUX00	0x00010000 /**< 1st Aux Channel */
-#define XADCPS_SEQ_CH_AUX01	0x00020000 /**< 2nd Aux Channel */
-#define XADCPS_SEQ_CH_AUX02	0x00040000 /**< 3rd Aux Channel */
-#define XADCPS_SEQ_CH_AUX03	0x00080000 /**< 4th Aux Channel */
-#define XADCPS_SEQ_CH_AUX04	0x00100000 /**< 5th Aux Channel */
-#define XADCPS_SEQ_CH_AUX05	0x00200000 /**< 6th Aux Channel */
-#define XADCPS_SEQ_CH_AUX06	0x00400000 /**< 7th Aux Channel */
-#define XADCPS_SEQ_CH_AUX07	0x00800000 /**< 8th Aux Channel */
-#define XADCPS_SEQ_CH_AUX08	0x01000000 /**< 9th Aux Channel */
-#define XADCPS_SEQ_CH_AUX09	0x02000000 /**< 10th Aux Channel */
-#define XADCPS_SEQ_CH_AUX10	0x04000000 /**< 11th Aux Channel */
-#define XADCPS_SEQ_CH_AUX11	0x08000000 /**< 12th Aux Channel */
-#define XADCPS_SEQ_CH_AUX12	0x10000000 /**< 13th Aux Channel */
-#define XADCPS_SEQ_CH_AUX13	0x20000000 /**< 14th Aux Channel */
-#define XADCPS_SEQ_CH_AUX14	0x40000000 /**< 15th Aux Channel */
-#define XADCPS_SEQ_CH_AUX15	0x80000000 /**< 16th Aux Channel */
-
-#define XADCPS_SEQ00_CH_VALID_MASK  0x7FE1 /**< Mask for the valid channels */
-#define XADCPS_SEQ01_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ02_CH_VALID_MASK  0x7FE0 /**< Mask for the valid channels */
-#define XADCPS_SEQ03_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ04_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
-#define XADCPS_SEQ05_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ06_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
-#define XADCPS_SEQ07_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
-
-
-#define XADCPS_SEQ_CH_AUX_SHIFT	16 /**< Shift for the Aux Channel */
-
-/*@}*/
-
-/**
- * @name OT Upper Alarm Threshold Register Bit Definitions
- * @{
- */
-
-#define XADCPS_ATR_OT_UPPER_ENB_MASK	0x000F /**< Mask for OT enable */
-#define XADCPS_ATR_OT_UPPER_VAL_MASK	0xFFF0 /**< Mask for OT value */
-#define XADCPS_ATR_OT_UPPER_VAL_SHIFT	4      /**< Shift for OT value */
-#define XADCPS_ATR_OT_UPPER_ENB_VAL	0x0003 /**< Value for OT enable */
-#define XADCPS_ATR_OT_UPPER_VAL_MAX	0x0FFF /**< Max OT value */
-
-/*@}*/
-
-
-/**
- * @name JTAG DRP Bit Definitions
- * @{
- */
-#define XADCPS_JTAG_DATA_MASK		0x0000FFFF /**< Mask for the Data */
-#define XADCPS_JTAG_ADDR_MASK		0x03FF0000 /**< Mask for the Addr */
-#define XADCPS_JTAG_ADDR_SHIFT		16	   /**< Shift for the Addr */
-#define XADCPS_JTAG_CMD_MASK		0x3C000000 /**< Mask for the Cmd */
-#define XADCPS_JTAG_CMD_WRITE_MASK	0x08000000 /**< Mask for CMD Write */
-#define XADCPS_JTAG_CMD_READ_MASK	0x04000000 /**< Mask for CMD Read */
-#define XADCPS_JTAG_CMD_SHIFT		26	   /**< Shift for the Cmd */
-
-/*@}*/
-
-/** @name Unlock Register Definitions
-  * @{
- */
- #define XADCPS_UNLK_OFFSET	 0x034 /**< Unlock Register */
- #define XADCPS_UNLK_VALUE	 0x757BDF0D /**< Unlock Value */
-
- /* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-*
-* Read a register of the XADC device. This macro provides register
-* access to all registers using the register offsets defined above.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset is the offset of the register to read.
-*
-* @return	The contents of the register.
-*
-* @note		C-style Signature:
-*		u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
-*
-******************************************************************************/
-#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
-			(Xil_In32((BaseAddress) + (RegOffset)))
-
-/*****************************************************************************/
-/**
-*
-* Write a register of the XADC device. This macro provides
-* register access to all registers using the register offsets defined above.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset is the offset of the register to write.
-* @param	Data is the value to write to the register.
-*
-* @return	None.
-*
-* @note 	C-style Signature:
-*		void XAdcPs_WriteReg(u32 BaseAddress,
-*					u32 RegOffset,u32 Data)
-*
-******************************************************************************/
-#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
-		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Formats the data to be written to the the XADC registers.
-*
-* @param	RegOffset is the offset of the Register
-* @param	Data is the data to be written to the Register if it is
-*		a write.
-* @param	ReadWrite specifies whether it is a Read or a Write.
-*		Use 0 for Read, 1 for Write.
-*
-* @return	None.
-*
-* @note 	C-style Signature:
-*		void XAdcPs_FormatWriteData(u32 RegOffset,
-*					     u16 Data, int ReadWrite)
-*
-******************************************************************************/
-#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) 	    \
-    ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
-     ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | 	     \
-     (Data & XADCPS_JTAG_DATA_MASK))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* End of protection macro. */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xbasic_types.h

@@ -1,127 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note  Dummy File for backwards compatibility
-*
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
-* 7.0   aru   01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 	aru   02/06/19 Included stdint.h and stddef.h
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
-#define XBASIC_TYPES_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stddef.h>
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t	Xuint8;		/**< unsigned 8-bit */
-typedef char		Xint8;		/**< signed 8-bit */
-typedef uint16_t	Xuint16;	/**< unsigned 16-bit */
-typedef short		Xint16;		/**< signed 16-bit */
-typedef uint32_t	Xuint32;	/**< unsigned 32-bit */
-typedef long		Xint32;		/**< signed 32-bit */
-typedef float		Xfloat32;	/**< 32-bit floating point */
-typedef double		Xfloat64;	/**< 64-bit double precision FP */
-typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
-	Xuint32 Upper;
-	Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32         u32;
-typedef Xuint16         u16;
-typedef Xuint8          u8;
-#endif
-#else
-#include <linux/types.h>
-#endif
-
-#ifndef TRUE
-#  define TRUE		1U
-#endif
-
-#ifndef FALSE
-#  define FALSE		0U
-#endif
-
-#ifndef NULL
-#define NULL		0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL		NULL
-#define XTRUE		TRUE
-#define XFALSE		FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning  Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xbram.h

@@ -1,223 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xbram.h
-* @addtogroup bram_v4_2
-* @{
-* @details
-*
-* If ECC is not enabled, this driver exists only to allow the tools to
-* create a memory test application and to populate xparameters.h with memory
-* range constants. In this case there is no source code.
-*
-* If ECC is enabled, this file contains the software API definition of the
-* Xilinx BRAM Interface Controller (XBram) device driver.
-*
-* The Xilinx BRAM controller is a soft IP core designed for Xilinx
-* FPGAs and contains the following general features:
-*   - LMB v2.0 bus interfaces with byte enable support
-*   - Used in conjunction with bram_block peripheral to provide fast BRAM
-*     memory solution for MicroBlaze ILMB and DLMB ports
-*   - Supports byte, half-word, and word transfers
-*   - Supports optional BRAM error correction and detection.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XBram_Config structure is used by the driver to configure
-* itself. This configuration structure is typically created by the tool-chain
-* based on HW build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized as
-* follows:
-*
-*   - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
-*     Uses a configuration structure provided by the caller. If running in a
-*     system with address translation, the provided virtual memory base address
-*     replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the BRAM registers. With less
-* than 32 bits, the unused bits from registers are read as zero and written as
-* don't cares.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 3.00a sa  05/11/10 Added ECC support
-* 3.01a sa  01/13/12  Changed Selftest API from
-*		      XBram_SelfTest(XBram *InstancePtr) to
-*		      XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
-*		      fixed a problem with interrupt generation for CR 639274
-*		      Modified Selftest example to return XST_SUCCESS when
-*		      ECC is not enabled and return XST_FAILURE when ECC is
-*		      enabled and Control Base Address is zero (CR 636581)
-*		      Modified Selftest to use correct CorrectableCounterBits
-*		      for CR 635655
-*		      Updated to check CorrectableFailingDataRegs in the case
-*		      of LMB BRAM.
-* 		      Added CorrectableFailingDataRegs and
-*		      UncorrectableFailingDataRegs to the config structure to
-*		      distinguish between AXI BRAM and LMB BRAM.
-*		      These registers are not present in the current version of
-*		      the AXI BRAM Controller.
-* 3.02a sa 04/16/12   Added test of byte and halfword read-modify-write
-* 3.02a sa 04/16/12   Modified driver tcl to sort the address parameters
-*  	       	      to support both xps and vivado designs.
-* 3.02a adk 24/4/13   Modified the tcl file to avoid warnings
-*	       	      when ecc is disabled cr:705002.
-* 3.03a bss 05/22/13  Added Xil_DCacheFlushRange in xbram_selftest.c to
-*		      flush the Cache after writing to BRAM in InjectErrors
-*		      API(CR #719011)
-* 4.0   adk  19/12/13 Updated as per the New Tcl API's
-* 4.1   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
-*                     Changed the prototype of XBram_CfgInitialize API.
-*       ms  01/23/17 Modified xil_printf statement in main function for all
-*                    examples to ensure that "Successfully ran" and "Failed"
-*                    strings are available in all examples. This is a fix
-*                    for CR-965028.
-*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
-*                    generation.
-* 4.2   ms  04/18/17 Modified tcl file to add suffix U for all macro
-*                    definitions of bram in xparameters.h
-*       ms  08/07/17 Fixed compilation warnings in xbram_sinit.c
-* 4.3   aru 03/23/19 Used UINTPTR instead of u32 for MemBaseAddress and
-*                    MemHighAddress.
-* </pre>
-*****************************************************************************/
-#ifndef XBRAM_H		/* prevent circular inclusions */
-#define XBRAM_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xbram_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;			   /**< Unique ID  of device */
-	u32 DataWidth;			   /**< BRAM data width */
-	int EccPresent;			   /**< Is ECC supported in H/W */
-	int FaultInjectionPresent;	   /**< Is Fault Injection
-					     *  supported in H/W */
-	int CorrectableFailingRegisters;   /**< Is Correctable Failing Registers
-					     *  supported in H/W */
-	int CorrectableFailingDataRegs;    /**< Is Correctable Failing Data
-					    *   Registers supported in H/W */
-	int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
-					     *  Registers supported in H/W */
-	int UncorrectableFailingDataRegs;  /**< Is Un-correctable Failing Data
-					     *  Registers supported in H/W */
-	int EccStatusInterruptPresent;	   /**< Are ECC status and interrupts
-					     *  supported in H/W */
-	int CorrectableCounterBits;	   /**< Number of bits in the
-					     *  Correctable Error Counter */
-	int EccOnOffRegister;		   /**< Is ECC on/off register supported
-					     *  in h/w */
-	int EccOnOffResetValue;		   /**< Reset value of the ECC on/off
-					     *  register in h/w */
-	int WriteAccess;		   /**< Is write access enabled in
-					     *  h/w */
-	UINTPTR MemBaseAddress;		   /**< Device memory base address */
-	UINTPTR MemHighAddress;		   /**< Device memory high address */
-	UINTPTR CtrlBaseAddress;		   /**< Device register base address.*/
-	UINTPTR CtrlHighAddress;		   /**< Device register base address.*/
-} XBram_Config;
-
-/**
- * The XBram driver instance data. The user is required to
- * allocate a variable of this type for every BRAM device in the
- * system. A pointer to a variable of this type is then passed to the driver
- * API functions.
- */
-typedef struct {
-	XBram_Config  Config;		/* BRAM config structure */
-	u32 IsReady;			/* Device is initialized and ready */
-} XBram;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Functions in xbram_sinit.c
- */
-XBram_Config *XBram_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xbram.c
- */
-int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
-			UINTPTR EffectiveAddr);
-
-/*
- * Functions implemented in xbram_selftest.c
- */
-int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
-
-/*
- * Functions implemented in xbram_intr.c
- */
-void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
-void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
-void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
-u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
-u32 XBram_InterruptGetStatus(XBram *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xbram_hw.h

@@ -1,405 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbram_hw.h
-* @addtogroup bram_v4_2
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device.  The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sa   24/11/10 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XBRAM_HW_H		/* prevent circular inclusions */
-#define XBRAM_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-
-#define XBRAM_ECC_STATUS_OFFSET	0x0  /**< ECC status Register */
-#define XBRAM_ECC_EN_IRQ_OFFSET	0x4  /**< ECC interrupt enable Register */
-#define XBRAM_ECC_ON_OFF_OFFSET	0x8  /**< ECC on/off register */
-#define XBRAM_CE_CNT_OFFSET	0xC  /**< Correctable error counter Register */
-
-#define XBRAM_CE_FFD_0_OFFSET	0x100 /**< Correctable error first failing
-				        *  data Register, 31-0 */
-#define XBRAM_CE_FFD_1_OFFSET	0x104 /**< Correctable error first failing
-				        *  data Register, 63-32 */
-#define XBRAM_CE_FFD_2_OFFSET	0x108 /**< Correctable error first failing
-				        *  data Register, 95-64 */
-#define XBRAM_CE_FFD_3_OFFSET	0x10C /**< Correctable error first failing
-				        *  data Register, 127-96 */
-#define XBRAM_CE_FFD_4_OFFSET	0x110 /**< Correctable error first failing
-				        *  data Register, 159-128 */
-#define XBRAM_CE_FFD_5_OFFSET	0x114 /**< Correctable error first failing
-				        *  data Register, 191-160 */
-#define XBRAM_CE_FFD_6_OFFSET	0x118 /**< Correctable error first failing
-				        *  data Register, 223-192 */
-#define XBRAM_CE_FFD_7_OFFSET	0x11C /**< Correctable error first failing
-				        *  data Register, 255-224 */
-#define XBRAM_CE_FFD_8_OFFSET	0x120 /**< Correctable error first failing
-				        *  data Register, 287-256 */
-#define XBRAM_CE_FFD_9_OFFSET	0x124 /**< Correctable error first failing
-				        *  data Register, 319-288 */
-#define XBRAM_CE_FFD_10_OFFSET	0x128 /**< Correctable error first failing
-				        *  data Register, 351-320 */
-#define XBRAM_CE_FFD_11_OFFSET	0x12C /**< Correctable error first failing
-				        *  data Register, 383-352 */
-#define XBRAM_CE_FFD_12_OFFSET	0x130 /**< Correctable error first failing
-				        *  data Register, 415-384 */
-#define XBRAM_CE_FFD_13_OFFSET	0x134 /**< Correctable error first failing
-				        *  data Register, 447-416 */
-#define XBRAM_CE_FFD_14_OFFSET	0x138 /**< Correctable error first failing
-				        *  data Register, 479-448 */
-#define XBRAM_CE_FFD_15_OFFSET	0x13C /**< Correctable error first failing
-				        *  data Register, 511-480 */
-#define XBRAM_CE_FFD_16_OFFSET	0x140 /**< Correctable error first failing
-				        *  data Register, 543-512 */
-#define XBRAM_CE_FFD_17_OFFSET	0x144 /**< Correctable error first failing
-				        *  data Register, 575-544 */
-#define XBRAM_CE_FFD_18_OFFSET	0x148 /**< Correctable error first failing
-				        *  data Register, 607-576 */
-#define XBRAM_CE_FFD_19_OFFSET	0x14C /**< Correctable error first failing
-				        *  data Register, 639-608 */
-#define XBRAM_CE_FFD_20_OFFSET	0x150 /**< Correctable error first failing
-				        *  data Register, 671-640 */
-#define XBRAM_CE_FFD_21_OFFSET	0x154 /**< Correctable error first failing
-				        *  data Register, 703-672 */
-#define XBRAM_CE_FFD_22_OFFSET	0x158 /**< Correctable error first failing
-				        *  data Register, 735-704 */
-#define XBRAM_CE_FFD_23_OFFSET	0x15C /**< Correctable error first failing
-				        *  data Register, 767-736 */
-#define XBRAM_CE_FFD_24_OFFSET	0x160 /**< Correctable error first failing
-				        *  data Register, 799-768 */
-#define XBRAM_CE_FFD_25_OFFSET	0x164 /**< Correctable error first failing
-				        *  data Register, 831-800 */
-#define XBRAM_CE_FFD_26_OFFSET	0x168 /**< Correctable error first failing
-				        *  data Register, 863-832 */
-#define XBRAM_CE_FFD_27_OFFSET	0x16C /**< Correctable error first failing
-				        *  data Register, 895-864 */
-#define XBRAM_CE_FFD_28_OFFSET	0x170 /**< Correctable error first failing
-				        *  data Register, 927-896 */
-#define XBRAM_CE_FFD_29_OFFSET	0x174 /**< Correctable error first failing
-				        *  data Register, 959-928 */
-#define XBRAM_CE_FFD_30_OFFSET	0x178 /**< Correctable error first failing
-				        *  data Register, 991-960 */
-#define XBRAM_CE_FFD_31_OFFSET	0x17C /**< Correctable error first failing
-				        *  data Register, 1023-992 */
-
-#define XBRAM_CE_FFE_0_OFFSET	0x180 /**< Correctable error first failing
-				        *  ECC Register, 31-0 */
-#define XBRAM_CE_FFE_1_OFFSET	0x184 /**< Correctable error first failing
-				        *  ECC Register, 63-32 */
-#define XBRAM_CE_FFE_2_OFFSET	0x188 /**< Correctable error first failing
-				        *  ECC Register, 95-64 */
-#define XBRAM_CE_FFE_3_OFFSET	0x18C /**< Correctable error first failing
-				        *  ECC Register, 127-96 */
-#define XBRAM_CE_FFE_4_OFFSET	0x190 /**< Correctable error first failing
-				        *  ECC Register, 159-128 */
-#define XBRAM_CE_FFE_5_OFFSET	0x194 /**< Correctable error first failing
-				        *  ECC Register, 191-160 */
-#define XBRAM_CE_FFE_6_OFFSET	0x198 /**< Correctable error first failing
-				        *  ECC Register, 223-192 */
-#define XBRAM_CE_FFE_7_OFFSET	0x19C /**< Correctable error first failing
-				        *  ECC Register, 255-224 */
-
-#define XBRAM_CE_FFA_0_OFFSET	0x1C0 /**< Correctable error first failing
-				        *  address Register 31-0 */
-#define XBRAM_CE_FFA_1_OFFSET	0x1C4 /**< Correctable error first failing
-				        *  address Register 63-32 */
-
-#define XBRAM_UE_FFD_0_OFFSET	0x200 /**< Uncorrectable error first failing
-				        *  data Register, 31-0 */
-#define XBRAM_UE_FFD_1_OFFSET	0x204 /**< Uncorrectable error first failing
-				        *  data Register, 63-32 */
-#define XBRAM_UE_FFD_2_OFFSET	0x208 /**< Uncorrectable error first failing
-				        *  data Register, 95-64 */
-#define XBRAM_UE_FFD_3_OFFSET	0x20C /**< Uncorrectable error first failing
-				        *  data Register, 127-96 */
-#define XBRAM_UE_FFD_4_OFFSET	0x210 /**< Uncorrectable error first failing
-				        *  data Register, 159-128 */
-#define XBRAM_UE_FFD_5_OFFSET	0x214 /**< Uncorrectable error first failing
-				        *  data Register, 191-160 */
-#define XBRAM_UE_FFD_6_OFFSET	0x218 /**< Uncorrectable error first failing
-				        *  data Register, 223-192 */
-#define XBRAM_UE_FFD_7_OFFSET	0x21C /**< Uncorrectable error first failing
-				        *  data Register, 255-224 */
-#define XBRAM_UE_FFD_8_OFFSET	0x220 /**< Uncorrectable error first failing
-				        *  data Register, 287-256 */
-#define XBRAM_UE_FFD_9_OFFSET	0x224 /**< Uncorrectable error first failing
-				        *  data Register, 319-288 */
-#define XBRAM_UE_FFD_10_OFFSET	0x228 /**< Uncorrectable error first failing
-				        *  data Register, 351-320 */
-#define XBRAM_UE_FFD_11_OFFSET	0x22C /**< Uncorrectable error first failing
-				        *  data Register, 383-352 */
-#define XBRAM_UE_FFD_12_OFFSET	0x230 /**< Uncorrectable error first failing
-				        *  data Register, 415-384 */
-#define XBRAM_UE_FFD_13_OFFSET	0x234 /**< Uncorrectable error first failing
-				        *  data Register, 447-416 */
-#define XBRAM_UE_FFD_14_OFFSET	0x238 /**< Uncorrectable error first failing
-				        *  data Register, 479-448 */
-#define XBRAM_UE_FFD_15_OFFSET	0x23C /**< Uncorrectable error first failing
-				        *  data Register, 511-480 */
-#define XBRAM_UE_FFD_16_OFFSET	0x240 /**< Uncorrectable error first failing
-				        *  data Register, 543-512 */
-#define XBRAM_UE_FFD_17_OFFSET	0x244 /**< Uncorrectable error first failing
-				        *  data Register, 575-544 */
-#define XBRAM_UE_FFD_18_OFFSET	0x248 /**< Uncorrectable error first failing
-				        *  data Register, 607-576 */
-#define XBRAM_UE_FFD_19_OFFSET	0x24C /**< Uncorrectable error first failing
-				        *  data Register, 639-608 */
-#define XBRAM_UE_FFD_20_OFFSET	0x250 /**< Uncorrectable error first failing
-				        *  data Register, 671-640 */
-#define XBRAM_UE_FFD_21_OFFSET	0x254 /**< Uncorrectable error first failing
-				        *  data Register, 703-672 */
-#define XBRAM_UE_FFD_22_OFFSET	0x258 /**< Uncorrectable error first failing
-				        *  data Register, 735-704 */
-#define XBRAM_UE_FFD_23_OFFSET	0x25C /**< Uncorrectable error first failing
-				        *  data Register, 767-736 */
-#define XBRAM_UE_FFD_24_OFFSET	0x260 /**< Uncorrectable error first failing
-				        *  data Register, 799-768 */
-#define XBRAM_UE_FFD_25_OFFSET	0x264 /**< Uncorrectable error first failing
-				        *  data Register, 831-800 */
-#define XBRAM_UE_FFD_26_OFFSET	0x268 /**< Uncorrectable error first failing
-				        *  data Register, 863-832 */
-#define XBRAM_UE_FFD_27_OFFSET	0x26C /**< Uncorrectable error first failing
-				        *  data Register, 895-864 */
-#define XBRAM_UE_FFD_28_OFFSET	0x270 /**< Uncorrectable error first failing
-				        *  data Register, 927-896 */
-#define XBRAM_UE_FFD_29_OFFSET	0x274 /**< Uncorrectable error first failing
-				        *  data Register, 959-928 */
-#define XBRAM_UE_FFD_30_OFFSET	0x278 /**< Uncorrectable error first failing
-				        *  data Register, 991-960 */
-#define XBRAM_UE_FFD_31_OFFSET	0x27C /**< Uncorrectable error first failing
-				        *  data Register, 1023-992 */
-
-#define XBRAM_UE_FFE_0_OFFSET	0x280 /**< Uncorrectable error first failing
-				        *  ECC Register, 31-0 */
-#define XBRAM_UE_FFE_1_OFFSET	0x284 /**< Uncorrectable error first failing
-				        *  ECC Register, 63-32 */
-#define XBRAM_UE_FFE_2_OFFSET	0x288 /**< Uncorrectable error first failing
-				        *  ECC Register, 95-64 */
-#define XBRAM_UE_FFE_3_OFFSET	0x28C /**< Uncorrectable error first failing
-				        *  ECC Register, 127-96 */
-#define XBRAM_UE_FFE_4_OFFSET	0x290 /**< Uncorrectable error first failing
-				        *  ECC Register, 159-128 */
-#define XBRAM_UE_FFE_5_OFFSET	0x294 /**< Uncorrectable error first failing
-				        *  ECC Register, 191-160 */
-#define XBRAM_UE_FFE_6_OFFSET	0x298 /**< Uncorrectable error first failing
-				        *  ECC Register, 223-192 */
-#define XBRAM_UE_FFE_7_OFFSET	0x29C /**< Uncorrectable error first failing
-				        *  ECC Register, 255-224 */
-
-#define XBRAM_UE_FFA_0_OFFSET	0x2C0 /**< Uncorrectable error first failing
-				        *  address Register 31-0 */
-#define XBRAM_UE_FFA_1_OFFSET	0x2C4 /**< Uncorrectable error first failing
-				        *  address Register 63-32 */
-
-#define XBRAM_FI_D_0_OFFSET	0x300 /**< Fault injection Data Register,
-				        *  31-0 */
-#define XBRAM_FI_D_1_OFFSET	0x304 /**< Fault injection Data Register,
-				        *  63-32 */
-#define XBRAM_FI_D_2_OFFSET	0x308 /**< Fault injection Data Register,
-				        *  95-64 */
-#define XBRAM_FI_D_3_OFFSET	0x30C /**< Fault injection Data Register,
-				        *  127-96 */
-#define XBRAM_FI_D_4_OFFSET	0x310 /**< Fault injection Data Register,
-				        *  159-128 */
-#define XBRAM_FI_D_5_OFFSET	0x314 /**< Fault injection Data Register,
-				        *  191-160 */
-#define XBRAM_FI_D_6_OFFSET	0x318 /**< Fault injection Data Register,
-				        *  223-192 */
-#define XBRAM_FI_D_7_OFFSET	0x31C /**< Fault injection Data Register,
-				        *  255-224 */
-#define XBRAM_FI_D_8_OFFSET	0x320 /**< Fault injection Data Register,
-				        *  287-256 */
-#define XBRAM_FI_D_9_OFFSET	0x324 /**< Fault injection Data Register,
-				        *  319-288 */
-#define XBRAM_FI_D_10_OFFSET	0x328 /**< Fault injection Data Register,
-				        *  351-320 */
-#define XBRAM_FI_D_11_OFFSET	0x32C /**< Fault injection Data Register,
-				        *  383-352 */
-#define XBRAM_FI_D_12_OFFSET	0x330 /**< Fault injection Data Register,
-				        *  415-384 */
-#define XBRAM_FI_D_13_OFFSET	0x334 /**< Fault injection Data Register,
-				        *  447-416 */
-#define XBRAM_FI_D_14_OFFSET	0x338 /**< Fault injection Data Register,
-				        *  479-448 */
-#define XBRAM_FI_D_15_OFFSET	0x33C /**< Fault injection Data Register,
-				        *  511-480 */
-#define XBRAM_FI_D_16_OFFSET	0x340 /**< Fault injection Data Register,
-				        *  543-512 */
-#define XBRAM_FI_D_17_OFFSET	0x344 /**< Fault injection Data Register,
-				        *  575-544 */
-#define XBRAM_FI_D_18_OFFSET	0x348 /**< Fault injection Data Register,
-				        *  607-576 */
-#define XBRAM_FI_D_19_OFFSET	0x34C /**< Fault injection Data Register,
-				        *  639-608 */
-#define XBRAM_FI_D_20_OFFSET	0x350 /**< Fault injection Data Register,
-				        *  671-640 */
-#define XBRAM_FI_D_21_OFFSET	0x354 /**< Fault injection Data Register,
-				        *  703-672 */
-#define XBRAM_FI_D_22_OFFSET	0x358 /**< Fault injection Data Register,
-				        *  735-704 */
-#define XBRAM_FI_D_23_OFFSET	0x35C /**< Fault injection Data Register,
-				        *  767-736 */
-#define XBRAM_FI_D_24_OFFSET	0x360 /**< Fault injection Data Register,
-				        *  799-768 */
-#define XBRAM_FI_D_25_OFFSET	0x364 /**< Fault injection Data Register,
-				        *  831-800 */
-#define XBRAM_FI_D_26_OFFSET	0x368 /**< Fault injection Data Register,
-				        *  863-832 */
-#define XBRAM_FI_D_27_OFFSET	0x36C /**< Fault injection Data Register,
-				        *  895-864 */
-#define XBRAM_FI_D_28_OFFSET	0x370 /**< Fault injection Data Register,
-				        *  927-896 */
-#define XBRAM_FI_D_29_OFFSET	0x374 /**< Fault injection Data Register,
-				        *  959-928 */
-#define XBRAM_FI_D_30_OFFSET	0x378 /**< Fault injection Data Register,
-				        *  991-960 */
-#define XBRAM_FI_D_31_OFFSET	0x37C /**< Fault injection Data Register,
-				        *  1023-992 */
-
-#define XBRAM_FI_ECC_0_OFFSET	0x380 /**< Fault injection ECC Register,
-				        *  31-0 */
-#define XBRAM_FI_ECC_1_OFFSET	0x384 /**< Fault injection ECC Register,
-				        *  63-32 */
-#define XBRAM_FI_ECC_2_OFFSET	0x388 /**< Fault injection ECC Register,
-				        *  95-64 */
-#define XBRAM_FI_ECC_3_OFFSET	0x38C /**< Fault injection ECC Register,
-				        *  127-96 */
-#define XBRAM_FI_ECC_4_OFFSET	0x390 /**< Fault injection ECC Register,
-				        *  159-128 */
-#define XBRAM_FI_ECC_5_OFFSET	0x394 /**< Fault injection ECC Register,
-				        *  191-160 */
-#define XBRAM_FI_ECC_6_OFFSET	0x398 /**< Fault injection ECC Register,
-				        *  223-192 */
-#define XBRAM_FI_ECC_7_OFFSET	0x39C /**< Fault injection ECC Register,
-				        *  255-224 */
-
-
-/* @} */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the ECC status register and ECC interrupt enable register.
- * @{
- */
-#define XBRAM_IR_CE_MASK	0x2 /**< Mask for the correctable error */
-#define XBRAM_IR_UE_MASK	0x1 /**< Mask for the uncorrectable error */
-#define XBRAM_IR_ALL_MASK	0x3 /**< Mask of all bits */
-/*@}*/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XBram_In32  Xil_In32
-#define XBram_Out32 Xil_Out32
-
-#define XBram_In16  Xil_In16
-#define XBram_Out16 Xil_Out16
-
-#define XBram_In8  Xil_In8
-#define XBram_Out8 Xil_Out8
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a BRAM register. A 32 bit write is performed.
-*
-* @param	BaseAddress is the base address of the BRAM device register.
-* @param	RegOffset is the register offset from the base to write to.
-* @param	Data is the data written to the register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
-	XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a BRAM register. A 32 bit read is performed.
-*
-* @param	BaseAddress is the base address of the BRAM device registers.
-* @param	RegOffset is the register offset from the base to read from.
-*
-* @return	Data read from the register.
-*
-* @note		C-style signature:
-*		u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XBram_ReadReg(BaseAddress, RegOffset) \
-	XBram_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h

@@ -1,74 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_5
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note 	None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date		Changes
-* ----- -----  -------- -----------------------------------------------
-* 1.00  kvn    02/14/15 First release
-* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
-*       kvn    08/18/15 Modified Makefile according to compiler changes.
-* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
-*                       for MB BSPs. Instead it throws up a warning. This
-*                       fixes the CR#953056.
-* 1.5   sne    01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef XCORESIGHTPSDCC_H                /* prevent circular inclusions */
-#define XCORESIGHTPSDCC_H                /* by using protection macros */
-#ifndef __MICROBLAZE__
-#include <xil_types.h>
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-#endif
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h

@@ -1,47 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_7
-* @{
-* @details
-*
-* dummy file
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 2.5   ms   04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
-*                     parameter of cpu_cortexa9 in xparameters.h
-# 2.7   mus  07/03/18 Updated tcl to not to add default flags forcefully into
-#                     extra compiler flags. Now, user can remove default flags
-#                     from extra compiler flags. It fixes CR#998768.
-******************************************************************************/
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xddrps.h

@@ -1,62 +0,0 @@
-/*******************************************************************************
- *
- * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Except as contained in this notice, the name of the Xilinx shall not be used
- * in advertising or otherwise to promote the sale, use or other dealings in
- * this Software without prior written authorization from Xilinx.
- *
-*******************************************************************************/
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_0
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note	None.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0	 nsk  08/06/15 First Release
- * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
- *		       to support PBD Designs (CR #876857)
- *
- * </pre>
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xdebug.h

@@ -1,40 +0,0 @@
-#ifndef XDEBUG  /* prevent circular inclusions */
-#define XDEBUG  /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
-#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
-#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL)
-
-#define xdbg_stmnt(x)  x
-
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-#define xdbg_printf(...)
-
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XDEBUG */

df_datalink/bsp/ps7_cortexa9_0/include/xdevcfg.h

@@ -1,399 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.h
-* @addtogroup devcfg_v3_5
-* @{
-* @details
-*
-* The is the main header file for the Device Configuration Interface of the Zynq
-* device. The device configuration interface has three main functionality.
-*  1. AXI-PCAP
-*  2. Security Policy
-*  3. XADC
-* This current version of the driver supports only the AXI-PCAP and Security
-* Policy blocks. There is a separate driver for XADC.
-*
-* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
-* DMA embedded in the AXI PCAP provides the master interface to
-* the Device configuration block for any DMA transfers. The data transfer can
-* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
-* RAM/DDR/peripheral memory).
-*
-* The current driver only supports the downloading the FPGA bitstream and
-* readback of the decrypted image (sort of loopback).
-* The driver does not know what information needs to be written to the FPGA to
-* readback FPGA configuration register or memory data. The application above the
-* driver should take care of creating the data that needs to be downloaded to
-* the FPGA so that the bitstream can be readback.
-* This driver also does not support the reading of the internal registers of the
-* PCAP. The driver has no knowledge of the PCAP internals.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Device Configuration device.
-*
-* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
-* Interface. The user needs to first call the XDcfg_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XDcfg_CfgInitialize() API.
-*
-* <b>Interrupts</b>
-* The Driver implements an interrupt handler to support the interrupts provided
-* by this interface.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XDcfg driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
-*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-*		     APIs is words (32 bit) and not bytes.
-* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-*		     to add information that 2 LSBs of the Source/Destination
-*		     address when equal to 2�b01 indicate the last DMA command
-*		     of an overall transfer.
-*		     Destination Address passed to this API for secure transfers
-*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
-*		     resulting in the failure of secure transfers of
-*		     non-bitstream images.
-* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
-*		     set the mask instead of oring it with the
-*		     value read from the interrupt status register
-* 		     Added defines for the PS Version bits,
-*	             removed the FIFO Flush bits from the
-*		     Miscellaneous Control Reg.
-*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-*		     and XDcfg_SelectPcapInterface APIs for CR 643295
-*		     The user has to call the XDcfg_SelectIcapInterface API
-*		     for the PL reconfiguration using AXI HwIcap.
-*		     Updated the XDcfg_Transfer API to clear the
-*		     QUARTER_PCAP_RATE_EN bit in the control register for
-*		     non secure writes for CR 675543.
-* 2.02a nm  01/31/13 Fixed CR# 679335.
-* 		     Added Setting and Clearing the internal PCAP loopback.
-*		     Removed code for enabling/disabling AES engine as BootROM
-*		     locks down this setting.
-*		     Fixed CR# 681976.
-*		     Skip Checking the PCFG_INIT in case of non-secure DMA
-*		     loopback.
-*		     Fixed CR# 699558.
-*		     XDcfg_Transfer fails to transfer data in loopback mode.
-*		     Fixed CR# 701348.
-*                    Peripheral test fails with  Running
-* 		     DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm  04/19/13 Fixed CR# 703728.
-*		     Updated the register definitions as per the latest TRM
-*		     version UG585 (v1.4) November 16, 2012.
-* 3.0   adk 10/12/13 Updated as per the New Tcl API's
-* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
-*		     updated driver code with != instead of ==,
-*		     while checking for Interrupt Status with DMA and
-*		     PCAP Done Mask
-*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-*			XDCFG_INT_STS_OFFSET) &
-*			XDCFG_IXR_D_P_DONE_MASK) !=
-*			XDCFG_IXR_D_P_DONE_MASK);
-*		     A new example has been added to read back the
-*		     configuration registers from the PL region.
-*		     xdevcfg_reg_readback_example.c
-* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
-*                    generation.
-*       ms  04/10/17 Modified filename tag in interrupt and polled examples
-*                    to include them in doxygen examples.
-* 3.5   ms  04/18/17 Modified tcl file to add suffix U for all macros
-*                    definitions of devcfg in xparameters.h
-*       ms  08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-* </pre>
-*
-******************************************************************************/
-#ifndef XDCFG_H		/* prevent circular inclusions */
-#define XDCFG_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE		1
-#define XDCFG_SECURE_PCAP_WRITE			2
-#define XDCFG_PCAP_READBACK			3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE	4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE	5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param	CallBackRef is the callback reference passed in by the upper
-*		layer when setting the callback functions, and passed back to
-*		the upper layer when the callback is invoked. Its type is
-*		unimportant to the driver component, so it is a void pointer.
-* @param	Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddr;		/**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
-	XDcfg_Config Config;	/**< Hardware Configuration */
-	u32 IsReady;		/**< Device is initialized and ready */
-	u32 IsStarted;		/**< Device Configuration Interface
-				  * is running
-				  */
-	XDcfg_IntrHandler StatusHandler;  /* Event handler function */
-	void *CallBackRef;	/* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param	InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr)					\
-	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, 			\
-	XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param	InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return	Version of the PS.
-*
-* @note		C-style signature:
-*		void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr)					\
-	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, 		\
-			XDCFG_MCTRL_OFFSET)) & 				\
-			XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> 		\
-			XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param	InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr)			\
-	XDcfg_ReadReg((InstancePtr)->Config.BaseAddr,  		\
-			XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param	InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr)				  \
-	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET,   \
-	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
-	& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param	InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr)				   \
-	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET,    \
-	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET))  \
-	| XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
-			 XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
-				u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
-				void *SourcePtr, u32 SrcWordLength,
-				void *DestPtr, u32 DestWordLength,
-				u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
-				void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xdevcfg_hw.h

@@ -1,391 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_3
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm  08/01/12 Added defines for the PS Version bits,
-*	             removed the FIFO Flush bits from the
-*		     Miscellaneous Control Reg
-* 2.03a nm  04/19/13 Fixed CR# 703728.
-*		     Updated the register definitions as per the latest TRM
-*		     version UG585 (v1.4) November 16, 2012.
-* 2.04a	kpc	10/07/13 Added function prototype.
-* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-* </pre>
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H		/* prevent circular inclusions */
-#define XDCFG_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET		0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET		0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET		0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET		0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET		0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET		0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET	0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET	0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET	0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET	0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET		0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET	0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET		0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET		0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET		0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
-  * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK	0x80000000 /**< Force  into
-						     * Secure Reset
-						     */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK	0x40000000 /**< Program signal to
-						     *  Reset FPGA
-						     */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK	0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK	  	0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK	0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK	0x02000000 /**< Enable PCAP send data
-						     *  to FPGA every 4 PCAP
-						     *  cycles
-						     */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK	0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK	0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK	0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK	0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK	0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK		0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK		0x00000080 /**< Secure/Non Secure
-						     *  Status mask
-						     */
-#define XDCFG_CTRL_SPNIDEN_MASK		0x00000040 /**< Secure Non Invasive
-						     *  Debug Enable
-						     */
-#define XDCFG_CTRL_SPIDEN_MASK		0x00000020 /**< Secure Invasive
-						     *  Debug Enable
-						     */
-#define XDCFG_CTRL_NIDEN_MASK		0x00000010 /**< Non-Invasive Debug
-						     *  Enable
-						     */
-#define XDCFG_CTRL_DBGEN_MASK		0x00000008 /**< Invasive Debug
-						     *  Enable
-						     */
-#define XDCFG_CTRL_DAP_EN_MASK		0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
-  * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK	0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK		0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK		0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK		0x00000002 /**< Lock SEC_EN and
-						     *  USER_MODE
-						     */
-#define XDCFG_LOCK_DBG_MASK		0x00000001 /**< This bit locks
-						     *  security config
-						     *  including: DAP_En,
-						     *  DBGEN,,
-						     *  NIDEN, SPNIEN
-						     */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
-  * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK	  	0x00000C00 /**< Read FIFO
-						     *  Threshold Mask
-						     */
-#define XDCFG_CFG_WFIFO_TH_MASK	  	0x00000300 /**< Write FIFO Threshold
-						     *  Mask
-						     */
-#define XDCFG_CFG_RCLK_EDGE_MASK	0x00000080 /**< Read data active
-						     *  clock edge
-						     */
-#define XDCFG_CFG_WCLK_EDGE_MASK	0x00000040 /**< Write data active
-						     *  clock edge
-						     */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK	0x00000020 /**< Disable Source address
-						     *  increment mask
-						     */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK	0x00000010 /**< Disable Destination
-						     *  address increment
-						     *  mask
-						     */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
-  * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK	0x80000000 /**< Tri-state IO during
-						     *  HIZ
-						     */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK	0x40000000 /**< First configuration
-						     *  done
-						     */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK	0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK	0x10000000 /**< Tri-state IO during
-						     *  configuration
-						     */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK	0x08000000 /**< PL configuration
-						     *  reset
-						     */
-#define XDCFG_IXR_AXI_WTO_MASK		0x00800000 /**< AXI Write Address
-						     *  or Data or response
-						     *  timeout
-						     */
-#define XDCFG_IXR_AXI_WERR_MASK		0x00400000 /**< AXI Write response
-						     *  error
-						     */
-#define XDCFG_IXR_AXI_RTO_MASK		0x00200000 /**< AXI Read Address or
-						     *  response timeout
-						     */
-#define XDCFG_IXR_AXI_RERR_MASK		0x00100000 /**< AXI Read response
-						     *  error
-						     */
-#define XDCFG_IXR_RX_FIFO_OV_MASK	0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK	0x00020000 /**< Tx FIFO less than
-						     *  threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK	0x00010000 /**< Rx FIFO greater than
-						     *  threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK	0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK		0x00004000 /**< DMA command queue
-						     *  overflow
-						     */
-#define XDCFG_IXR_DMA_DONE_MASK		0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK		0x00001000 /**< DMA and PCAP
-						     *  transfers Done
-						     */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK	0x00000800 /**< PCAP to DMA transfer
-						     *  length error
-						     */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK	0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK	0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK	0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK	0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK	0x00000004 /**< Done Signal  Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK	0x00000002 /**< Detect Positive edge
-						     *  of Init Signal
-						     */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK  	0x00000001 /**< Detect Negative edge
-						     *  of Init Signal
-						     */
-#define XDCFG_IXR_ERROR_FLAGS_MASK		(XDCFG_IXR_AXI_WTO_MASK | \
-						XDCFG_IXR_AXI_WERR_MASK | \
-						XDCFG_IXR_AXI_RTO_MASK |  \
-						XDCFG_IXR_AXI_RERR_MASK | \
-						XDCFG_IXR_RX_FIFO_OV_MASK | \
-						XDCFG_IXR_DMA_CMD_ERR_MASK |\
-						XDCFG_IXR_DMA_Q_OV_MASK |   \
-						XDCFG_IXR_P2D_LEN_ERR_MASK |\
-						XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK			0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
-  * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK	0x80000000 /**< DMA command
-						     *  Queue full
-						     */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK	0x40000000 /**< DMA command
-						     *  Queue empty
-						     */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000 /**< Number of
-						     *  completed DMA
-						     *  transfers
-						     */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK	0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK	0x0007F000  /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B	0x00000800  /**< Tri-state IO
-						      *  during HIZ
-						      */
-#define XDCFG_STATUS_PSS_FST_CFG_B	0x00000400  /**< First PL config
-						      *  done
-						      */
-#define XDCFG_STATUS_PSS_GPWRDWN_B	0x00000200  /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B	0x00000100  /**< Tri-state IO during
-						      *  config
-						      */
-#define XDCFG_STATUS_SECURE_RST_MASK	0x00000080  /**< Secure Reset
-						      *  POR Status
-						      */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 	0x00000040 /**< Illegal APB
-							     *  access
-							     */
-#define XDCFG_STATUS_PSS_CFG_RESET_B		0x00000020 /**< PL config
-							     *  reset status
-							     */
-#define XDCFG_STATUS_PCFG_INIT_MASK		0x00000010 /**< FPGA Init
-							     *  Status
-							     */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK	0x00000008
-							   /**< BBRAM key
-							     *  disable
-							     */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK		0x00000004 /**< Efuse Security
-							     *  Enable Status
-							     */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK	0x00000002 /**< EFuse JTAG
-							     *  Disable
-							     *  status
-							     */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK		0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control  Register Bit definitions
-  * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK  0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28	     /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK	  0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
-  * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER		0x0	 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF		0x1	 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER		0x2	 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY		0x4	 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS	0xFFFFFFFF  /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA		0x757BDF0D  /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS		0xF8007000  /**< Device Config base
-						      * address
-						      */
-#define XDCFG_CONFIG_RESET_VALUE	0x508	/**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param	BaseAddr is the base address of the device
-* @param	RegOffset is the register offset to be read
-*
-* @return	The 32-bit value of the register
-*
-* @note		C-style signature:
-*		u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset)		\
-	Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param	BaseAddr is the base address of the device
-* @param	RegOffset is the register offset to be written
-* @param	Data is the 32-bit value to write to the register
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)	\
-	Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xdmaps.h

@@ -1,349 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal 
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps.h
-* @addtogroup dmaps_v2_4
-* @{
-* @details
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  	Date     Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00	hbm    08/19/10 First Release
-* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-*		        the maximum number of channels.
-*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-*			Added the tcl file to automatically generate the
-*			xparameters.h
-* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
-*			header from the xdmaps.h file to xdmaps.c file
-*			Other cleanup for coding guidelines and CR 657109
-*			and CR 657898
-*			The xdmaps_example_no_intr.c example is removed
-*			as it is using interrupts  and is similar to
-*			the interrupt example - CR 652477
-* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm     10/22/2012 Fixed CR# 681671.
-* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-*			  with -Wall and -Wextra option in bsp.
-*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-*			  function description.
-*			  Fixed CR# 704396. Removed unused variables
-*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-*			  function.
-* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
-*			   Removed the PDBG prints. By default they were always
-*			   defined out and never used. The PDBG is non-standard for
-*			   Xilinx drivers and no other driver does something similar.
-*			   Since there is no easy way to fix compilation issues with
-*			   the IARCC compiler around PDBG, it is better to remove it.
-*			   Users can always use xil_printfs if they want to debug.
-* 2.0   adk    10/12/13  Updated as per the New Tcl API's
-* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
-* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
-*                        linker error for IAR compiler
-* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
-*                       examples to ensure that "Successfully ran" and "Failed"
-*                       strings are available in all examples. This is a fix
-*                       for CR-965028.
-*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
-*                       generation.
-* 2.4   adk    13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H		/* prevent circular inclusions */
-#define XDMAPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;	 /**< Unique ID  of device */
-	u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
-	unsigned int EndianSwapSize;	/**< Endian swap size. */
-	unsigned int DstCacheCtrl;	/**< Destination cache control */
-	unsigned int DstProtCtrl;	/**< Destination protection control */
-	unsigned int DstBurstLen;	/**< Destination burst length */
-	unsigned int DstBurstSize;	/**< Destination burst size */
-	unsigned int DstInc;		/**< Destination incrementing or fixed
-					 *   address */
-	unsigned int SrcCacheCtrl;	/**< Source cache control */
-	unsigned int SrcProtCtrl;	/**< Source protection control */
-	unsigned int SrcBurstLen;	/**< Source burst length */
-	unsigned int SrcBurstSize;	/**< Source burst size */
-	unsigned int SrcInc;		/**< Source incrementing or fixed
-					 *   address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
-	u32 SrcAddr;		/**< Source starting address */
-	u32 DstAddr;		/**< Destination starting address */
-	unsigned int Length;	/**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
-	XDmaPs_ChanCtrl ChanCtrl; 	/**< Channel Control Struct */
-	XDmaPs_BD BD;			/**< Together with SgLength field,
-					  *  it's a scatter-gather list.
-					  */
-	void *UserDmaProg;		/**< If user wants the driver to
-					  *  execute their own DMA program,
-					  *  this field points to the DMA
-					  *  program.
-					  */
-	int UserDmaProgLength;		/**< The length of user defined
-					  *  DMA program.
-					  */
-
-	void *GeneratedDmaProg;		/**< The DMA program genreated
-					 * by the driver. This field will be
-					 * set if a user invokes the DMA
-					 * program generation function. Or
-					 * the DMA command is finished and
-					 * a user informs the driver not to
-					 * release the program buffer.
-					 * This field has two purposes, one
-					 * is to ask the driver to generate
-					 * a DMA program while the DMAC is
-					 * performaning DMA transactions. The
-					 * other purpose is to debug the
-					 * driver.
-					 */
-	int GeneratedDmaProgLength;	 /**< The length of the DMA program
-					  * generated by the driver
-					  */
-	int DmaStatus;			/**< 0 on success, otherwise error code
-					 */
-	u32 ChanFaultType;	/**< Channel fault type in case of fault
-				 */
-	u32 ChanFaultPCAddr;	/**< Channel fault PC address
-				 */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
-				    XDmaPs_Cmd *DmaCmd,
-				    void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
-				     XDmaPs_Cmd *DmaCmd,
-				     void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS	2
-#define XDMAPS_CHAN_BUF_LEN	128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
-	char Buf[XDMAPS_CHAN_BUF_LEN];  /**< The actual buffer the holds the
-					  *  content */
-	unsigned Len;			/**< The actual length of the DMA
-					  *  program in bytes. */
-	int Allocated;			/**< A tag indicating whether the
-					  *  buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
-	unsigned DevId;		 	/**< Device id indicating which DMAC */
-	unsigned ChanId; 		/**< Channel number of the DMAC */
-	XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
-							      program buffers*/
-	XDmaPsDoneHandler DoneHandler; 	/**< Done interrupt handler */
-	void *DoneRef;			/**< Done interrupt callback data */
-	XDmaPs_Cmd *DmaCmdToHw; 	/**< DMA command being executed */
-	XDmaPs_Cmd *DmaCmdFromHw; 	/**< DMA  command that is finished.
-				     	  *  This field is for debugging purpose
-				     	  */
-	int HoldDmaProg;		/**< A tag indicating whether to hold the
-					  *  DMA program after the DMA is done.
-					  */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
-	XDmaPs_Config Config;	/**< Configuration data structure */
-	int IsReady;		/**< Device is Ready */
-	int CacheLength;	/**< icache length */
-	XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
-	void *FaultRef;	/**< fault call back data */
-	XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
-	/**<
-	 * channel data
-	 */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
-			  XDmaPs_Config *Config,
-			  u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
-		  XDmaPs_Cmd *Cmd,
-		  int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
-		       XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
-			XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
-			   unsigned Channel,
-			   XDmaPsDoneHandler DoneHandler,
-			   void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
-			    XDmaPsFaultHandler FaultHandler,
-			    void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-int XDmaPs_Instr_DMARMB(char *DmaProg);
-int XDmaPs_Instr_DMAWMB(char *DmaProg);
-
-/**
- * To avoid linking error,Declare all inline functions as extern for
- * IAR compiler
- */
-#ifdef __ICCARM__
-extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
-			       u32 Imm, unsigned int Ns);
-extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
-	       unsigned LoopIterations);
-extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xdmaps_hw.h

@@ -1,289 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal 
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_4
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who   Date     Changes
-* ----- ----  -------- ----------------------------------------------
-* 1.00a	hbm   08/18/10 First Release
-* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-*		       the maximum number of channels.
-*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg    05/16/12 Made changes for doxygen
-* 1.06a kpc   07/10/13 Added function prototype
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H		/* prevent circular inclusions */
-#define XDMAPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET		0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET	0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET	0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET		0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET	0x028 /* DMA Interrupt Status Register
-					       */
-#define XDMAPS_INTCLR_OFFSET	0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 	0x030 /* DMA Fault Status DMA Manager
-				       * Register
-				       */
-#define XDMAPS_FSC_OFFSET	0x034 /* DMA Fault Status DMA Chanel Register
-				       */
-#define XDMAPS_FTM_OFFSET	0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET	0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch)	(XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET	0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch)	(XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET	0x104 /* Channel Program Counter for DMA
-				       * Channel 0
-				       */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch)	(XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET	0x400 /* Source Address Register for DMA
-				       * Channel 0
-				       */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch)	(XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET	0x404 /* Destination Address Register for
-				       * DMA Channel 0
-				       */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch)	(XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET	0x408 /* Channel Control Register for
-				       * DMA Channel 0
-				       */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch)	(XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET	0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch)	(XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET	0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch)	(XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET	0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET	0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET	0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET	0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET	0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET	0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET	0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET	0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET	0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET	0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET	0xFE0 /* Peripheral Identification
-					       * Register 0
-					       */
-#define XDMAPS_PERIPH_ID_1_OFFSET	0xFE4 /* Peripheral Identification
-					       * Register 1
-					       */
-#define XDMAPS_PERIPH_ID_2_OFFSET	0xFE8 /* Peripheral Identification
-					       * Register 2
-					       */
-#define XDMAPS_PERIPH_ID_3_OFFSET	0xFEC /* Peripheral Identification
-					       * Register 3
-					       */
-#define XDMAPS_PCELL_ID_0_OFFSET	0xFF0 /* PrimeCell Identification
-				       * Register 0
-				       */
-#define XDMAPS_PCELL_ID_1_OFFSET	0xFF4 /* PrimeCell Identification
-				       * Register 1
-				       */
-#define XDMAPS_PCELL_ID_2_OFFSET	0xFF8 /* PrimeCell Identification
-				       * Register 2
-				       */
-#define XDMAPS_PCELL_ID_3_OFFSET	0xFFC /* PrimeCell Identification
-				       * Register 3
-				       */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS		0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED	0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY		0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK		0x07 /* channel status active mask,
-					      * llast 3 bits of CS register
-					      */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK	0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
-	(((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV		8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK		0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
-    Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param    BaseAddress contains the base address of the device.
-* @param    RegOffset contains the offset from the base address of the device.
-* @param    RegisterValue is the value to be written to the register.
-*
-* @return   None.
-*
-* @note
-* C-Style signature:
-*    void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-*                          u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
-    Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xenv.h

@@ -1,183 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch   10/24/02 Added XENV_LINUX
-* 1.00a rmm  04/17/02 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param   DestPtr is the destination address to copy data to.
- * @param   SrcPtr is the source address to copy data from.
- * @param   Bytes is the number of bytes to copy.
- *
- * @return  None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param   DestPtr is the destination address to set.
- * @param   Data contains the value to set.
- * @param   Bytes is the number of bytes to set.
- *
- * @return  None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param   StampPtr is the storage for the retrieved time stamp.
- *
- * @return  None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param   Stamp1Ptr - First sampled time stamp.
- * @param   Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return  An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param   Stamp1Ptr - First sampled time stamp.
- * @param   Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return  An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param   delay is the number of microseconds to delay.
- *
- * @return  None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif            /* end of protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xenv_standalone.h

@@ -1,364 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* 	This file is not intended to be included directly by driver code.
-* 	Instead, the generic xenv.h file is intended to be included by driver
-* 	code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr  02/28/07 Added cache handling macros.
-* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-*                     used under Xilinx standalone BSP.
-* 1.00a xd   11/03/04 Improved support for doxygen.
-* 1.00a rmm  03/21/02 First release
-* 1.00a wgr  03/22/07 Converted to new coding style.
-* 1.00a rpm  06/29/07 Added udelay macro for standalone
-* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
-*                     to in MICROBLAZE section
-* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include <string.h>
-
-#if defined __MICROBLAZE__
-#  include "mb_interface.h"
-#  include "xparameters.h"   /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-#  include "sleep.h"
-#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param	DestPtr
- *		Destination address to copy data to.
- *
- * @param	SrcPtr
- * 		Source address to copy data from.
- *
- * @param	Bytes
- * 		Number of bytes to copy.
- *
- * @return	None.
- *
- * @note
- * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * 		This implemention MAY BREAK work if source and target memory
- * 		area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
-	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param	DestPtr
- *		Destination address to copy data to.
- *
- * @param	Data
- * 		Value to set.
- *
- * @param	Bytes
- * 		Number of bytes to copy.
- *
- * @return	None.
- *
- * @note
- * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
-	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param   StampPtr is the storage for the retrieved time stamp.
- *
- * @return  None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- * <br><br>
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param   Stamp1Ptr is the first sampled time stamp.
- * @param   Stamp2Ptr is the second sampled time stamp.
- *
- * @return  0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param   Stamp1Ptr is the first sampled time stamp.
- * @param   Stamp2Ptr is the second sampled time stamp.
- *
- * @return  0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param	delay
- * 		Number of microseconds to delay.
- *
- * @return	None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay)	usleep(delay)
-#define udelay(delay)	usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE()	\
-		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE()	\
-		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
-#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
-#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
-
-#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
-			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
-#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
-			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
-#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
-			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-#  define XCACHE_ENABLE_DCACHE()
-#  define XCACHE_DISABLE_DCACHE()
-#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
-#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
-
-#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
-
-#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
-			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-#  define XCACHE_ENABLE_ICACHE()
-#  define XCACHE_DISABLE_ICACHE()
-#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- *   specific memory region (0x80000001). Each bit (0-30) in the regions
- *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- *   range.
- *
- *   regions    --> cached address range
- *   ------------|--------------------------------------------------
- *   0x80000000  | [0, 0x7FFFFFF]
- *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
- *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
-		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
-		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* #ifndef XENV_STANDALONE_H */

df_datalink/bsp/ps7_cortexa9_0/include/xgpiops.h

@@ -1,283 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_5
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-*	- 4 banks
-*	- Masked writes (There are no masked reads)
-*	- Bypass mode
-*	- Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* <b>Driver Description</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* <b>Interrupts</b>
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* <b>Threads</b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b>Asserts</b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b>Building the driver</b>
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv   01/15/10 First Release
-* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-*		      relevant to Zynq device.The interrupts are disabled
-*		      for output pins on all banks during initialization.
-* 1.02a hk   08/22/13 Added low level reset API
-* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
-* 					  passed to APIs. CR# 822636
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
-*                     generation.
-*       ms   04/05/17 Added tabspace for return statements in functions of
-*                     gpiops examples for proper documentation while
-*                     generating doxygen.
-* 3.3   ms   04/17/17 Added notes about gpio input and output pin description
-*                     for zcu102 and zc702 boards in polled and interrupt
-*                     example, configured Interrupt pin to input pin for
-*                     proper functioning of interrupt example.
-* 3.4   aru  08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
-*                     in saftey mode and modified the code such as
-*                     Use of mixed mode arithmetic,Declared the poiner param
-*                     as Pointer to const,Casting operation to a pointer,
-*                     Literal value requires a U suffix.
-* 3.5   sne  03/14/19 Added Versal support.
-* </pre>
-*
-******************************************************************************/
-#ifndef XGPIOPS_H		/* prevent circular inclusions */
-#define XGPIOPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- *  @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
-/*@}*/
-
-#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
-										*	Zynq Ultrascale+ MP GPIO device
-										*/
-#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
-						  *	Zynq Ultrascale+ MP GPIO device
-					      * 0 - 25,  Bank 0
-					      * 26 - 51, Bank 1
-					      *	52 - 77, Bank 2
-					      *	78 - 109, Bank 3
-					      *	110 - 141, Bank 4
-					      *	142 - 173, Bank 5
-					      */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
-					      * 0 - 31,  Bank 0
-					      * 32 - 53, Bank 1
-					      *	54 - 85, Bank 2
-					      *	86 - 117, Bank 3
-					      */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the callback functions for a GPIO bank. It is
- *		passed back to the upper layer when the callback is invoked. Its
- *		type is not important to the driver component, so it is a void
- *		pointer.
- * @param	Bank is the bank for which the interrupt status has changed.
- * @param	Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddr;		/**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XGpioPs_Config GpioConfig;	/**< Device configuration */
-	u32 IsReady;			/**< Device is initialized and ready */
-	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
-	void *CallBackRef; 		/**< Callback ref for bank handlers */
-	u32 Platform;			/**< Platform data */
-	u32 MaxPinNum;			/**< Max pins in the GPIO device */
-	u8 MaxBanks;			/**< Max banks in a GPIO device */
-        u32 PmcGpio;                    /**< Flag for accessing PS GPIO for versal*/
-} XGpioPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
-			   u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#else
-void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#endif
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
-			  u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
-			  u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
-			     XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xgpiops_hw.h

@@ -1,168 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_5
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv   01/15/10 First Release
-* 1.02a hk   08/22/13 Added low level reset API function prototype and
-*                     related constant definitions
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Corrected reset values of banks.
-* 3.5   sne  03/14/19 Added versal support.
-* </pre>
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
-#define XGPIOPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- *  @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
-/* @} */
-
-/** @name Register offsets for each Bank.
- *  @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
-/* @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
-
-/** @name Interrupt type reset values for each bank
- *  @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
-#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
-#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
-/* @} */
-#define XGPIOPS_PS_GPIO_BASEADDR     0xFF0B0000U     /* Flag for Base Address for PS_GPIO in Versal */
-#define XGPIOPS_ZERO    0U  /* Flag for 0 Value */
-#define XGPIOPS_ONE     1U  /* Flag for 1 Value */
-#define XGPIOPS_TWO     2U  /* Flag for 2 Value */
-#define XGPIOPS_THREE   3U  /* Flag for 3 Value */
-#define XGPIOPS_FOUR    4U  /* Flag for 4 Value */
-#define XGPIOPS_SIX     6U  /* Flag for 6 Value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param	BaseAddr is the base address of the device.
-* @param	RegOffset is the register offset to be read.
-*
-* @return	The 32-bit value of the register
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
-		Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param	BaseAddr is the base address of the device.
-* @param	RegOffset is the offset of the register to be written.
-* @param	Data is the 32-bit value to write to the register.
-*
-* @return	None.
-*
-* @note		None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
-		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(u32 BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xil_assert.h

@@ -1,191 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/14/09 First release
-* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
-#define XIL_ASSERT_H	/* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE     0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief    This assert macro is to be used for void functions. This in
-*           conjunction with the Xil_AssertWait boolean can be used to
-*           accomodate tests so that asserts which fail allow execution to
-*           continue.
-*
-* @param    Expression: expression to be evaluated. If it evaluates to
-*           false, the assert occurs.
-*
-* @return   Returns void unless the Xil_AssertWait variable is true, in which
-*           case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression)                \
-{                                                  \
-    if (Expression) {                              \
-        Xil_AssertStatus = XIL_ASSERT_NONE;       \
-    } else {                                       \
-        Xil_Assert(__FILE__, __LINE__);            \
-        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
-        return;                                    \
-    }                                              \
-}
-
-/*****************************************************************************/
-/**
-* @brief    This assert macro is to be used for functions that do return a
-*           value. This in conjunction with the Xil_AssertWait boolean can be
-*           used to accomodate tests so that asserts which fail allow execution
-*           to continue.
-*
-* @param    Expression: expression to be evaluated. If it evaluates to false,
-*           the assert occurs.
-*
-* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
-* 	        case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression)             \
-{                                                  \
-    if (Expression) {                              \
-        Xil_AssertStatus = XIL_ASSERT_NONE;       \
-    } else {                                       \
-        Xil_Assert(__FILE__, __LINE__);            \
-        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
-        return 0;                                  \
-    }                                              \
-}
-
-/*****************************************************************************/
-/**
-* @brief     Always assert. This assert macro is to be used for void functions.
-*            Use for instances where an assert should always occur.
-*
-* @return    Returns void unless the Xil_AssertWait variable is true, in which
-*	         case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways()                   \
-{                                                  \
-   Xil_Assert(__FILE__, __LINE__);                 \
-   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
-   return;                                         \
-}
-
-/*****************************************************************************/
-/**
-* @brief   Always assert. This assert macro is to be used for functions that
-*          do return a value. Use for instances where an assert should always
-*          occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-*	      case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways()                \
-{                                                  \
-   Xil_Assert(__FILE__, __LINE__);                 \
-   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
-   return 0;                                       \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_cache.h

@@ -1,118 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm  01/29/10 First release
-* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-*		      APIs.
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __GNUC__
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
-			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
-			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
-			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
-			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
-			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#elif defined (__ICCARM__)
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
-			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
-			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
-			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
-			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
-			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#endif
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_cache_l.h

@@ -1,97 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm  01/24/10 First release
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h

@@ -1,89 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  12/11/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
-		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
-		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
-		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

df_datalink/bsp/ps7_cortexa9_0/include/xil_errata.h

@@ -1,127 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note
-* The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt  04/18/13 First release
-* 6.6   mus  12/07/17 Removed errata 753970, It fixes CR#989132.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- *  Errata No: 	 742230
- *  Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- *  Errata No: 	 743622
- *  Description: Faulty hazard checking in the Store Buffer may lead
- *	         	 to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- *  Errata No: 	 775420
- *  Description: A data cache maintenance operation which aborts,
- *		 		 might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- *  Errata No: 	 794073
- *  Description: Speculative instruction fetches with MMU disabled
- *               might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- *  Errata No: 	 588369
- *  Description: Clean & Invalidate maintenance operations do not
- *	   	 		 invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- *  Errata No: 	 727915
- *  Description: Background Clean and Invalidate by Way operation
- *		 can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif  /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_exception.h

@@ -1,285 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2	pkp  	 28/05/15 First release
-* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7   mna      26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7   asa      18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0   mus      01/03/19 Tweak Xil_ExceptionEnableMask and
-*                         Xil_ExceptionDisableMask macros to support legacy
-*                         examples for Cortexa72 EL3 exception level.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST			0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT		1U
-#define XIL_EXCEPTION_ID_IRQ_INT		2U
-#define XIL_EXCEPTION_ID_FIQ_INT		3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
-#define XIL_EXCEPTION_ID_LAST			5U
-#else
-#define XIL_EXCEPTION_ID_RESET			0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
-#define XIL_EXCEPTION_ID_SWI_INT		2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
-#define XIL_EXCEPTION_ID_IRQ_INT		5U
-#define XIL_EXCEPTION_ID_FIQ_INT		6U
-#define XIL_EXCEPTION_ID_LAST			6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT    XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief	Enable Exceptions.
-*
-* @param	Mask: Value for enabling the exceptions.
-*
-* @return	None.
-*
-* @note		If bit is 0, exception is enabled.
-*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask)	\
-		mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask)	\
-		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask)	\
-		{								\
-		  register u32 Reg __asm("cpsr"); \
-		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
-		}
-#endif
-/****************************************************************************/
-/**
-* @brief	Enable the IRQ exception.
-*
-* @return   None.
-*
-* @note     None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
-                Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
-		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief	Disable Exceptions.
-*
-* @param	Mask: Value for disabling the exceptions.
-*
-* @return	None.
-*
-* @note		If bit is 1, exception is disabled.
-*			C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask)	\
-		mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask)	\
-		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask)	\
-		{									\
-		  register u32 Reg __asm("cpsr"); \
-		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
-		}
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return   None.
-*
-* @note     None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
-		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if !defined (__aarch64__) && !defined (ARMA53_32)
-/****************************************************************************/
-/**
-* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
-* 			API is defined for cortex-a9 and cortex-r5.
-*
-* @return   None.
-*
-* @note     This macro is supposed to be used from interrupt handlers. In the
-*			interrupt handler the interrupts are disabled by default (I and F
-*			are 1). To allow nesting of interrupts, this macro should be
-*			used. It clears the I and F bits by changing the ARM mode to
-*			system mode. Once these bits are cleared and provided the
-*			preemption of interrupt conditions are met in the GIC, nesting of
-*			interrupts will start happening.
-*			Caution: This macro must be used with caution. Before calling this
-*			macro, the user must ensure that the source of the current IRQ
-*			is appropriately cleared. Otherwise, as soon as we clear the I and
-*			F bits, there can be an infinite loop of interrupts with an
-*			eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
-		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
-		__asm__ __volatile__ ("mrs     lr, spsr");  \
-		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
-		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
-		__asm__ __volatile__ ("stmfd   sp!, {lr}");
-
-/****************************************************************************/
-/**
-* @brief	Disable the nested interrupts by setting the I and F bits. This API
-*			is defined for cortex-a9 and cortex-r5.
-*
-* @return   None.
-*
-* @note     This macro is meant to be called in the interrupt service routines.
-*			This macro cannot be used independently. It can only be used when
-*			nesting of interrupts have been enabled by using the macro
-*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
-*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-*			point. The user then must call this macro before exiting the interrupt
-*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
-*			hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
-		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
-		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
-		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
-		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
-		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
-					 Xil_ExceptionHandler Handler,
-					 void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
-					Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_hal.h

@@ -1,65 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

df_datalink/bsp/ps7_cortexa9_0/include/xil_io.h

@@ -1,341 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 05/29/14 First release
-* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-*                         ARM processors
-* </pre>
-******************************************************************************/
-
-#ifndef XIL_IO_H           /* prevent circular inclusions */
-#define XIL_IO_H           /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-u16 Xil_EndianSwap16(u16 Data);
-u32 Xil_EndianSwap32(u32 Data);
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-#  define INST_SYNC		mbar(0)
-#  define DATA_SYNC		mbar(1)
-# else
-#  define SYNCHRONIZE_IO	dmb()
-#  define INST_SYNC		isb()
-#  define DATA_SYNC		dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an input operation for a memory location by reading
-*           from the specified address and returning the 8 bit Value read from
-*            that address.
-*
-* @param	Addr: contains the address to perform the input operation
-*
-* @return	The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
-	return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an input operation for a memory location by reading from
-*           the specified address and returning the 16 bit Value read from that
-*           address.
-*
-* @param	Addr: contains the address to perform the input operation
-*
-* @return	The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
-	return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an input operation for a memory location by
-*           reading from the specified address and returning the 32 bit Value
-*           read  from that address.
-*
-* @param	Addr: contains the address to perform the input operation
-*
-* @return	The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
-	return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief     Performs an input operation for a memory location by reading the
-*            64 bit Value read  from that address.
-*
-*
-* @param	Addr: contains the address to perform the input operation
-*
-* @return	The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
-	return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an output operation for an memory location by
-*           writing the 8 bit Value to the the specified address.
-*
-* @param	Addr: contains the address to perform the output operation
-* @param	Value: contains the 8 bit Value to be written at the specified
-*           address.
-*
-* @return	None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
-	volatile u8 *LocalAddr = (volatile u8 *)Addr;
-	*LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an output operation for a memory location by writing the
-*            16 bit Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-* @param	Value contains the Value to be written at the specified address.
-*
-* @return	None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
-	volatile u16 *LocalAddr = (volatile u16 *)Addr;
-	*LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an output operation for a memory location by writing the
-*           32 bit Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-* @param	Value contains the 32 bit Value to be written at the specified
-*           address.
-*
-* @return	None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
-#ifndef ENABLE_SAFETY
-	volatile u32 *LocalAddr = (volatile u32 *)Addr;
-	*LocalAddr = Value;
-#else
-	XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief    Performs an output operation for a memory location by writing the
-*           64 bit Value to the the specified address.
-*
-* @param	Addr contains the address to perform the output operation
-* @param	Value contains 64 bit Value to be written at the specified address.
-*
-* @return	None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
-	volatile u64 *LocalAddr = (volatile u64 *)Addr;
-	*LocalAddr = Value;
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE	Xil_In16
-# define Xil_In32LE	Xil_In32
-# define Xil_Out16LE	Xil_Out16
-# define Xil_Out32LE	Xil_Out32
-# define Xil_Htons	Xil_EndianSwap16
-# define Xil_Htonl	Xil_EndianSwap32
-# define Xil_Ntohs	Xil_EndianSwap16
-# define Xil_Ntohl	Xil_EndianSwap32
-# else
-# define Xil_In16BE	Xil_In16
-# define Xil_In32BE	Xil_In32
-# define Xil_Out16BE	Xil_Out16
-# define Xil_Out32BE	Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE	Xil_In16
-# define Xil_In32LE	Xil_In32
-# define Xil_Out16LE	Xil_Out16
-# define Xil_Out32LE	Xil_Out32
-# define Xil_Htons	Xil_EndianSwap16
-# define Xil_Htonl	Xil_EndianSwap32
-# define Xil_Ntohs	Xil_EndianSwap16
-# define Xil_Ntohl	Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
-	u16 value = Xil_In16(Addr);
-	return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
-	u32 value = Xil_In32(Addr);
-	return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
-	Value = Xil_EndianSwap16(Value);
-	Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
-	Value = Xil_EndianSwap32(Value);
-	Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_mem.h

@@ -1,68 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (C) 2015 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1   nsk      11/07/16 First release.
-* 7.0   mus      01/07/19 Add cpp extern macro
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H		/* prevent circular inclusions */
-#define XIL_MEM_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h

@@ -1,273 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register defintions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc   03/07/13 First release.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H		/* prevent circular inclusions */
-#define XIL_MISC_RESET_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-#define XDDRC_CTRL_BASEADDR				0xF8006000U
-#define XSLCR_BASEADDR					0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR				(XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR			(XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR			(XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET			0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET		0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET		0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET				0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET				0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET				0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE		0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 	0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 	0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 	0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 	0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 		0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL		0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK	0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK		0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL	0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL	0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL		0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL		0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL		0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL		0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL	0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL	0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL		0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL		0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL			0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL			0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL			0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL			0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL			0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL			0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL			0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL			0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL			0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL			0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL			0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL			0x00000003U
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */

df_datalink/bsp/ps7_cortexa9_0/include/xil_mmu.h

@@ -1,106 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm  01/12/12 Initial version
-* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
-*					  u32 which resolves issue of CR#805869
-* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 	/* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02	/* Strongly ordered */
-#define DEVICE_MEMORY 0xC06		/* Device memory */
-#define RESERVED 0x0			/* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE	(~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a9_mmu_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_printf.h

@@ -1,48 +0,0 @@
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <ctype.h>
-#include <string.h>
-#include <stdarg.h>
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to   */
-/* make xil_printf re-entrant.                        */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the  */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and   */
-/* that is unacceptable in most embedded systems.    */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/*                                                   */
-
-void xil_printf( const char8 *ctrl1, ...);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xil_sleeptimer.h

@@ -1,128 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2017 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver   Who  Date	 Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6	srm  10/18/17 First Release.
-* 7.0   mus  01/07/19 Add cpp extern macro
-*
-* </pre>
-*****************************************************************************/
-
-#ifndef XIL_SLEEPTIMER_H		/* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/****************************  Include Files  ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT  32U
-#define XSleep_ReadCounterVal   Xil_In32
-#define XCntrVal 			    u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT  16U
-#define XSleep_ReadCounterVal   Xil_In16
-#define XCntrVal 			    u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#if defined (versal)
-#define CRL_TTC_RST    0xFF5E0344U
-#define CRL_TTC_BASE_RST_MASK    0x1U
-#else
-#define RST_LPD_IOU2 					    0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 	0x00000800U
-#endif
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET		0x00000000U
-					     /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET		0x0000000CU
-	                                     /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET	0x00000018U
-					     /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK		0x00000001U
-						   /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK		0x00000001U
-						/**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK		0x00000010U
-						  /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_SLEEPTIMER_H */

df_datalink/bsp/ps7_cortexa9_0/include/xil_testcache.h

@@ -1,67 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* @addtogroup common_test_utils
-* <h2>Cache test </h2>
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-* <pre>
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm  07/29/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
-#define XIL_TESTCACHE_H	/* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_testio.h

@@ -1,90 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities
-* <h2>I/O test </h2>
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm  08/05/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
-#define XIL_TESTIO_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 	0
-#define XIL_TESTIO_LE		1
-#define XIL_TESTIO_BE		2
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_testmem.h

@@ -1,154 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils
-*
-* <h2>Memory test</h2>
-*
-* The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-* Following list describes the supported memory tests:
-*
-*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-*  - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-*          location 1 = 0x00000001
-*          location 2 = 0x00000002
-*          ...
-* @endcode
-*
-*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-*       location 1 = 0xFFFFFFFE
-*       location 2 = 0xFFFFFFFD
-*       ...
-*@endcode
-*
-*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver    Who    Date    Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm  08/25/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
-#define XIL_TESTMEM_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE	1U
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS     0x00U
-#define XIL_TESTMEM_INCREMENT       0x01U
-#define XIL_TESTMEM_WALKONES        0x02U
-#define XIL_TESTMEM_WALKZEROS       0x03U
-#define XIL_TESTMEM_INVERSEADDR     0x04U
-#define XIL_TESTMEM_FIXEDPATTERN    0x05U
-#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-
-extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_types.h

@@ -1,214 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm  07/14/09 First release
-* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
-*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
-*		      Define LONG and ULONG datatypes and mask values
-* 7.00  mus  01/07/19 Add cpp extern macro
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TYPES_H	/* prevent circular inclusions */
-#define XIL_TYPES_H	/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stddef.h>
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#  define TRUE		1U
-#endif
-
-#ifndef FALSE
-#  define FALSE		0U
-#endif
-
-#ifndef NULL
-#define NULL		0U
-#endif
-
-#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
-                                                 assigend to "IsReady" member of driver
-												 instance to indicate that driver
-												 instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
-                                                 "IsStarted" member of driver instance
-												 to indicate that driver instance is
-												 started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
-	u32 Upper;
-	u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief    Return the most significant half of the 64 bit data type.
-*
-* @param    x is the 64 bit word.
-*
-* @return   The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief    Return the least significant half of the 64 bit data type.
-*
-* @param    x is the 64 bit word.
-*
-* @return   The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK	~ULONG64_HI_MASK
-
-#else
-#include <linux/types.h>
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief  Returns 32-63 bits of a number.
- * @param  n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note    A basic shift-right of a 64- or 32-bit quantity.
- *          Use this to suppress the "right shift count >= width of type"
- *          warning when that quantity is 32-bits.
- */
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-
-/**
- * @brief  Returns 0-31 bits of a number
- * @param  n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE		1U
-#endif
-
-#ifndef FALSE
-#define FALSE		0U
-#endif
-
-#ifndef NULL
-#define NULL		0U
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/**
-* @} End of "addtogroup common_types".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xil_util.h

@@ -1,57 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (C) 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* @file xil_util.h
-*
-* This file contains xil utility functions declaration
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4   mmd      04/21/19 First release.
-*
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Conver input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-#endif	/* XIL_UTIL_H_ */

df_datalink/bsp/ps7_cortexa9_0/include/xl2cc.h

@@ -1,168 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm  02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-*		      'xil_errata.h' for errata description
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET		0x0000U
-#define XPS_L2CC_TYPE_OFFSET		0x0004U
-#define XPS_L2CC_CNTRL_OFFSET		0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET	0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET	0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET	0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET	0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET	0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET	0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET	0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET	0x0210U
-
-#define XPS_L2CC_IER_OFFSET		0x0214U		/* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET		0x0218U		/* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET		0x021CU		/* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET		0x0220U		/* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET		0x0730U		/* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET	0x0740U		/* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET		0x0770U		/* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET		0x077CU		/* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET		0x07B0U		/* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET	0x07B8U		/* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET		0x07BCU		/* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET	0x07F0U		/* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET	0x07F8U		/* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET	0x07FCU		/* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET	0x0900U		/* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET	0x0904U		/* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET	0x0908U		/* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET	0x090CU		/* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET	0x0910U		/* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET	0x0914U		/* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET	0x0918U		/* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET	0x091CU		/* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET	0x0920U		/* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET	0x0924U		/* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET	0x0928U		/* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET	0x092CU		/* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET	0x0930U		/* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET	0x0934U		/* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET	0x0938U		/* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET	0x093CU		/* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U		/* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET	0x0954U		/* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET	0x0C00U		/* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET		0x0C04U		/* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET		0x0F40U		/* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK		0x00000001U	/* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK	0x40000000U	/* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK		0x20000000U	/* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK		0x10000000U	/* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK		0x08000000U	/* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK		0x04000000U	/* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK		0x02000000U	/* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK		0x01800000U	/* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK		0x00400000U	/* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK		0x00200000U	/* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK		0x00100000U	/* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK	0x000E0000U	/* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK		0x00010000U	/* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK		0x00002000U	/* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK	0x00001000U	/* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK		0x00000800U	/* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK	0x00000400U	/* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK		0x00000001U	/* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK	0x72360000U	/* Enable all prefetching, */
-                                                    /* Cache replacement policy, Parity enable, */
-                                                    /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK	0xFFF1FFFFU	/* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK	0x00000111U	/* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK	0x00000121U	/* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK	0x00000100U	/* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK	0x00000080U	/* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK		0x00000040U	/* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK		0x00000020U	/* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK		0x00000010U	/* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK		0x00000008U	/* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK		0x00000004U	/* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK		0x00000002U	/* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK		0x00000001U	/* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK	0xFFF00000U	/* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U	/* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK	0x00000004U	/* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK		0x00000002U	/* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK		0x00000002U	/* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xl2cc_counter.h

@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm  07/11/11 First release
-* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
-*		      inside the APIs
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
-#define L2CCCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants define the event codes for the event counters.
- */
-#define XL2CC_CO		0x1
-#define XL2CC_DRHIT		0x2
-#define XL2CC_DRREQ		0x3
-#define XL2CC_DWHIT		0x4
-#define XL2CC_DWREQ		0x5
-#define XL2CC_DWTREQ		0x6
-#define XL2CC_IRHIT		0x7
-#define XL2CC_IRREQ		0x8
-#define XL2CC_WA		0x9
-#define XL2CC_IPFALLOC		0xa
-#define XL2CC_EPFHIT		0xb
-#define XL2CC_EPFALLOC		0xc
-#define XL2CC_SRRCVD		0xd
-#define XL2CC_SRCONF		0xe
-#define XL2CC_EPFRCVD		0xf
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
-void XL2cc_EventCtrStart(void);
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* L2CCCOUNTER_H */
-/**
-* @} End of "addtogroup l2_event_counter_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xparameters.h

@@ -1,470 +0,0 @@
-#ifndef XPARAMETERS_H   /* prevent circular inclusions */
-#define XPARAMETERS_H   /* by using protection macros */
-
-/* Definition for CPU ID */
-#define XPAR_CPU_ID 0U
-
-/* Definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-
-/* Definitions for interface PHY */
-#define XPAR_PHY_BASEADDR 0x43C20000
-#define XPAR_PHY_HIGHADDR 0x43C20FFF
-
-#include "xparameters_ps.h"
-
-#define STDIN_BASEADDRESS 0xE0000000
-#define STDOUT_BASEADDRESS 0xE0000000
-
-/******************************************************************/
-
-/* Platform specific definitions */
-#define PLATFORM_ZYNQ
- 
-/* Definitions for sleep timer configuration */
-#define XSLEEP_TIMER_IS_DEFAULT_TIMER
- 
- 
-/******************************************************************/
-/* Definitions for driver BRAM */
-#define XPAR_XBRAM_NUM_INSTANCES 3U
-
-/* Definitions for peripheral PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL */
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_DEVICE_ID 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_DATA_WIDTH 32U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_ECC 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_FAULT_INJECT 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_WRITE_ACCESS 0U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_S_AXI_BASEADDR 0x44000000U
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0x44001FFFU
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
-#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
-
-
-/* Definitions for peripheral PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL */
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_DEVICE_ID 1U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_DATA_WIDTH 32U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_ECC 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_FAULT_INJECT 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_WRITE_ACCESS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_S_AXI_BASEADDR 0x40000000U
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0x40000FFFU
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
-#define XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
-
-
-/* Definitions for peripheral PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL */
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_DEVICE_ID 2U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_DATA_WIDTH 32U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_ECC 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_FAULT_INJECT 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_WRITE_ACCESS 0U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_S_AXI_BASEADDR 0x42000000U
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0x42000FFFU
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
-#define XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL */
-#define XPAR_BRAM_0_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_AXI_BRAM_CTRL_DEVICE_ID
-#define XPAR_BRAM_0_DATA_WIDTH 32U
-#define XPAR_BRAM_0_ECC 0U
-#define XPAR_BRAM_0_FAULT_INJECT 0U
-#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0U
-#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0U
-#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0U
-#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0U
-#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
-#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
-#define XPAR_BRAM_0_WRITE_ACCESS 0U
-#define XPAR_BRAM_0_BASEADDR 0x44000000U
-#define XPAR_BRAM_0_HIGHADDR 0x44001FFFU
-#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU  
-#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU  
-
-/* Canonical definitions for peripheral PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL */
-#define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_PHY_RX_BUFF_AXI_BRAM_CTRL_DEVICE_ID
-#define XPAR_BRAM_1_DATA_WIDTH 32U
-#define XPAR_BRAM_1_ECC 0U
-#define XPAR_BRAM_1_FAULT_INJECT 0U
-#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0U
-#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0U
-#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0U
-#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0U
-#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
-#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
-#define XPAR_BRAM_1_WRITE_ACCESS 0U
-#define XPAR_BRAM_1_BASEADDR 0x40000000U
-#define XPAR_BRAM_1_HIGHADDR 0x40000FFFU
-#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU  
-#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU  
-
-/* Canonical definitions for peripheral PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL */
-#define XPAR_BRAM_2_DEVICE_ID XPAR_PHY_DATA_INTERFACE_PHY_TX_BUFF_AXI_BRAM_CTRL_DEVICE_ID
-#define XPAR_BRAM_2_DATA_WIDTH 32U
-#define XPAR_BRAM_2_ECC 0U
-#define XPAR_BRAM_2_FAULT_INJECT 0U
-#define XPAR_BRAM_2_CE_FAILING_REGISTERS 0U
-#define XPAR_BRAM_2_UE_FAILING_REGISTERS 0U
-#define XPAR_BRAM_2_ECC_STATUS_REGISTERS 0U
-#define XPAR_BRAM_2_CE_COUNTER_WIDTH 0U
-#define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
-#define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
-#define XPAR_BRAM_2_WRITE_ACCESS 0U
-#define XPAR_BRAM_2_BASEADDR 0x42000000U
-#define XPAR_BRAM_2_HIGHADDR 0x42000FFFU
-#define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU  
-#define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU  
-
-
-/******************************************************************/
-
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver DEVCFG */
-#define XPAR_XDCFG_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
-#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
-#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
-#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
-#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Definitions for driver DMAPS */
-#define XPAR_XDMAPS_NUM_INSTANCES 2
-
-/* Definitions for peripheral PS7_DMA_NS */
-#define XPAR_PS7_DMA_NS_DEVICE_ID 0
-#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
-#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
-
-
-/* Definitions for peripheral PS7_DMA_S */
-#define XPAR_PS7_DMA_S_DEVICE_ID 1
-#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
-#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DMA_NS */
-#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
-#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
-#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
-
-/* Canonical definitions for peripheral PS7_DMA_S */
-#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
-#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
-#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-
-/* Definitions for peripheral AXI_SPI_ENGINE_AXI_SPI_ENGINE */
-#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR 0x43C00000
-#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_HIGHADDR 0x43C0FFFF
-
-
-/* Definitions for peripheral PS7_AFI_0 */
-#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
-#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
-
-
-/* Definitions for peripheral PS7_AFI_1 */
-#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
-#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
-
-
-/* Definitions for peripheral PS7_AFI_2 */
-#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
-#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
-
-
-/* Definitions for peripheral PS7_AFI_3 */
-#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
-#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
-
-
-/* Definitions for peripheral PS7_DDRC_0 */
-#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
-#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
-
-
-/* Definitions for peripheral PS7_GLOBALTIMER_0 */
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
-
-
-/* Definitions for peripheral PS7_GPV_0 */
-#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
-#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
-
-
-/* Definitions for peripheral PS7_INTC_DIST_0 */
-#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
-#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
-
-
-/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
-
-
-/* Definitions for peripheral PS7_L2CACHEC_0 */
-#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Definitions for peripheral PS7_OCMC_0 */
-#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
-#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
-
-
-/* Definitions for peripheral PS7_PL310_0 */
-#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Definitions for peripheral PS7_PMU_0 */
-#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
-#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
-
-
-/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
-
-
-/* Definitions for peripheral PS7_RAM_0 */
-#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
-
-
-/* Definitions for peripheral PS7_RAM_1 */
-#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
-#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
-/* Definitions for peripheral PS7_SCUC_0 */
-#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
-#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
-
-
-/* Definitions for peripheral PS7_SLCR_0 */
-#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
-#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
-
-
-/* Definitions for peripheral SYSTEMBUS */
-#define XPAR_SYSTEMBUS_BASEADDR 0x43C10000
-#define XPAR_SYSTEMBUS_HIGHADDR 0x43C11FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIOPS */
-#define XPAR_XGPIOPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_GPIO_0 */
-#define XPAR_PS7_GPIO_0_DEVICE_ID 0
-#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
-#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_GPIO_0 */
-#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
-#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
-#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver QSPIPS */
-#define XPAR_XQSPIPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_QSPI_0 */
-#define XPAR_PS7_QSPI_0_DEVICE_ID 0
-#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
-#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
-#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_PS7_QSPI_0_QSPI_MODE 0
-#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_QSPI_0 */
-#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
-#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
-#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
-#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_XQSPIPS_0_QSPI_MODE 0
-#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Definitions for Fabric interrupts connected to ps7_scugic_0 */
-#define XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR 62U
-#define XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR 63U
-#define XPAR_FABRIC_PHY_IRQ_INTR 64U
-
-/******************************************************************/
-
-/* Canonical definitions for Fabric interrupts connected to ps7_scugic_0 */
-
-/******************************************************************/
-
-/* Definitions for driver SCUGIC */
-#define XPAR_XSCUGIC_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
-#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
-#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUTIMER */
-#define XPAR_XSCUTIMER_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
-#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
-#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUWDT */
-#define XPAR_XSCUWDT_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
-#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
-#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Definitions for driver UARTPS */
-#define XPAR_XUARTPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_UART_0 */
-#define XPAR_PS7_UART_0_DEVICE_ID 0
-#define XPAR_PS7_UART_0_BASEADDR 0xE0000000
-#define XPAR_PS7_UART_0_HIGHADDR 0xE0000FFF
-#define XPAR_PS7_UART_0_UART_CLK_FREQ_HZ 100000000
-#define XPAR_PS7_UART_0_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_UART_0 */
-#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_0_DEVICE_ID
-#define XPAR_XUARTPS_0_BASEADDR 0xE0000000
-#define XPAR_XUARTPS_0_HIGHADDR 0xE0000FFF
-#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
-#define XPAR_XUARTPS_0_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Definitions for driver XADCPS */
-#define XPAR_XADCPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_XADC_0 */
-#define XPAR_PS7_XADC_0_DEVICE_ID 0
-#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
-#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_XADC_0 */
-#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
-#define XPAR_XADCPS_0_BASEADDR 0xF8007100
-#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-#endif  /* end of protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xparameters_ps.h

@@ -1,334 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
-*                        driver tcl
-* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6   srm     10/18/17 Added ARMA9 macro to identify CortexA9
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XPARAMETERS_PS_H_
-#define _XPARAMETERS_PS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/****************************  Include Files  *******************************/
-
-
-/************************** Constant Definitions *****************************/
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock
- */
-
-/* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR		0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
-
-/* Canonical definitions for Interrupts  */
-#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
-#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
-#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
-#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
-#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
-#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
-
-
-#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
-#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
-
-
-
-/* Canonical definitions for DMAC */
-
-
-/* Canonical definitions for WDT */
-
-/* Canonical definitions for SLCR */
-#define XPAR_XSLCR_NUM_INSTANCES	1U
-#define XPAR_XSLCR_0_DEVICE_ID		0U
-#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
-
-/* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES	1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
-#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
-#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_ACK_BEFORE		0U
-
-/* Canonical definitions for Global Timer */
-#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
-#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
-#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
-#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
-
-
-/* Xilinx Parallel Flash Library (XilFlash) User Settings */
-#define XPAR_AXI_EMC
-
-
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock. These have been put for bacwards compatibilty
- */
-
-#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
-#define XPS_UART0_BASEADDR		0xE0000000U
-#define XPS_UART1_BASEADDR		0xE0001000U
-#define XPS_USB0_BASEADDR		0xE0002000U
-#define XPS_USB1_BASEADDR		0xE0003000U
-#define XPS_I2C0_BASEADDR		0xE0004000U
-#define XPS_I2C1_BASEADDR		0xE0005000U
-#define XPS_SPI0_BASEADDR		0xE0006000U
-#define XPS_SPI1_BASEADDR		0xE0007000U
-#define XPS_CAN0_BASEADDR		0xE0008000U
-#define XPS_CAN1_BASEADDR		0xE0009000U
-#define XPS_GPIO_BASEADDR		0xE000A000U
-#define XPS_GEM0_BASEADDR		0xE000B000U
-#define XPS_GEM1_BASEADDR		0xE000C000U
-#define XPS_QSPI_BASEADDR		0xE000D000U
-#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
-#define XPS_SDIO0_BASEADDR		0xE0100000U
-#define XPS_SDIO1_BASEADDR		0xE0101000U
-#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
-#define XPS_NAND_BASEADDR		0xE1000000U
-#define XPS_PARPORT0_BASEADDR		0xE2000000U
-#define XPS_PARPORT1_BASEADDR		0xE4000000U
-#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
-#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
-#define XPS_TTC0_BASEADDR		0xF8001000U
-#define XPS_TTC1_BASEADDR		0xF8002000U
-#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
-#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
-#define XPS_WDT_BASEADDR		0xF8005000U
-#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
-#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
-#define XPS_AFI0_BASEADDR		0xF8008000U
-#define XPS_AFI1_BASEADDR		0xF8009000U
-#define XPS_AFI2_BASEADDR		0xF800A000U
-#define XPS_AFI3_BASEADDR		0xF800B000U
-#define XPS_OCM_BASEADDR		0xF800C000U
-#define XPS_EFUSE_BASEADDR		0xF800D000U
-#define XPS_CORESIGHT_BASEADDR		0xF8800000U
-#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
-#define XPS_SCU_PERIPH_BASE		0xF8F00000U
-#define XPS_L2CC_BASEADDR		0xF8F02000U
-#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
-#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
-#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
-#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
-#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
-
-/* Shared Peripheral Interrupts (SPI) */
-#define XPS_CORE_PARITY0_INT_ID		32U
-#define XPS_CORE_PARITY1_INT_ID		33U
-#define XPS_L2CC_INT_ID			34U
-#define XPS_OCMINTR_INT_ID		35U
-#define XPS_ECC_INT_ID			36U
-#define XPS_PMU0_INT_ID			37U
-#define XPS_PMU1_INT_ID			38U
-#define XPS_SYSMON_INT_ID		39U
-#define XPS_DVC_INT_ID			40U
-#define XPS_WDT_INT_ID			41U
-#define XPS_TTC0_0_INT_ID		42U
-#define XPS_TTC0_1_INT_ID		43U
-#define XPS_TTC0_2_INT_ID 		44U
-#define XPS_DMA0_ABORT_INT_ID		45U
-#define XPS_DMA0_INT_ID			46U
-#define XPS_DMA1_INT_ID			47U
-#define XPS_DMA2_INT_ID			48U
-#define XPS_DMA3_INT_ID			49U
-#define XPS_SMC_INT_ID			50U
-#define XPS_QSPI_INT_ID			51U
-#define XPS_GPIO_INT_ID			52U
-#define XPS_USB0_INT_ID			53U
-#define XPS_GEM0_INT_ID			54U
-#define XPS_GEM0_WAKE_INT_ID		55U
-#define XPS_SDIO0_INT_ID		56U
-#define XPS_I2C0_INT_ID			57U
-#define XPS_SPI0_INT_ID			58U
-#define XPS_UART0_INT_ID		59U
-#define XPS_CAN0_INT_ID			60U
-#define XPS_FPGA0_INT_ID		61U
-#define XPS_FPGA1_INT_ID		62U
-#define XPS_FPGA2_INT_ID		63U
-#define XPS_FPGA3_INT_ID		64U
-#define XPS_FPGA4_INT_ID		65U
-#define XPS_FPGA5_INT_ID		66U
-#define XPS_FPGA6_INT_ID		67U
-#define XPS_FPGA7_INT_ID		68U
-#define XPS_TTC1_0_INT_ID		69U
-#define XPS_TTC1_1_INT_ID		70U
-#define XPS_TTC1_2_INT_ID		71U
-#define XPS_DMA4_INT_ID			72U
-#define XPS_DMA5_INT_ID			73U
-#define XPS_DMA6_INT_ID			74U
-#define XPS_DMA7_INT_ID			75U
-#define XPS_USB1_INT_ID			76U
-#define XPS_GEM1_INT_ID			77U
-#define XPS_GEM1_WAKE_INT_ID		78U
-#define XPS_SDIO1_INT_ID		79U
-#define XPS_I2C1_INT_ID			80U
-#define XPS_SPI1_INT_ID			81U
-#define XPS_UART1_INT_ID		82U
-#define XPS_CAN1_INT_ID			83U
-#define XPS_FPGA8_INT_ID		84U
-#define XPS_FPGA9_INT_ID		85U
-#define XPS_FPGA10_INT_ID		86U
-#define XPS_FPGA11_INT_ID		87U
-#define XPS_FPGA12_INT_ID		88U
-#define XPS_FPGA13_INT_ID		89U
-#define XPS_FPGA14_INT_ID		90U
-#define XPS_FPGA15_INT_ID		91U
-
-/* Private Peripheral Interrupts (PPI) */
-#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
-#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
-#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
-#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
-#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
-
-
-/* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
-#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
-#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
-#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
-#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
-#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
-#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
-
-#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
-
-/* For backwards compatibilty */
-#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
-
-#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
-
-#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-#endif
-
-#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
-#endif
-
-#define XPAR_SCUTIMER_DEVICE_ID		0U
-#define XPAR_SCUWDT_DEVICE_ID		0U
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */

df_datalink/bsp/ps7_cortexa9_0/include/xplatform_info.h

@@ -1,120 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2017 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date    Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-*                      function for PMUFW.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
-#define XPLATFORM_INFO_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal)
-#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
-#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
-									XPAR_PMC_TAP_VERSION_OFFSET)
-#else
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define	XPAR_CSU_VER_OFFSET 0x00000044U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
-									XPAR_CSU_VER_OFFSET)
-#endif
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-#define XPLAT_versal 0x6U
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-#define XPLAT_INFO_MASK (0xF)
-
-#if defined (versal)
-#define XPS_VERSION_INFO_MASK 0xFF00U
-#define XPS_VERSION_INFO_SHIFT 0x8U
-#define XPLAT_INFO_SHIFT 0x18U
-#else
-#define XPS_VERSION_INFO_MASK (0xF)
-#define XPS_VERSION_INFO_SHIFT 0x0U
-#define XPLAT_INFO_SHIFT 0xCU
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info(void);
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
-u32 XGetPSVersion_Info();
-#endif
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info();
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xpm_counter.h

@@ -1,572 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm  07/11/11 First release
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include <stdint.h>
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- *    - b00 no instructions renamed
- *    - b01 one instruction renamed
- *    - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config		PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
- *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
- *			  XPM_EVENT_INSTRFECT_TLBREFILL,
- *			  XPM_EVENT_DATA_CACHEREFILL,
- *			  XPM_EVENT_DATA_CACHEACCESS,
- *			  XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
- *			  XPM_EVENT_DATA_WRITE,
- *			  XPM_EVENT_EXCEPTION,
- *			  XPM_EVENT_EXCEPRETURN,
- *			  XPM_EVENT_CHANGECONTEXT,
- *			  XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
- *			  XPM_EVENT_UNALIGNEDACCESS,
- *			  XPM_EVENT_BRANCHMISS,
- *			  XPM_EVENT_CLOCKCYCLES,
- *			  XPM_EVENT_BRANCHPREDICT,
- *			  XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
- *			  XPM_EVENT_JAVABACKBRANCH,
- *			  XPM_EVENT_COHERLINEMISS,
- *			  XPM_EVENT_COHERLINEHIT,
- *			  XPM_EVENT_INSTRSTALL,
- *			  XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
- *			  XPM_EVENT_STREXPASS,
- *			  XPM_EVENT_STREXFAIL,
- *			  XPM_EVENT_DATAEVICT,
- *			  XPM_EVENT_NODISPATCH,
- *			  XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
- *			  XPM_EVENT_PREDICTFUNCRET,
- *			  XPM_EVENT_MAINEXEC,
- *			  XPM_EVENT_SECEXEC,
- *			  XPM_EVENT_LDRSTR,
- *			  XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
- *			  XPM_EVENT_PLDSTALL,
- *			  XPM_EVENT_WRITESTALL,
- *			  XPM_EVENT_INSTRTLBSTALL,
- *			  XPM_EVENT_DATATLBSTALL,
- *			  XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
- *			  XPM_EVENT_DMB_STALL,
- *			  XPM_EVENT_INT_CLKEN,
- *			  XPM_EVENT_DE_CLKEN,
- *			  XPM_EVENT_INSTRISB,
- *			  XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
- *			  XPM_EVENT_EXTINT,
- *			  XPM_EVENT_PLE_LRC,
- *			  XPM_EVENT_PLE_LRS,
- *			  XPM_EVENT_PLE_FLUSH,
- *			  XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
- *			  XPM_EVENT_PLE_PROG,
- *			  XPM_EVENT_PLE_LRC,
- *			  XPM_EVENT_PLE_LRS,
- *			  XPM_EVENT_PLE_FLUSH,
- *			  XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
- *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
- *			  XPM_EVENT_INSTRFECT_TLBREFILL,
- *			  XPM_EVENT_DATA_CACHEREFILL,
- *			  XPM_EVENT_DATA_CACHEACCESS,
- *			  XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1	0
-#define XPM_CNTRCFG2	1
-#define XPM_CNTRCFG3	2
-#define XPM_CNTRCFG4	3
-#define XPM_CNTRCFG5	4
-#define XPM_CNTRCFG6	5
-#define XPM_CNTRCFG7	6
-#define XPM_CNTRCFG8	7
-#define XPM_CNTRCFG9	8
-#define XPM_CNTRCFG10	9
-#define XPM_CNTRCFG11	10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface fuctions to access perfromance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xpseudo_asm.h

@@ -1,82 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm  10/18/09 First release
-* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h

@@ -1,252 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp		 05/21/14 First release
-* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
-#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/* necessary for pre-processor */
-#define stringify(s)	tostring(s)
-#define tostring(s)	#s
-
-#if defined (__aarch64__)
-/* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval = 0U; \
-			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
-			  rval;\
-			 })
-
-#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
-
-#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
-#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
-
-#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
-#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
-
-
-
-#define mtgpr(rn, v)	/*__asm__ __volatile__(\
-			  "mov r" stringify(rn) ", %0 \n"\
-			  : : "r" (v)\
-			)*/
-
-#define mfgpr(rn)	/*({u32 rval; \
-			  __asm__ __volatile__(\
-			    "mov %0,r" stringify(rn) "\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })*/
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb sy")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__("dsb sy")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__("dmb sy")
-
-
-/* Memory Operations */
-#define ldr(adr)	({u64 rval; \
-			  __asm__ __volatile__(\
-			    "ldr	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
-
-#define mfelrel3() ({u64 rval = 0U; \
-                   asm volatile("mrs %0,  ELR_EL3" : "=r" (rval));\
-                  rval;\
-                 })
-
-#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
-
-#else
-
-/* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval = 0U; \
-			  __asm__ __volatile__(\
-			    "mrs	%0, cpsr\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })
-
-#define mtcpsr(v)	__asm__ __volatile__(\
-			  "msr	cpsr,%0\n"\
-			  : : "r" (v)\
-			)
-
-#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
-#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
-
-#define cpsief()	__asm__ __volatile__("cpsie	f\n")
-#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
-
-
-
-#define mtgpr(rn, v)	__asm__ __volatile__(\
-			  "mov r" stringify(rn) ", %0 \n"\
-			  : : "r" (v)\
-			)
-
-#define mfgpr(rn)	({u32 rval; \
-			  __asm__ __volatile__(\
-			    "mov %0,r" stringify(rn) "\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
-
-
-/* Memory Operations */
-#define ldr(adr)	({u32 rval; \
-			  __asm__ __volatile__(\
-			    "ldr	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
-
-#endif
-
-#define ldrb(adr)	({u8 rval; \
-			  __asm__ __volatile__(\
-			    "ldrb	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
-
-#define str(adr, val)	__asm__ __volatile__(\
-			  "str	%0,[%1]\n"\
-			  : : "r" (val), "r" (adr)\
-			)
-
-#define strb(adr, val)	__asm__ __volatile__(\
-			  "strb	%0,[%1]\n"\
-			  : : "r" (val), "r" (adr)\
-			)
-
-/* Count leading zeroes (clz) */
-#define clz(arg)	({u8 rval; \
-			  __asm__ __volatile__(\
-			    "clz	%0,%1"\
-			    : "=r" (rval) : "r" (arg)\
-			  );\
-			  rval;\
-			 })
-
-#if defined (__aarch64__)
-#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
-#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
-
-#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
-#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
-#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
-/* CP15 operations */
-#define mfcp(reg)	({u64 rval = 0U;\
-			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
-			rval;\
-			})
-
-#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
-
-#else
-/* CP15 operations */
-#define mtcp(rn, v)	__asm__ __volatile__(\
-			 "mcr " rn "\n"\
-			 : : "r" (v)\
-			);
-
-#define mfcp(rn)	({u32 rval = 0U; \
-			 __asm__ __volatile__(\
-			   "mrc " rn "\n"\
-			   : "=r" (rval)\
-			 );\
-			 rval;\
-			 })
-#endif
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XPSEUDO_ASM_GCC_H */

df_datalink/bsp/ps7_cortexa9_0/include/xqspips.h

@@ -1,804 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_6
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* <b> Linear Mode </b>
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device.  The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-*	- XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-*	  static configuration structure defined in xqspips_g.c. This is setup
-*	  by the tools. For some operating systems the config structure will be
-*	  initialized by the software and this call is not needed.
-*	- XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-*	  configuration structure provided by the caller. If running in a system
-*	  with address translation, the provided virtual memory base address
-*	  replaces the physical address present in the configuration structure.
-*
-* <b>Multiple Masters</b>
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* <b>Modes of Operation</b>
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-*	     is written into the TXFIFO and de asserted when the TXFIFO becomes
-*	     empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-*		TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-*		  the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-*   TXFIFO write otherwise there could be a race condition where the TXFIFO
-*   becomes empty before the new word is written. In that case the
-*   transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-*   This results in a single transaction to be split into multiple pieces each
-*   with its own chip select. This will result in garbage data to be sent.
-*
-* <b>Interrupts</b>
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data.  The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* <b>Polled Operation</b>
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* <b>Device Busy</b>
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* <b>Device Configuration</b>
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent.  It works with
-* physical addresses only.  Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianess set to little-endian.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-*		     in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* 		     Removed code related to mode fault for CR 671468
-*		     The XQspiPs_SetSlaveSelect has been modified to remove
-*		     the argument of the slave select as the QSPI controller
-*		     only supports one slave.
-* 		     XQspiPs_GetSlaveSelect API has been removed
-* 		     Added a flag ShiftReadData to the instance structure
-*.		     and is used in the XQspiPs_GetReadData API.
-*		     The ShiftReadData Flag indicates whether the data
-*		     read from the Rx FIFO needs to be shifted
-*		     in cases where the data is less than 4  bytes
-* 		     Removed the selection for the following options:
-*		     Master mode (XQSPIPS_MASTER_OPTION) and
-*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-*		     as the QSPI driver supports the Master mode
-*		     and Flash Interface mode and doesnot support
-*		     Slave mode or the legacy mode.
-*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-*		     APIs so that the last argument (IsInst) specifying whether
-*		     it is instruction or data has been removed. The first byte
-*		     in the SendBufPtr argument of these APIs specify the
-*		     instruction to be sent to the Flash Device.
-*		     This version of the driver fixes CRs 670197/663787/
-*		     670297/671468.
-* 		     Added the option for setting the Holdb_dr bit in the
-*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-*		     is the option to be used for setting this bit in the
-*		     configuration register.
-*		     The XQspiPs_PolledTransfer function has been updated
-*		     to fill the data to fifo depth.
-* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-*		     Added macros for Set/Get Rx Watermark. Changed QSPI
-*		     Enable/Disable macro argument from BaseAddress to
-*		     Instance Pointer. Added DelayNss argument to SetDelays
-*		     and GetDelays API's.
-*		     Created macros XQspiPs_IsManualStart and
-*		     XQspiPs_IsManualChipSelect.
-*		     Changed QSPI transfer logic for polled and interrupt
-*		     modes to be based on filled tx fifo count and receive
-*		     based on it. RXNEMPTY interrupt is not used.
-*		     Added assertions to XQspiPs_LqspiRead function.
-*		     SetDelays and GetDelays API's include DelayNss parameter.
-*		     Added defines for DelayNss,Rx Watermark,Interrupts
-*		     which need write to clear. Removed Read zeros mask from
-*		     LQSPI Config register. Renamed Fixed burst error to
-*		     data FSM error in  LQSPI Status register.
-*
-* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
-*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-*			 Added enable and disable to the XQspiPs_LqspiRead() function
-*			 Removed XQspi_Reset() in Set_Options() function when
-*			 LQSPI_MODE_OPTION is set.
-*            Added instructions for bank selection, die erase and
-*            flag status register to the flash instruction table
-*            Handling for instructions not in flash instruction
-*			 table added. Checking for Tx FIFO empty when switching from
-*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-*            byte count 3 (spansion), instruction size and TXD register
-*			 changed accordingly. CR# 712502 and 703869.
-*            Added prefix to constant definitions for ConnectionMode
-*            Added (#ifdef linear base address) in the Linear read function.
-*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-*            XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
-*                    thresholds. This is to improve performance.
-*                    Added API's for QSPI reset and
-*                    linear mode initialization for boot.
-*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
-*                    Added RX threshold reset(1) after transfer in polled and
-*                    interrupt transfers. Made changes to make sure threshold
-*                    change is done only when no transfer is in progress.
-*                    Updated linear init API for parallel and stacked modes.
-*                    CR#737760.
-* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
-*                    required bits leaving reserved bits untouched. CR# 796813.
-* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
-* 					 controller does not update FIFO status flags as expected
-* 					 when thresholds are used.
-* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
-*                    to remove compilation warnings. CR# 868893.
-*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
-*                    generation.
-*       ms  04/05/17 Modified Comment lines in functions of qspips
-*                    examples to recognize it as documentation block
-*                    and modified filename tag in
-*                    xqspips_dual_flash_stack_lqspi_example.c to include it in
-*                    doxygen examples.
-* 3.4   nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-* 3.5	tjs 08/21/18 Fixed compilation warnings for the ARMCC.
-* 3.5	tjs 07/16/18 Added support for low density ISSI flash parts.
-* 3.6   akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6   akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
-*                    to wait for the on going operation to complete before
-*                    performing the next operation.
-* 3.6   akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-*                    configuration register values of both the Flashes in dual
-*                    parellel connection.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPS_H		/* prevent circular inclusions */
-#define XQSPIPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include <string.h>
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device.  Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The <b>Active Low Clock option</b> configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The <b>Clock Phase option</b> configures the QSPI device for one of two
- * transfer formats.  A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The <b>Manual Start option</b> is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION	0x2  /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION	0x4  /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION	0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION	0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION	0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION	0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2		0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4		0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8		0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16		0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32		0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64		0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128	0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256	0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver.  These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE	2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN	4 /**< Receive data loss because
-					    *  RX FIFO full
-					    */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define	XQSPIPS_FLASH_OPCODE_WRSR	0x01 /* Write status register */
-#define	XQSPIPS_FLASH_OPCODE_PP		0x02 /* Page program */
-#define	XQSPIPS_FLASH_OPCODE_NORM_READ	0x03 /* Normal read data bytes */
-#define	XQSPIPS_FLASH_OPCODE_WRDS	0x04 /* Write disable */
-#define	XQSPIPS_FLASH_OPCODE_RDSR1	0x05 /* Read status register 1 */
-#define	XQSPIPS_FLASH_OPCODE_WREN	0x06 /* Write enable */
-#define	XQSPIPS_FLASH_OPCODE_FAST_READ	0x0B /* Fast read data bytes */
-#define	XQSPIPS_FLASH_OPCODE_BE_4K	0x20 /* Erase 4KiB block */
-#define	XQSPIPS_FLASH_OPCODE_RDSR2	0x35 /* Read status register 2 */
-#define	XQSPIPS_FLASH_OPCODE_DUAL_READ	0x3B /* Dual read data bytes */
-#define	XQSPIPS_FLASH_OPCODE_BE_32K	0x52 /* Erase 32KiB block */
-#define	XQSPIPS_FLASH_OPCODE_QUAD_READ	0x6B /* Quad read data bytes */
-#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS	0x75 /* Erase suspend */
-#define	XQSPIPS_FLASH_OPCODE_ERASE_RES	0x7A /* Erase resume */
-#define	XQSPIPS_FLASH_OPCODE_RDID	0x9F /* Read JEDEC ID */
-#define	XQSPIPS_FLASH_OPCODE_BE		0xC7 /* Erase whole flash block */
-#define	XQSPIPS_FLASH_OPCODE_SE		0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR	0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD	0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR	0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD	0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE	0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR	0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR	0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG	0xE8	/* Lock Reg Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG	0xE5	/* Lock Reg Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE	1
-#define XQSPIPS_SIZE_TWO	2
-#define XQSPIPS_SIZE_THREE	3
-#define XQSPIPS_SIZE_FOUR	4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE		0
-#define XQSPIPS_CONNECTION_MODE_STACKED		1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL	2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT		32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device.  The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode.  The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param	CallBackRef is the callback reference passed in by the upper
- *		layer when setting the callback functions, and passed back to
- *		the upper layer when the callback is invoked. Its type is
- *		not important to the driver, so it is a void pointer.
- * @param	StatusEvent holds one or more status events that have occurred.
- *		See the XQspiPs_SetStatusHandler() for details on the status
- *		events that can be passed in the callback.
- * @param	ByteCount indicates how many bytes of data were successfully
- *		transferred.  This may be less than the number of bytes
- *		requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
-					unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID  of device */
-	u32 BaseAddress;	/**< Base address of the device */
-	u32 InputClockHz;	/**< Input clock frequency */
-	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
-	XQspiPs_Config Config;	 /**< Configuration structure */
-	u32 IsReady;		 /**< Device is initialized and ready */
-
-	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
-	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
-	int RequestedBytes;	 /**< Number of bytes to transfer (state) */
-	int RemainingBytes;	 /**< Number of bytes left to transfer(state) */
-	u32 IsBusy;		 /**< A transfer is in progress (state) */
-	XQspiPs_StatusHandler StatusHandler;
-	void *StatusRef;	 /**< Callback reference for status handler */
-	u32 ShiftReadData;	 /**<  Flag to indicate whether the data
-				   *   read from the Rx FIFO needs to be shifted
-				   *   in cases where the data is less than 4
-				   *   bytes
-				   */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-*		- TRUE if option is set
-*		- FALSE if option is not set
-*
-* @note		C-Style signature:
-*		u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
-	((XQspiPs_GetOptions(InstancePtr) & \
-	  XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param	InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-*		- TRUE if option is set
-*		- FALSE if option is not set
-*
-* @note		C-Style signature:
-*		u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
-	((XQspiPs_GetOptions(InstancePtr) & \
-	  XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-* @param	RegisterValue is the value to be written, valid values are
-*		0-255.
-*
-* @return	None
-*
-* @note		C-Style signature:
-*		void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
-*			u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
-	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +	\
-			XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return	An 8-bit value representing Slave Idle Count.
-*
-* @note		C-Style signature:
-*		u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr)				\
-	XQspiPs_In32(((InstancePtr)->Config.BaseAddress) +		\
-	XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-* @param	RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
-*			u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
-	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
-			XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return	A 6-bit value representing Tx Watermark level.
-*
-* @note		C-Style signature:
-*		u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr)				\
-	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-* @param	RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
-*			u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
-	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
-			XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return	A 6-bit value representing Rx Watermark level.
-*
-* @note		C-Style signature:
-*		u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr)				\
-	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr)					\
-	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
-			XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr)					\
-	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-* @param	RegisterValue is the value to be written to the Linear QSPI
-*		configuration register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-*			u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)		\
-	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
-			XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param	InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return	A 32-bit value representing the contents of the LQSPI Config
-*		register.
-*
-* @note		C-Style signature:
-*		u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr)				\
-	XQspiPs_In32((InstancePtr->Config.BaseAddress) +		\
-			XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
-			   u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
-		      u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
-			    u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
-			u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
-				XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
-			 u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
-			 u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xqspips_hw.h

@@ -1,421 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2019 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_6
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or  macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00  sdm 11/25/10 First release
-* 2.00a ka  07/25/12 Added a few register defines for CR 670297
-*		     and removed some defines of reserved fields for
-*		     CR 671468
-*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-*		     bit in Configuration register.
-* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-*		     which need write to clear. Removed Read zeros mask from
-*		     LQSPI Config register.
-* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
-*                    linear mode initialization for boot. Added related
-*                    constant definitions.
-* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
-*                    required bits leaving reserved bits untouched. CR# 796813.
-* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
-* 					 controller does not update FIFO status flags as expected
-* 					 when thresholds are used.
-* 3.6   akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H		/* prevent circular inclusions */
-#define XQSPIPS_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET	 	0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET	 	0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET	 	0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET	 	0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET	 	0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET	 	0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET	 	0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET	 	0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET	 	0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET	 	0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET	 	0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET	 	0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET	 	0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET	0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET	 	0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET	 	0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET	 	0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET  	0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET  	0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET  		0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK    0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK    0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK   0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
-						   Enable */
-#define XQSPIPS_CR_SSFORCE_MASK   0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK    0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT   10	      /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK   0x000000C0 /**< Size of word to be
-						   transferred */
-#define XQSPIPS_CR_PRESC_MASK     0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT    3	      /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM  0x07	      /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK      0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK      0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK    0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK    0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK   0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET  XQSPIPS_CR_IFMODE_MASK | \
-				   XQSPIPS_CR_SSCTRL_MASK | \
-				   XQSPIPS_CR_DATA_SZ_MASK | \
-				   XQSPIPS_CR_MSTREN_MASK | \
-				   XQSPIPS_CR_SSFORCE_MASK | \
-				   XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR  XQSPIPS_CR_CPOL_MASK | \
-				   XQSPIPS_CR_CPHA_MASK | \
-				   XQSPIPS_CR_PRESC_MASK | \
-				   XQSPIPS_CR_MANSTRTEN_MASK | \
-				   XQSPIPS_CR_MANSTRT_MASK | \
-				   XQSPIPS_CR_ENDIAN_MASK | \
-				   XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * <b>QSPI Status Register</b>
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * <b>QSPI Interrupt Enable Register</b>
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register.  Write only.
- *
- * <b>QSPI Interrupt Disable Register </b>
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * <b>QSPI Interrupt Mask Register</b>
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK	   0x00000040  /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK    0x00000020  /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK  0x00000010  /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK    0x00000008  /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK	   0x00000004  /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK	   0x00000001  /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK	   0x00000025  /**< QSPI default interrupts
-						    mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041  /**< Interrupts which
-						    need write to clear */
-#define XQSPIPS_ISR_RESET_STATE    0x00000004  /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL    0x0000007D  /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK    0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK	0xFF000000 /**< Delay to de-assert slave select
-						between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT	24	   /**< Delay to de-assert slave select
-						between two words shift */
-#define XQSPIPS_DR_BTWN_MASK	0x00FF0000 /**< Delay Between Transfers
-						mask */
-#define XQSPIPS_DR_BTWN_SHIFT	16	   /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK	0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT	8 	   /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK	0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK	0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK           0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE    0x00000001 /**< Transmit Watermark
-						  * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK	    0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE    0x00000001 /**< Receive Watermark
-						  * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH	63	/**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK	 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK	 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK	 0x20000000 /**< Seperate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK	 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK	 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK	 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
-							 or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK	 0x00000700 /**< Number of dummy bytes
-							 between addr and return
-							 read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK	 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE	 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK	  0x00000004 /**< AXI Data FSM Error
-							  received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK	  0x00000002 /**< AXI write command
-							  received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-#define XQSPIPS_DUMMY_TX_DATA   0xFFFFFFFF
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to the target register.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
-	XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param	BaseAddress contains the base address of the device.
-* @param	RegOffset contains the offset from the 1st register of the
-*		device to target register.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-*		u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
-	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xreg_cortexa9.h

@@ -1,587 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm  10/20/09 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XREG_CORTEXA9_H
-#define XREG_CORTEXA9_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* GPRs */
-#define XREG_GPR0				r0
-#define XREG_GPR1				r1
-#define XREG_GPR2				r2
-#define XREG_GPR3				r3
-#define XREG_GPR4				r4
-#define XREG_GPR5				r5
-#define XREG_GPR6				r6
-#define XREG_GPR7				r7
-#define XREG_GPR8				r8
-#define XREG_GPR9				r9
-#define XREG_GPR10				r10
-#define XREG_GPR11				r11
-#define XREG_GPR12				r12
-#define XREG_GPR13				r13
-#define XREG_GPR14				r14
-#define XREG_GPR15				r15
-#define XREG_CPSR				cpsr
-
-/* Coprocessor number defines */
-#define XREG_CP0				0
-#define XREG_CP1				1
-#define XREG_CP2				2
-#define XREG_CP3				3
-#define XREG_CP4				4
-#define XREG_CP5				5
-#define XREG_CP6				6
-#define XREG_CP7				7
-#define XREG_CP8				8
-#define XREG_CP9				9
-#define XREG_CP10				10
-#define XREG_CP11				11
-#define XREG_CP12				12
-#define XREG_CP13				13
-#define XREG_CP14				14
-#define XREG_CP15				15
-
-/* Coprocessor control register defines */
-#define XREG_CR0				cr0
-#define XREG_CR1				cr1
-#define XREG_CR2				cr2
-#define XREG_CR3				cr3
-#define XREG_CR4				cr4
-#define XREG_CR5				cr5
-#define XREG_CR6				cr6
-#define XREG_CR7				cr7
-#define XREG_CR8				cr8
-#define XREG_CR9				cr9
-#define XREG_CR10				cr10
-#define XREG_CR11				cr11
-#define XREG_CR12				cr12
-#define XREG_CR13				cr13
-#define XREG_CR14				cr14
-#define XREG_CR15				cr15
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE			0x20
-#define XREG_CPSR_MODE_BITS			0x1F
-#define XREG_CPSR_SYSTEM_MODE			0x1F
-#define XREG_CPSR_UNDEFINED_MODE		0x1B
-#define XREG_CPSR_DATA_ABORT_MODE		0x17
-#define XREG_CPSR_SVC_MODE			0x13
-#define XREG_CPSR_IRQ_MODE			0x12
-#define XREG_CPSR_FIQ_MODE			0x11
-#define XREG_CPSR_USER_MODE			0x10
-
-#define XREG_CPSR_IRQ_ENABLE			0x80
-#define XREG_CPSR_FIQ_ENABLE			0x40
-
-#define XREG_CPSR_N_BIT				0x80000000
-#define XREG_CPSR_Z_BIT				0x40000000
-#define XREG_CPSR_C_BIT				0x20000000
-#define XREG_CPSR_V_BIT				0x10000000
-
-
-/* CP15 defines */
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
-#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
-#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
-#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
-#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
-
-#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
-#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
-
-#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
-#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
-#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
-#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
-#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
-
-#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
-#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
-
-#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
-#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
-
-#define XREG_CP15_SECURE_CONFIG			"p15, 0, %0,  c1,  c1, 0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE		"p15, 0, %0,  c1,  c1, 1"
-#define XREG_CP15_NS_ACCESS_CONTROL		"p15, 0, %0,  c1,  c1, 2"
-#define XREG_CP15_VIRTUAL_CONTROL		"p15, 0, %0,  c1,  c1, 3"
-
-#else /* RVCT */
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID			"cp15:0:c0:c0:0"
-#define XREG_CP15_CACHE_TYPE			"cp15:0:c0:c0:1"
-#define XREG_CP15_TCM_TYPE			"cp15:0:c0:c0:2"
-#define XREG_CP15_TLB_TYPE			"cp15:0:c0:c0:3"
-#define XREG_CP15_MULTI_PROC_AFFINITY		"cp15:0:c0:c0:5"
-
-#define XREG_CP15_PROC_FEATURE_0		"cp15:0:c0:c1:0"
-#define XREG_CP15_PROC_FEATURE_1		"cp15:0:c0:c1:1"
-#define XREG_CP15_DEBUG_FEATURE_0		"cp15:0:c0:c1:2"
-#define XREG_CP15_MEMORY_FEATURE_0		"cp15:0:c0:c1:4"
-#define XREG_CP15_MEMORY_FEATURE_1		"cp15:0:c0:c1:5"
-#define XREG_CP15_MEMORY_FEATURE_2		"cp15:0:c0:c1:6"
-#define XREG_CP15_MEMORY_FEATURE_3		"cp15:0:c0:c1:7"
-
-#define XREG_CP15_INST_FEATURE_0		"cp15:0:c0:c2:0"
-#define XREG_CP15_INST_FEATURE_1		"cp15:0:c0:c2:1"
-#define XREG_CP15_INST_FEATURE_2		"cp15:0:c0:c2:2"
-#define XREG_CP15_INST_FEATURE_3		"cp15:0:c0:c2:3"
-#define XREG_CP15_INST_FEATURE_4		"cp15:0:c0:c2:4"
-
-#define XREG_CP15_CACHE_SIZE_ID			"cp15:1:c0:c0:0"
-#define XREG_CP15_CACHE_LEVEL_ID		"cp15:1:c0:c0:1"
-#define XREG_CP15_AUXILARY_ID			"cp15:1:c0:c0:7"
-
-#define XREG_CP15_CACHE_SIZE_SEL		"cp15:2:c0:c0:0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL			"cp15:0:c1:c0:0"
-#define XREG_CP15_AUX_CONTROL			"cp15:0:c1:c0:1"
-#define XREG_CP15_CP_ACCESS_CONTROL		"cp15:0:c1:c0:2"
-
-#define XREG_CP15_SECURE_CONFIG			"cp15:0:c1:c1:0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE		"cp15:0:c1:c1:1"
-#define XREG_CP15_NS_ACCESS_CONTROL		"cp15:0:c1:c1:2"
-#define XREG_CP15_VIRTUAL_CONTROL		"cp15:0:c1:c1:3"
-#endif
-
-/* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
-#define XREG_CP15_CONTROL_V_BIT			0x00002000U
-#define XREG_CP15_CONTROL_I_BIT			0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
-#define XREG_CP15_CONTROL_B_BIT			0x00000080U
-#define XREG_CP15_CONTROL_C_BIT			0x00000004U
-#define XREG_CP15_CONTROL_A_BIT			0x00000002U
-#define XREG_CP15_CONTROL_M_BIT			0x00000001U
-
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0				"p15, 0, %0,  c2,  c0, 0"
-#define XREG_CP15_TTBR1				"p15, 0, %0,  c2,  c0, 1"
-#define XREG_CP15_TTB_CONTROL			"p15, 0, %0,  c2,  c0, 2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL		"p15, 0, %0,  c3,  c0, 0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
-
-#define XREG_CP15_INVAL_IC_POU_IS		"p15, 0, %0,  c7,  c1, 0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"p15, 0, %0,  c7,  c1, 6"
-
-#define XREG_CP15_PHYS_ADDR			"p15, 0, %0,  c7,  c4, 0"
-
-#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0		"p15, 0, %0,  c7,  c8, 0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1		"p15, 0, %0,  c7,  c8, 1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2		"p15, 0, %0,  c7,  c8, 2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3		"p15, 0, %0,  c7,  c8, 3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0		"p15, 0, %0,  c7,  c8, 4"
-#define XREG_CP15_VA_TO_PA_OTHER_1		"p15, 0, %0,  c7,  c8, 5"
-#define XREG_CP15_VA_TO_PA_OTHER_2		"p15, 0, %0,  c7,  c8, 6"
-#define XREG_CP15_VA_TO_PA_OTHER_3		"p15, 0, %0,  c7,  c8, 7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
-
-#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS			"p15, 0, %0,  c8,  c3, 0"
-#define XREG_CP15_INVAL_TLB_MVA_IS		"p15, 0, %0,  c8,  c3, 1"
-#define XREG_CP15_INVAL_TLB_ASID_IS		"p15, 0, %0,  c8,  c3, 2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"p15, 0, %0,  c8,  c3, 3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED		"p15, 0, %0,  c8,  c5, 0"
-#define XREG_CP15_INVAL_ITLB_MVA		"p15, 0, %0,  c8,  c5, 1"
-#define XREG_CP15_INVAL_ITLB_ASID		"p15, 0, %0,  c8,  c5, 2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED		"p15, 0, %0,  c8,  c6, 0"
-#define XREG_CP15_INVAL_DTLB_MVA		"p15, 0, %0,  c8,  c6, 1"
-#define XREG_CP15_INVAL_DTLB_ASID		"p15, 0, %0,  c8,  c6, 2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED		"p15, 0, %0,  c8,  c7, 0"
-#define XREG_CP15_INVAL_UTLB_MVA		"p15, 0, %0,  c8,  c7, 1"
-#define XREG_CP15_INVAL_UTLB_ASID		"p15, 0, %0,  c8,  c7, 2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID		"p15, 0, %0,  c8,  c7, 3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
-#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
-
-#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN			"p15, 0, %0, c10,  c0, 0"
-
-#define XREG_CP15_PRI_MEM_REMAP			"p15, 0, %0, c10,  c2, 0"
-#define XREG_CP15_NORM_MEM_REMAP		"p15, 0, %0, c10,  c2, 1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR			"p15, 0, %0, c12,  c0, 0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"p15, 0, %0, c12,  c0, 1"
-
-#define XREG_CP15_INTERRUPT_STATUS		"p15, 0, %0, c12,  c1, 0"
-#define XREG_CP15_VIRTUALIZATION_INTR		"p15, 0, %0, c12,  c1, 1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
-#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
-#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
-#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL			"p15, 0, %0, c15,  c0, 0"
-#define XREG_CP15_CONFIG_BASE_ADDR		"p15, 4, %0, c15,  c0, 0"
-
-#define XREG_CP15_READ_TLB_ENTRY		"p15, 5, %0, c15,  c4, 2"
-#define XREG_CP15_WRITE_TLB_ENTRY		"p15, 5, %0, c15,  c4, 4"
-
-#define XREG_CP15_MAIN_TLB_VA			"p15, 5, %0, c15,  c5, 2"
-
-#define XREG_CP15_MAIN_TLB_PA			"p15, 5, %0, c15,  c6, 2"
-
-#define XREG_CP15_MAIN_TLB_ATTR			"p15, 5, %0, c15,  c7, 2"
-
-#else
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0				"cp15:0:c2:c0:0"
-#define XREG_CP15_TTBR1				"cp15:0:c2:c0:1"
-#define XREG_CP15_TTB_CONTROL			"cp15:0:c2:c0:2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL		"cp15:0:c3:c0:0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS		"cp15:0:c5:c0:0"
-#define XREG_CP15_INST_FAULT_STATUS		"cp15:0:c5:c0:1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS		"cp15:0:c5:c1:0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS		"cp15:0:c5:c1:1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS		"cp15:0:c6:c0:0"
-#define XREG_CP15_INST_FAULT_ADDRESS		"cp15:0:c6:c0:2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP				"cp15:0:c7:c0:4"
-
-#define XREG_CP15_INVAL_IC_POU_IS		"cp15:0:c7:c1:0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"cp15:0:c7:c1:6"
-
-#define XREG_CP15_PHYS_ADDR			"cp15:0:c7:c4:0"
-
-#define XREG_CP15_INVAL_IC_POU			"cp15:0:c7:c5:0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"cp15:0:c7:c5:1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER		"cp15:0:c7:c5:4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY		"cp15:0:c7:c5:6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"cp15:0:c7:c6:1"
-#define XREG_CP15_INVAL_DC_LINE_SW		"cp15:0:c7:c6:2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0		"cp15:0:c7:c8:0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1		"cp15:0:c7:c8:1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2		"cp15:0:c7:c8:2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3		"cp15:0:c7:c8:3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0		"cp15:0:c7:c8:4"
-#define XREG_CP15_VA_TO_PA_OTHER_1		"cp15:0:c7:c8:5"
-#define XREG_CP15_VA_TO_PA_OTHER_2		"cp15:0:c7:c8:6"
-#define XREG_CP15_VA_TO_PA_OTHER_3		"cp15:0:c7:c8:7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"cp15:0:c7:c10:1"
-#define XREG_CP15_CLEAN_DC_LINE_SW		"cp15:0:c7:c10:2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER		"cp15:0:c7:c10:4"
-#define XREG_CP15_DATA_MEMORY_BARRIER		"cp15:0:c7:c10:5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"cp15:0:c7:c11:1"
-
-#define XREG_CP15_NOP2				"cp15:0:c7:c13:1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"cp15:0:c7:c14:1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"cp15:0:c7:c14:2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS			"cp15:0:c8:c3:0"
-#define XREG_CP15_INVAL_TLB_MVA_IS		"cp15:0:c8:c3:1"
-#define XREG_CP15_INVAL_TLB_ASID_IS		"cp15:0:c8:c3:2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"cp15:0:c8:c3:3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED		"cp15:0:c8:c5:0"
-#define XREG_CP15_INVAL_ITLB_MVA		"cp15:0:c8:c5:1"
-#define XREG_CP15_INVAL_ITLB_ASID		"cp15:0:c8:c5:2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED		"cp15:0:c8:c6:0"
-#define XREG_CP15_INVAL_DTLB_MVA		"cp15:0:c8:c6:1"
-#define XREG_CP15_INVAL_DTLB_ASID		"cp15:0:c8:c6:2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED		"cp15:0:c8:c7:0"
-#define XREG_CP15_INVAL_UTLB_MVA		"cp15:0:c8:c7:1"
-#define XREG_CP15_INVAL_UTLB_ASID		"cp15:0:c8:c7:2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID		"cp15:0:c8:c7:3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL		"cp15:0:c9:c12:0"
-#define XREG_CP15_COUNT_ENABLE_SET		"cp15:0:c9:c12:1"
-#define XREG_CP15_COUNT_ENABLE_CLR		"cp15:0:c9:c12:2"
-#define XREG_CP15_V_FLAG_STATUS			"cp15:0:c9:c12:3"
-#define XREG_CP15_SW_INC			"cp15:0:c9:c12:4"
-#define XREG_CP15_EVENT_CNTR_SEL		"cp15:0:c9:c12:5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER		"cp15:0:c9:c13:0"
-#define XREG_CP15_EVENT_TYPE_SEL		"cp15:0:c9:c13:1"
-#define XREG_CP15_PERF_MONITOR_COUNT		"cp15:0:c9:c13:2"
-
-#define XREG_CP15_USER_ENABLE			"cp15:0:c9:c14:0"
-#define XREG_CP15_INTR_ENABLE_SET		"cp15:0:c9:c14:1"
-#define XREG_CP15_INTR_ENABLE_CLR		"cp15:0:c9:c14:2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN			"cp15:0:c10:c0:0"
-
-#define XREG_CP15_PRI_MEM_REMAP			"cp15:0:c10:c2:0"
-#define XREG_CP15_NORM_MEM_REMAP		"cp15:0:c10:c2:1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR			"cp15:0:c12:c0:0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"cp15:0:c12:c0:1"
-
-#define XREG_CP15_INTERRUPT_STATUS		"cp15:0:c12:c1:0"
-#define XREG_CP15_VIRTUALIZATION_INTR		"cp15:0:c12:c1:1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID			"cp15:0:c13:c0:1"
-#define USER_RW_THREAD_PID			"cp15:0:c13:c0:2"
-#define USER_RO_THREAD_PID			"cp15:0:c13:c0:3"
-#define USER_PRIV_THREAD_PID			"cp15:0:c13:c0:4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL			"cp15:0:c15:c0:0"
-#define XREG_CP15_CONFIG_BASE_ADDR		"cp15:4:c15:c0:0"
-
-#define XREG_CP15_READ_TLB_ENTRY		"cp15:5:c15:c4:2"
-#define XREG_CP15_WRITE_TLB_ENTRY		"cp15:5:c15:c4:4"
-
-#define XREG_CP15_MAIN_TLB_VA			"cp15:5:c15:c5:2"
-
-#define XREG_CP15_MAIN_TLB_PA			"cp15:5:c15:c6:2"
-
-#define XREG_CP15_MAIN_TLB_ATTR			"cp15:5:c15:c7:2"
-#endif
-
-
-/* MPE register definitions */
-#define XREG_FPSID				c0
-#define XREG_FPSCR				c1
-#define XREG_MVFR1				c6
-#define XREG_MVFR0				c7
-#define XREG_FPEXC				c8
-#define XREG_FPINST				c9
-#define XREG_FPINST2				c10
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT	(24)
-#define XREG_FPSID_IMPLEMENTER_MASK	(0xFF << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE		(1<<23)
-#define XREG_FPSID_ARCH_BIT		(16)
-#define XREG_FPSID_ARCH_MASK		(0xF  << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT		(8)
-#define XREG_FPSID_PART_MASK		(0xFF << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT		(4)
-#define XREG_FPSID_VARIANT_MASK		(0xF  << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT		(0)
-#define XREG_FPSID_REV_MASK		(0xF  << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT		(1 << 31)
-#define XREG_FPSCR_Z_BIT		(1 << 30)
-#define XREG_FPSCR_C_BIT		(1 << 29)
-#define XREG_FPSCR_V_BIT		(1 << 28)
-#define XREG_FPSCR_QC			(1 << 27)
-#define XREG_FPSCR_AHP			(1 << 26)
-#define XREG_FPSCR_DEFAULT_NAN		(1 << 25)
-#define XREG_FPSCR_FLUSHTOZERO		(1 << 24)
-#define XREG_FPSCR_ROUND_NEAREST	(0 << 22)
-#define XREG_FPSCR_ROUND_PLUSINF	(1 << 22)
-#define XREG_FPSCR_ROUND_MINUSINF	(2 << 22)
-#define XREG_FPSCR_ROUND_TOZERO		(3 << 22)
-#define XREG_FPSCR_RMODE_BIT		(22)
-#define XREG_FPSCR_RMODE_MASK		(3 << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT		(20)
-#define XREG_FPSCR_STRIDE_MASK		(3 << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT		(16)
-#define XREG_FPSCR_LENGTH_MASK		(7 << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC			(1 << 7)
-#define XREG_FPSCR_IXC			(1 << 4)
-#define XREG_FPSCR_UFC			(1 << 3)
-#define XREG_FPSCR_OFC			(1 << 2)
-#define XREG_FPSCR_DZC			(1 << 1)
-#define XREG_FPSCR_IOC			(1 << 0)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT		(28)
-#define XREG_MVFR0_RMODE_MASK		(0xF << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT	(24)
-#define XREG_MVFR0_SHORT_VEC_MASK	(0xF << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT		(20)
-#define XREG_MVFR0_SQRT_MASK		(0xF << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT		(16)
-#define XREG_MVFR0_DIVIDE_MASK		(0xF << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT	(12)
-#define XREG_MVFR0_EXEC_TRAP_MASK	(0xF << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT		(8)
-#define XREG_MVFR0_DP_MASK		(0xF << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT		(4)
-#define XREG_MVFR0_SP_MASK		(0xF << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT		(0)
-#define XREG_MVFR0_A_SIMD_MASK		(0xF << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX			(1 << 31)
-#define XREG_FPEXC_EN			(1 << 30)
-#define XREG_FPEXC_DEX			(1 << 29)
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXA9_H */

df_datalink/bsp/ps7_cortexa9_0/include/xscugic.h

@@ -1,598 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v4_0
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-*   - specific individual interrupt enabling/disabling
-*   - specific individual interrupt acknowledging
-*   - attaching specific callback function to handle interrupt source
-*   - assigning desired priority to interrupt source if default is not
-*     acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent.  It works with
-* physical addresses only.  Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <b>Interrupt Vector Tables</b>
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs.  The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* <b>Nested Interrupts Processing</b>
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg  01/19/00 First release
-* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
-*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
-*		      moved to XScuGic_Config structure from XScuGic structure.
-*
-*		      The "Config" entry in XScuGic structure is made as
-*		      pointer for better efficiency.
-*
-*		      A new file named as xscugic_hw.c is now added. It is
-*		      to implement low level driver routines without using
-*		      any xscugic instance pointer. They are useful when the
-*		      user wants to use xscugic through device id or
-*		      base address. The driver routines provided are explained
-*		      below.
-*		      XScuGic_DeviceInitialize that takes device id as
-*		      argument and initializes the device (without calling
-*		      XScuGic_CfgInitialize).
-*		      XScuGic_DeviceInterruptHandler that takes device id
-*		      as argument and calls appropriate handlers from the
-*		      HandlerTable.
-*		      XScuGic_RegisterHandler that registers a new handler
-*		      by taking xscugic hardware base address as argument.
-*		      LookupConfigByBaseAddress is used to return the
-*		      corresponding config structure from XScuGic_ConfigTable
-*		      based on the scugic base address passed.
-* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
-*		      structure.
-* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-*		      *_hw.h
-*		      Added APIs
-*			- XScuGic_SetPriTrigTypeByDistAddr()
-*			- XScuGic_GetPriTrigTypeByDistAddr()
-*		      (CR 702687)
-*			Added support to direct interrupts to the appropriate CPU. Earlier
-*			  interrupts were directed to CPU1 (hard coded). Now depending
-*			  upon the CPU selected by the user (xparameters.h), interrupts
-*			  will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-*			  This is fix for CR#705621.
-* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
-*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0   adk  12/10/13 Updated as per the New Tcl API's
-* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
-*			  distributor is left uninitialized for Zynq AMP. It is assumed
-*             that the distributor will be initialized by Linux master. However
-*             for CortexR5 case, the earlier code is left unchanged where the
-*             the interrupt processor target registers in the distributor is
-*             initialized with the corresponding CPU ID on which the application
-*             built over the scugic driver runs.
-*             These changes fix CR#937243.
-*
-* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
-*            the flow and avoid code duplication. Changes are made for
-*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
-*            one R5 is operating with A53 in open amp config and other
-*            R5 running baremetal app, the existing code
-*            had the potential to stop the whole AMP solution to work (if
-*            for some reason the R5 running the baremetal app tasked to
-*            initialize the Distributor hangs or crashes before initializing).
-*            Changes are made so that the R5 under AMP first checks if
-*            the distributor is enabled or not and if not, it does the
-*            standard Distributor initialization.
-*            This fixes the CR#952962.
-* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
-*                     examples to ensure that "Successfully ran" and "Failed"
-*                     strings are available in all examples. This is a fix
-*                     for CR-965028.
-*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
-*       kvn  02/28/17 Make the CpuId as static variable and Added new
-*                     XScugiC_GetCpuId to access CpuId.
-*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
-*                     generation.
-* 3.7   ms   04/11/17 Modified tcl file to add suffix U for all macro
-*                     definitions of scugic in xparameters.h
-* 3.8   mus  07/05/17 Updated scugic.tcl to add support for intrrupts connected
-*                     through util_reduced_vector IP(OR gate)
-*       mus  07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-*                     the HandlerTable in XScuGic_ConfigTable to 0, it removes
-*                     the compilation warning in xscugic_g.c. Fix for CR#978736.
-*       mus  07/25/17 Updated xdefine_gic_params proc to export correct canonical
-*                     definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9   mus  02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-*                     XScuGic_InterruptUnmapFromCpu, These API's can be used
-*                     by applications to unmap specific/all interrupts from
-*                     target CPU.
-* 3.10  aru  08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.0   mus  11/22/18 Fixed bugs in software interrupt generation through 
-*                      XScuGic_SoftwareIntr API
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET   0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-
-#define XSCUGIC500_DCTLR_ARE_NS_ENABLE  0x20
-#define XSCUGIC500_DCTLR_ARE_S_ENABLE  0x10
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
-	Xil_InterruptHandler Handler;
-	void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
-	u16 DeviceId;		/**< Unique ID  of device */
-	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
-	u32 DistBaseAddress;	/**< Distributor Register base address */
-	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
-				 Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
-	XScuGic_Config *Config;  /**< Configuration table entry */
-	u32 IsReady;		 /**< Device is initialized and ready */
-	u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
-					((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
-	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
-					((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
-				   XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
-XSCUGIC_RDIST_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor SGI PPI Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be written
-* @param    Data is the 32-bit value to write to the register
-*
-* @return   None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
-				   XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor SGI PPI Interface register
-*
-* @param    InstancePtr is a pointer to the instance to be worked on.
-* @param    RegOffset is the register offset to be read
-*
-* @return   The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
-					XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-* This function enables system register interface for GIC CPU Interface
-*
-* @param	value to be written
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
-/****************************************************************************/
-/**
-* This function enables Grou0 interrupts
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
-/****************************************************************************/
-/**
-* This function enables Group1 interrupts
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL1_NONSECURE
-#define XScuGic_Enable_Group1_Interrupts() \
-		mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
-#else
-#define XScuGic_Enable_Group1_Interrupts() \
-		mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI0R_EL1
-*
-* @param	value to be written
-*
-* @return	None.
-*
-* @note     None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
-
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI1R_EL1
-*
-* @param	value to be written
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
-
-/****************************************************************************/
-/**
-* This function reads ICC_SGI1R_EL1 register
-*
-* @param	None
-*
-* @return	Value of ICC_SGI1R_EL1 register
-*
-* @note        None.
-*
-*****************************************************************************/
-#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
-/****************************************************************************/
-/**
-* This function sets interrupt priority filter
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#define XScuGic_set_priority_filter(val)  __asm__ __volatile__("msr  S3_0_C4_C6_0,%0"  : : "r" (val))
-/****************************************************************************/
-/**
-* This function returns interrupt id of highest priority pending interrupt
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_get_IntID()  mfcp(S3_0_C12_C8_0)
-#else
-#define XScuGic_get_IntID()  mfcp(S3_0_C12_C12_0)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function acks the interrupt
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#if  defined (__aarch64__)
-#if EL3
-#define XScuGic_ack_Int(val)   mtcp(S3_0_C12_C8_1,val)
-#else
-#define XScuGic_ack_Int(val)   mtcp(S3_0_C12_C12_1,val)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This macro returns bit position for the specific interrupt's trigger type
-* configuration within GICR_ICFGR0/GICR_ICFGR1 register
-*
-* @param	None.
-*
-* @return	None.
-*
-* @note        None.
-*
-*****************************************************************************/
-#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId)  (((Int_Id%16) & 0x1f) << 2) +1
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
-			Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
-							u32 EffectiveAddr);
-
-s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
-					u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
-					u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32  XScuGic_SelfTest(XScuGic *InstancePtr);
-
-void XScuGic_EnableSGI_PPI(XScuGic *InstancePtr,u32 ID);
-void XScuGic_SetPPI_SGI_Priority(XScuGic *InstancePtr,u32 ID, u32 priority);
-#ifdef __cplusplus
-}
-#endif
-
-#endif            /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xscugic_hw.h

@@ -1,753 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v4_0
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device.  The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg  01/19/10 First release
-* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
-*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-*		      added to enable or disable interrupts based on
-*		      Distributor Register base address. Normally users use
-*		      XScuGic instance and call XScuGic_Enable or
-*		      XScuGic_Disable to enable/disable interrupts. These
-*		      new macros are provided when user does not want to
-*		      use an instance pointer but still wants to enable or
-*		      disable interrupts.
-*		      Function prototypes for functions (present in newly
-*		      added file xscugic_hw.c) are added.
-* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
-*		      702687).
-* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
-*		      XScuGic_SetPriTrigTypeByDistAddr and
-*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-*		      Zynq Ultrascale Mp
-* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
-*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9   mus  02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-*					  and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-*					  API's can be used by applications to unmap specific/all
-*					  interrupts from target CPU. It fixes CR#992490.
-* 3.10  aru  08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef PLATFORM_ZYNQ
-#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
-#elif defined (versal) && !defined(ARMR5)
-#define XSCUGIC_MAX_NUM_INTR_INPUTS    	191U
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * First Interrupt Id for SPI interrupts.
- */
-#define XSCUGIC_SPI_INT_ID_START	0x20
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
-#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
-							Register */
-#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
-							Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
-							Register */
-#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
-							Register */
-#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
-							Register */
-#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
-							Register */
-#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
-							Register */
-#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
-							Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
-							Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
-							0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
-							Register */
-#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
-							Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
-#if defined (versal) && !defined(ARMR5)
-#define XSCUGIC_PCELLID_OFFSET		0x0000FFF0U /**< Pcell ID Register */
-#else
-#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
-#endif
-/* @} */
-
-/** @name  Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#if defined (versal) && !defined(ARMR5)
-#define XSCUGIC_EN_INT_MASK		0x00000003U /**< Interrupt In Enable */
-#else
-#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
-#endif
-/* @} */
-
-/** @name  Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
-						Shared Peripheral
-						Interrupts*/
-#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name  Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name  Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080.  A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
-						INT_ID */
-/* @} */
-
-/** @name  Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
-					      INT_ID */
-/* @} */
-
-/** @name  Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
-						INT_ID */
-#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
-						actually the lowest priority*/
-/* @} */
-
-/** @name  SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name  Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI    Read Only    b10 always
- * PPI    Read Only    depending on how the PPIs are configured.
- *                    b01    Active HIGH level sensitive
- *                    b11 Rising edge sensitive
- * SPI                LSB is read only.
- *                    b01    Active HIGH level sensitive
- *                    b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
-/* @} */
-
-/** @name  PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
-/* @} */
-
-/** @name  SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
-					     input */
-/* @} */
-
-/** @name  AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianess
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
-                                                  1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
-                                                  1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name  Software Triggered Interrupt Register
- * Controls issueing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
-                                                            b00-Use the target List
-                                                            b01-All CPUs except requester
-                                                            b10-To Requester
-                                                            b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
-                                                        signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
-							Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
-							Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
-						        Binary Point Register */
-
-/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
-                                                 0=separate registers,
-                                                 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
-                                                  interrupts,
-                                                  0= use IRQ for both,
-                                                  1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-/** @name Priority Mask Register
- * Priority Mask register definitions
- * The CPU interface does not send interrupt if the level of the interrupt is
- * lower than the level of the register.
- * @{
- */
-/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
-/* @} */
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
-						Value  Secure  Non-secure
-						b000    0xFE    0xFF
-						b001    0xFC    0xFE
-						b010    0xF8    0xFC
-						b011    0xF0    0xF8
-						b100    0xE0    0xF0
-						b101    0xC0    0xE0
-						b110    0x80    0xC0
-						b111    0x00    0x80
-						*/
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
-/* @} */
-
-#if defined (versal) && !defined(ARMR5)
-#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
-#endif
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interupt
- */
-#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
-/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
-/* @} */
-#if defined (versal) && !defined(ARMR5)
-/** @name ReDistributor Interface Register Map
- *
- * @{
- */
-#define XSCUGIC_RDIST_OFFSET              0x80000U
-#define XSCUGIC_RDIST_BASE_ADDRESS        (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
-#define XSCUGIC_RDIST_SGI_PPI_OFFSET              0x90000U
-#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS    (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
-#define XSCUGIC_RDIST_ISENABLE_OFFSET     0x100U
-#define XSCUGIC_RDIST_IPRIORITYR_OFFSET   0x400U
-#define XSCUGIC_RDIST_IGROUPR_OFFSET      0x80U
-#define XSCUGIC_RDIST_GRPMODR_OFFSET      0xD00U
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET   0xC00U
-#define XSCUGIC_RDIST_WAKER_OFFSET        0x14U
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT    24U
-
-/*
- * GICR_IGROUPR  register definitions
- */
-#if EL3
-#define XSCUGIC_DEFAULT_SECURITY    0x0U
-#else
-#define XSCUGIC_DEFAULT_SECURITY    0xFFFFFFFFU
-#endif
-/*
- * GICR_WAKER  register definitions
- */
-#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK    0x7
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Routing Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt configuration register offset
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt Priority register offset
-*
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
-	((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param	Register is the register offset for the clear/enable bank.
-* @param	InterruptID is the interrupt number.
-*
-* @return	The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
-		((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param	BaseAddress is the base address of the device.
-* @param	RegOffset is the register offset to be read
-*
-* @return	The 32-bit value of the register
-*
-* @note
-* C-style signature:
-*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
-	(Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param	BaseAddress is the base address of the device.
-* @param	RegOffset is the register offset to be written
-* @param	Data is the 32-bit value to write to the register
-*
-* @return	None.
-*
-* @note
-* C-style signature:
-*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
-	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/****************************************************************************/
-/**
-*
-* Enable specific interrupt(s) in the interrupt controller.
-*
-* @param	DistBaseAddress is the Distributor Register base address of the
-*		device
-* @param	Int_Id is the ID of the interrupt source and should be in the
-*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
-	XScuGic_WriteReg((DistBaseAddress), \
-			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
-			 (0x00000001U << ((Int_Id) % 32U)))
-
-/****************************************************************************/
-/**
-*
-* Disable specific interrupt(s) in the interrupt controller.
-*
-* @param	DistBaseAddress is the Distributor Register base address of the
-*		device
-* @param	Int_Id is the ID of the interrupt source and should be in the
-*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
-	XScuGic_WriteReg((DistBaseAddress), \
-			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
-			 (0x00000001U << ((Int_Id) % 32U)))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32  XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
-			     Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
-                                        u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
-					u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
-											u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
-												u8 Cpu_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif            /* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xscutimer.h

@@ -1,364 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_1
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* 		has to register it's own handler)
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* <b> Interrupts </b>
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm  03/10/10 First release
-* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
-*		     when the xstatus.h in the common driver overwrites
-*		     the xstatus.h of the standalone BSP during the
-*		     libgen.
-* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
-*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
-*                    generation.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H		/* prevent circular inclusions */
-#define XSCUTIMER_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;	/**< Unique ID of device */
-	u32 BaseAddr;	/**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
-	XScuTimer_Config Config; /**< Hardware Configuration */
-	u32 IsReady;		/**< Device is initialized and ready */
-	u32 IsStarted;		/**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-*		- TRUE if the timer has expired.
-*		- FALSE if the timer has not expired.
-*
-* @note		C-style signature:
-*		int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
-	((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
-				XSCUTIMER_ISR_OFFSET) & \
-				XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
-				XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr)				\
-	XScuTimer_LoadTimer((InstancePtr),				\
-		XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
-					XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-* @param	Value is the count to be loaded in to the load register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value)				\
-	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	Contents of the timer counter register.
-*
-* @note		C-style signature:
-		u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr)				\
-	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
-				XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr)				\
-	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUTIMER_CONTROL_OFFSET,			\
-			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
-				XSCUTIMER_CONTROL_OFFSET) |		 \
-				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr)			\
-	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUTIMER_CONTROL_OFFSET,			\
-			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
-				XSCUTIMER_CONTROL_OFFSET) &		\
-				~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr)				\
-	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUTIMER_CONTROL_OFFSET,			\
-			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
-					XSCUTIMER_CONTROL_OFFSET) |	\
-					XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr)				\
-	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUTIMER_CONTROL_OFFSET,			\
-			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
-				XSCUTIMER_CONTROL_OFFSET) &		\
-				~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr)			\
-	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param	InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr)			\
-	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
-		XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
-			    XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xscutimer_hw.h

@@ -1,283 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_1
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm  03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-*		     and interrupt registers
-* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-*		     when the xstatus.h in the common driver overwrites
-*		     the xstatus.h of the standalone BSP during the
-*		     libgen.
-* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H		/* prevent circular inclusions */
-#define XSCUTIMER_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET		0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET	0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET	0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET		0x0CU /**< Timer Interrupt
-						  Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT	8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK	0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK		0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK		0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param	BaseAddr is the base address of the scu timer.
-* @param	Value is the count to be loaded in to the load register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value)				\
-	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param	BaseAddr is the base address of the scu timer.
-*
-* @return	Contents of the timer load register.
-*
-* @note		C-style signature:
-*		u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr)					\
-	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param	BaseAddr is the base address of the scu timer.
-* @param	Value is the count to be loaded in to the counter register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value)			\
-	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param	BaseAddr is the base address of the scu timer.
-*
-* @return	Contents of the timer counter register.
-*
-* @note		C-style signature:
-		u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr)				\
-	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param	BaseAddr is the base address of the scu timer.
-* @param	Value is the count to be loaded in to the load register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value)			\
-	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param	BaseAddr is the base address of the scu timer.
-*
-* @return	Contents of the timer load register.
-*
-* @note		C-style signature:
-		u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr)				\
-	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param	BaseAddr is the base address of the scu timer.
-* @param	Value is the count to be loaded in to the counter register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value)				\
-	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param	BaseAddr is the base address of the scu timer.
-*
-* @return	Contents of the timer counter register.
-*
-* @note		C-style signature:
-		u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr)					\
-	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param	BaseAddr is the base address of the device
-* @param	RegOffset is the register offset to be read
-*
-* @return	The 32-bit value of the register
-*
-* @note		C-style signature:
-*		u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset)		\
-	Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param	BaseAddr is the base address of the device
-* @param	RegOffset is the register offset to be written
-* @param	Data is the 32-bit value to write to the register
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data)	\
-	Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xscuwdt.h

@@ -1,379 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_1
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* <b>Interrupts</b>
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-*		     when the xstatus.h in the common driver overwrites
-*		     the xstatus.h of the standalone BSP during the
-*		     libgen.
-* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
-*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
-*                    generation.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUWDT_H		/* prevent circular inclusions */
-#define XSCUWDT_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddr;		/**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
-	XScuWdt_Config Config;/**< Hardware Configuration */
-	u32 IsReady;		/**< Device is initialized and ready */
-	u32 IsStarted;		/**< Device watchdog timer is running */
-} XScuWdt;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-*		- TRUE if the watchdog has expired.
-*		- FALSE if the watchdog has not expired.
-*
-* @note		C-style signature:
-*		int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr)				\
-	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
-			  XSCUWDT_RST_STS_OFFSET) &			\
-	 XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-*		- TRUE if the watchdog has expired.
-*		- FALSE if the watchdog has not expired.
-*
-* @note		C-style signature:
-*		int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr)				\
-	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
-			  XSCUWDT_ISR_OFFSET) &				\
-	 XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr)					 \
-	XScuWdt_LoadWdt((InstancePtr),					 \
-			(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
-					 XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-* @param	Value is the value to be written to the Watchdog Load register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value)				\
-	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr)					  \
-	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		  \
-			 XSCUWDT_CONTROL_OFFSET,			  \
-			 (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
-			  XSCUWDT_CONTROL_OFFSET) |			  \
-			  (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr)				\
-{									\
-	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUWDT_DISABLE_OFFSET,				\
-			XSCUWDT_DISABLE_VALUE1);			\
-	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			XSCUWDT_DISABLE_OFFSET,				\
-			XSCUWDT_DISABLE_VALUE2);			\
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return	Contents of the watchdog control register.
-*
-* @note		C-style signature:
-		u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr)				\
-	XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,			\
-			XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-* @param	ControlReg is the value to be written to the watchdog control
-*		register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-		void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg)			\
-	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
-			 XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param	InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr)				\
-	XScuWdt_SetControlReg((InstancePtr),				\
-			      (XScuWdt_GetControlReg(InstancePtr) |	\
-			      XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
-			  XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xscuwdt_hw.h

@@ -1,178 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_1
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-*                    of 0x20 as the base address obtained from the tools
-*		     starts at 0x20.
-* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-*		     when the xstatus.h in the common driver overwrites
-*		     the xstatus.h of the standalone BSP during the
-*		     libgen.
-* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H		/* prevent circular inclusions */
-#define XSCUWDT_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET	0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET	0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET	0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET	0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET	0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET	0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK	 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT	 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK	 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK	 0x00000004U /**< Intr enable (in
-							 timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
-							 timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK	 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK	0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK	0x00000001U /**< Time out occured */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1		0x12345678U /**< Watchdog mode disable
-							value 1 */
-#define XSCUWDT_DISABLE_VALUE2		0x87654321U /**< Watchdog mode disable
-							value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param	BaseAddr is the base address of the device
-* @param	RegOffset is the register offset to be read
-*
-* @return	The 32-bit value of the register
-*
-* @note		C-style signature:
-*		u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset)		\
-	Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param	BaseAddr is the base address of the device
-* @param	RegOffset is the register offset to be written
-* @param	Data is the 32-bit value to write to the register
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data)	\
-	Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* end of protection macro */
-/** @} */

df_datalink/bsp/ps7_cortexa9_0/include/xstatus.h

@@ -1,533 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx® software status codes
-*
-* The xstatus.h file contains the Xilinx® software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-#ifndef XSTATUS_H		/* prevent circular inclusions */
-#define XSTATUS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS                     0L
-#define XST_FAILURE                     1L
-#define XST_DEVICE_NOT_FOUND            2L
-#define XST_DEVICE_BLOCK_NOT_FOUND      3L
-#define XST_INVALID_VERSION             4L
-#define XST_DEVICE_IS_STARTED           5L
-#define XST_DEVICE_IS_STOPPED           6L
-#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
-						   operation with a FIFO such as
-						   an underrun or overrun, this
-						   error requires the device to
-						   be reset */
-#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
-						   the device to be reset */
-#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
-						   typically requires the device
-						   using the DMA to be reset */
-#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
-						   polled mode operation */
-#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
-						   the specified data into */
-#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
-						   to hold the expected data */
-#define XST_NO_DATA                     13L	/*!< There was no data available */
-#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
-						   expected value */
-#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
-						   into the function */
-#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
-						   scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
-#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
-						   registered */
-#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
-						   the requested feature */
-#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
-						   interrupt mode operation */
-#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
-#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
-						   have maxed out */
-#define XST_IS_STARTED                  23L	/*!< Used when part of device is
-						   already started i.e.
-						   sub channel */
-#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
-						   already stopped i.e.
-						   sub channel */
-#define XST_DATA_LOST                   26L	/*!< Driver defined error */
-#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
-#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
-#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
-						   available because it has not
-						   been enabled */
-#define XST_NO_ACCESS			30L	/* Generic access error */
-/** @} */
-/***************** Utility Component statuses 401 - 500  *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
-#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
-#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
-						   was invalid after reset */
-#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
-						 * empty and full simultaneously
-						 */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
-						   failed */
-#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
-						   was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
-						   no buffer descriptors ready
-						   to be processed */
-#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
-						   the scatter gather list are
-						   being used */
-#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
-						   descriptor which is to be
-						   copied over in the scatter
-						   list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
-						   put into the scatter gather
-						   list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
-						   specified was larger than the
-						   total # of buffer descriptors
-						   in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
-						   already been created */
-#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
-						   been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
-						   being started was not committed
-						   to the list */
-#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
-						   has already been used by the
-						   hardware so it can't be reused
-						 */
-#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
-						   error */
-#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
-						   error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
-						   was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
-						   reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
-						   register did not reset when
-						   acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
-						   register was not updated when
-						   other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
-						   did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
-						   not updated correctly when other
-						   registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
-						   register did not indicate the
-						   expected value */
-#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
-						   did not indicate the expected
-						   value */
-#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
-						 * to hold the minimum number of
-						 * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
-#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
-						 * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR         1051L
-#define XST_UART_START_ERROR        1052L
-#define XST_UART_CONFIG_ERROR       1053L
-#define XST_UART_TEST_FAIL          1054L
-#define XST_UART_BAUD_ERROR         1055L
-#define XST_UART_BAUD_RANGE         1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
-#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
-#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
-					     /* general call address        */
-#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
-					     /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
-					     /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
-					     /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
-					     /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
-					     /* didn't return written value */
-#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
-#define XST_IIC_ARB_LOST 				1089 	/*!< Arbitration lost for master	*/
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
-						   controller hit the max value
-						   which requires the statistics
-						   to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
-						 */
-#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
-#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
-						   error. Use XFlash_DeviceControl
-						   to retrieve device specific codes
-						 */
-#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
-						 */
-#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
-						 */
-#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
-						   driver */
-#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
-						   aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
-						   addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
-						   write/erase function with
-						   XFL_NON_BLOCKING_WRITE/ERASE
-						   option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
-						 * selected */
-#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
-						 */
-#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
-						   device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
-						 * one master assigned to two or more
-						 * priorities, or one master not
-						 * assigned to any priority
-						 */
-#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
-						 * priority levels without first
-						 * suspending the use of priority
-						 * levels
-						 */
-#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
-						 * bus parking was not enabled
-						 */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
-						 * priority mode to allow the
-						 * priorities to be changed
-						 */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
-#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED      1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST    1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST   1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST   1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS     1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR			1400
-#define XST_FR_TX_BUSY			1401
-#define XST_FR_BUF_LOCKED		1402
-#define XST_FR_NO_BUF			1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420  *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED	1410
-#define XST_USB_BUF_ALIGN_ERROR		1411
-#define XST_USB_NO_DESC_AVAILABLE	1412
-#define XST_USB_BUF_TOO_BIG		1413
-#define XST_USB_NO_BUF			1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429  *****************************/
-
-#define XST_HWICAP_WRITE_DONE		1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440  *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR		1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459  *********************/
-
-#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
-						 * programming
-						 */
-#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
-						 */
-#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
-						 * internal error.
-						 */
-#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
-						 * driver
-						 */
-#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
-						 */
-#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
-						 * operation aborted due to a
-						 * timeout
-						 */
-#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
-						 * addressible range
-						 */
-#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
-						 */
-#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
-						 * page of the device
-						 */
-#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
-						 */
-
-#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
-						 */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_status_codes".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xtime_l.h

@@ -1,104 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date     Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
-* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
-* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
-*						implementation
-* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR               XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET       0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET       0x04U
-#define GTIMER_CONTROL_OFFSET             0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND          (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#ifdef __GNUC__
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-#endif
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/

df_datalink/bsp/ps7_cortexa9_0/include/xuartps.h

@@ -1,517 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_5
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* <b>Initialization & Configuration</b>
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-*	 configuration structure provided by the caller. If running in a system
-*	 with address translation, the parameter EffectiveAddr should be the
-* 	  virtual address.
-*
-* <b>Baud Rate</b>
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. Ther input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-* <pre>
-*	baud_rate = input_clock / (bgen * (bdiv + 1)
-* </pre>
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* <b>Interrupts</b>
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* <b>Data Transfer</b>
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date	Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a	drg/jz 01/12/10 First Release
-* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
-*		        in XUartPs_SetFlowDelay where the value was not
-*			being written to the register.
-* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
-*			instance structure and the driver is updated to use
-*			InputClockHz parameter from the XUartPs_Config config
-*			structure.
-*			Added a parameter to XUartPs_Config structure which
-*			specifies whether the user has selected Modem pins
-*			to be connected to MIO or FMIO.
-*			Added the tcl file to generate the xparameters.h
-* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-*			with the correct values for CR 666724
-* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
-*			and XUARTPS_IXR_TTRIG.
-*			Modified the name of these defines
-*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk     08/22/13 Added API for uart reset and related
-*			constant definitions.
-* 2.0   hk      03/07/14 Version number revised.
-* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
-*                       baud rate. CR# 804281.
-* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
-*			Support for Zynq Ultrascale Mp added.
-* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
-*						platform variable in driver instance structure.
-* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
-*			uart is connected to a valid interrupt controller CR#946803.
-* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
-* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
-*                       examples to ensure that "Successfully ran" and "Failed"
-*                       strings are available in all examples. This is a fix
-*                       for CR-965028.
-*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
-*                       generation.
-* 3.6   ms     02/16/18 Updates the flow control mode offset value in modem
-*                       control register.
-* 3.7   aru    08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
-*
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H		/* prevent circular inclusions */
-#define XUARTPS_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE	 921600U
-#define XUARTPS_MIN_RATE	 110U
-
-#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified.  These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
-											 *	error detected */
-#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
-	u16 DeviceId;	 /**< Unique ID  of device */
-	u32 BaseAddress; /**< Base address of device (IPIF) */
-	u32 InputClockHz;/**< Input clock frequency */
-	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
-				 *  to MIO or FMIO */
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
-	u8 *NextBytePtr;
-	u32 RequestedBytes;
-	u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
-	u32 BaudRate;	/**< In bps, ie 1200 */
-	u32 DataBits;	/**< Number of data bits */
-	u32 Parity;		/**< Parity */
-	u8 StopBits;	/**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the handler, and is passed back to the upper layer
- *		when the handler is called. It is used to find the device driver
- *		instance.
- * @param	Event contains one of the event constants indicating events that
- *		have occurred.
- * @param	EventData contains the number of bytes sent or received at the
- *		time of the call for send and receive events and contains the
- *		modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
-				  u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
-	XUartPs_Config Config;	/* Configuration data structure */
-	u32 InputClockHz;	/* Input clock frequency */
-	u32 IsReady;		/* Device is initialized and ready */
-	u32 BaudRate;		/* Current baud rate */
-
-	XUartPsBuffer SendBuffer;
-	XUartPsBuffer ReceiveBuffer;
-
-	XUartPs_Handler Handler;
-	void *CallBackRef;	/* Callback reference for event handler */
-	u32 Platform;
-	u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr)   \
-	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	The value read from the register.
-*
-* @note		C-Style signature:
-*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr)  \
-	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-* @param	RegisterValue is the value to be written to the register.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
-   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
-			(u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
-   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
-	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
-	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return	None.
-*
-* @note		C-Style signature:
-*		void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
-   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
-	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
-	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param	InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*		- TRUE if a byte can be sent
-*		- FALSE if the Transmitter Fifo is not empty
-*
-* @note		C-Style signature:
-*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr)				\
-	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
-	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
-				  XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
-			   u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
-			   u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
-			 void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */