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feat: 根据HJSL硬件修改相关profile

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This commit is contained in:
josh
2025-05-13 15:45:59 +08:00
parent a24d8e8d35
commit 0c5fc1ec2b
14 changed files with 1360 additions and 956 deletions
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df_datalink_sp/src/dev_profile/ad9361_profile.c
+1 -1
View File
@@ -273,7 +273,7 @@ AD9361_InitParam ad9361_default_init_param = {
{
.device_id = AD9361_SPI_DEVICE_ID,
.mode = SPI_MODE_1,
.chip_select = AD9361_SPI_CS_AD9361_1,
.chip_select = AD9361_1_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
},
df_datalink_sp/src/dev_profile/ad9361_reg_profile.c
+86 -577
View File
@@ -25,7 +25,7 @@ static struct spi_init_param ad9361_1_reg_spi_init = {
.device_id = AD9361_SPI_DEVICE_ID,
.max_speed_hz = AD9361_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_1,
.chip_select = AD9361_SPI_CS_AD9361_1,
.chip_select = AD9361_1_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
@@ -35,6 +35,7 @@ static struct gpio_init_param ad9361_1_reg_gpio_resetb_init = {
.platform_ops = &xil_gpio_ops,
.extra = &xil_gpio_param
};
struct ad9361_reg_init_param ad9361_1_reg_default_init_param = {
/* SPI */
.spi_init = &ad9361_1_reg_spi_init,
@@ -46,7 +47,7 @@ static struct spi_init_param ad9361_2_reg_spi_init = {
.device_id = AD9361_SPI_DEVICE_ID,
.max_speed_hz = AD9361_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_1,
.chip_select = AD9361_SPI_CS_AD9361_2,
.chip_select = AD9361_2_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
@@ -56,6 +57,7 @@ static struct gpio_init_param ad9361_2_reg_gpio_resetb_init = {
.platform_ops = &xil_gpio_ops,
.extra = &xil_gpio_param
};
struct ad9361_reg_init_param ad9361_2_reg_default_init_param = {
/* SPI */
.spi_init = &ad9361_2_reg_spi_init,
@@ -72,7 +74,7 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
// generated using the AD9361 Customer software Version 2.1.3
//************************************************************
// Profile: Custom
// REFCLK_IN: 25.000 MHz
// REFCLK_IN: 40.000 MHz
status = ad9361_reg_write(dev, 0x03DF, 0x01); // Required for proper operation
@@ -87,527 +89,40 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
// Set BBPLL Frequency: 1152.000000
//************************************************************
status = ad9361_reg_write(dev, 0x0045, 0x03); // Set BBPLL reflclk scale to REFCLK * 2
status = ad9361_reg_write(dev, 0x0046, 0x03); // Set BBPLL Loop Filter Charge Pump current
status = ad9361_reg_write(dev, 0x0046, 0x02); // Set BBPLL Loop Filter Charge Pump current
status = ad9361_reg_write(dev, 0x0048, 0xE8); // Set BBPLL Loop Filter C1, R1
status = ad9361_reg_write(dev, 0x0049, 0x5B); // Set BBPLL Loop Filter R2, C2, C1
status = ad9361_reg_write(dev, 0x004A, 0x35); // Set BBPLL Loop Filter C3,R2
status = ad9361_reg_write(dev, 0x004B, 0xE0); // Allow calibration to occur and set cal count to 1024 for max accuracy
status = ad9361_reg_write(dev, 0x004E, 0x10); // Set calibration clock to REFCLK/4 for more accuracy
status = ad9361_reg_write(dev, 0x0043, 0x66); // BBPLL Freq Word (Fractional[7:0])
status = ad9361_reg_write(dev, 0x0042, 0x46); // BBPLL Freq Word (Fractional[15:8])
status = ad9361_reg_write(dev, 0x0041, 0x01); // BBPLL Freq Word (Fractional[23:16])
status = ad9361_reg_write(dev, 0x0044, 0x17); // BBPLL Freq Word (Integer[7:0])
status = ad9361_reg_write(dev, 0x0043, 0x00); // BBPLL Freq Word (Fractional[7:0])
status = ad9361_reg_write(dev, 0x0042, 0xC0); // BBPLL Freq Word (Fractional[15:8])
status = ad9361_reg_write(dev, 0x0041, 0x0C); // BBPLL Freq Word (Fractional[23:16])
status = ad9361_reg_write(dev, 0x0044, 0x0E); // BBPLL Freq Word (Integer[7:0])
status = ad9361_reg_write(dev, 0x003F, 0x05); // Start BBPLL Calibration
status = ad9361_reg_write(dev, 0x003F, 0x01); // Clear BBPLL start calibration bit
status = ad9361_reg_write(dev, 0x004C, 0x86); // Increase BBPLL KV and phase margin
status = ad9361_reg_write(dev, 0x004D, 0x01); // Increase BBPLL KV and phase margin
status = ad9361_reg_write(dev, 0x004D, 0x05); // Increase BBPLL KV and phase margin
// Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 276.480 us (Done when 0x05E[7]==1)
// Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 172.800 us (Done when 0x05E[7]==1)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x005E, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x80) != 0x80 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
status = ad9361_reg_write(dev, 0x0003, 0xE5); // Setup Rx Digital Filters/ Channels
status = ad9361_reg_write(dev, 0x0003, 0xE4); // Setup Rx Digital Filters/ Channels
status = ad9361_reg_write(dev, 0x0004, 0x03); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
status = ad9361_reg_write(dev, 0x000A, 0x12); // Set BBPLL post divide rate
//************************************************************
// Program Rx FIR: C:\Users\josh\Desktop\Config\rx64.txt
//************************************************************
status = ad9361_reg_write(dev, 0x00F5, 0x9A); // Enable clock to Rx FIR Filter
status = ad9361_reg_write(dev, 0x00F6, 0x02); // Write Filter Gain setting
status = ad9361_reg_write(dev, 0x00F0, 0x00); // Write FIR coefficient address
status = ad9361_reg_write(dev, 0x00F1, 0x00); // Write FIR coefficient data[7:0]
status = ad9361_reg_write(dev, 0x00F2, 0x00); // Write FIR coefficient data[15:8]
status = ad9361_reg_write(dev, 0x00F5, 0x9E); // Set Write EN to push data into FIR filter register map
status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us
status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us
status = ad9361_reg_write(dev, 0x00F0, 0x01);
status = ad9361_reg_write(dev, 0x00F1, 0xB6);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x02);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x03);
status = ad9361_reg_write(dev, 0x00F1, 0xEA);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x04);
status = ad9361_reg_write(dev, 0x00F1, 0x61);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x05);
status = ad9361_reg_write(dev, 0x00F1, 0xA3);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x06);
status = ad9361_reg_write(dev, 0x00F1, 0x4D);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x07);
status = ad9361_reg_write(dev, 0x00F1, 0x77);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x08);
status = ad9361_reg_write(dev, 0x00F1, 0xD5);
status = ad9361_reg_write(dev, 0x00F2, 0xFE);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x09);
status = ad9361_reg_write(dev, 0x00F1, 0x38);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0A);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0B);
status = ad9361_reg_write(dev, 0x00F1, 0xF8);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0C);
status = ad9361_reg_write(dev, 0x00F1, 0xAD);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0D);
status = ad9361_reg_write(dev, 0x00F1, 0x75);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0E);
status = ad9361_reg_write(dev, 0x00F1, 0xFD);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0F);
status = ad9361_reg_write(dev, 0x00F1, 0xD8);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x10);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x11);
status = ad9361_reg_write(dev, 0x00F1, 0x3A);
status = ad9361_reg_write(dev, 0x00F2, 0x04);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x12);
status = ad9361_reg_write(dev, 0x00F1, 0x6B);
status = ad9361_reg_write(dev, 0x00F2, 0x05);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x13);
status = ad9361_reg_write(dev, 0x00F1, 0x51);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x14);
status = ad9361_reg_write(dev, 0x00F1, 0x80);
status = ad9361_reg_write(dev, 0x00F2, 0xFA);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x15);
status = ad9361_reg_write(dev, 0x00F1, 0x34);
status = ad9361_reg_write(dev, 0x00F2, 0xF7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x16);
status = ad9361_reg_write(dev, 0x00F1, 0x08);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x17);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x06);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x18);
status = ad9361_reg_write(dev, 0x00F1, 0x1A);
status = ad9361_reg_write(dev, 0x00F2, 0x0E);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x19);
status = ad9361_reg_write(dev, 0x00F1, 0x44);
status = ad9361_reg_write(dev, 0x00F2, 0x09);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1A);
status = ad9361_reg_write(dev, 0x00F1, 0x54);
status = ad9361_reg_write(dev, 0x00F2, 0xF8);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1B);
status = ad9361_reg_write(dev, 0x00F1, 0xD1);
status = ad9361_reg_write(dev, 0x00F2, 0xE7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1C);
status = ad9361_reg_write(dev, 0x00F1, 0xC2);
status = ad9361_reg_write(dev, 0x00F2, 0xE9);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1D);
status = ad9361_reg_write(dev, 0x00F1, 0x4F);
status = ad9361_reg_write(dev, 0x00F2, 0x08);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1E);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x3B);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1F);
status = ad9361_reg_write(dev, 0x00F1, 0x2A);
status = ad9361_reg_write(dev, 0x00F2, 0x6C);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x20);
status = ad9361_reg_write(dev, 0x00F1, 0xFF);
status = ad9361_reg_write(dev, 0x00F2, 0x7F);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x21);
status = ad9361_reg_write(dev, 0x00F1, 0x2A);
status = ad9361_reg_write(dev, 0x00F2, 0x6C);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x22);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x3B);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x23);
status = ad9361_reg_write(dev, 0x00F1, 0x4F);
status = ad9361_reg_write(dev, 0x00F2, 0x08);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x24);
status = ad9361_reg_write(dev, 0x00F1, 0xC2);
status = ad9361_reg_write(dev, 0x00F2, 0xE9);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x25);
status = ad9361_reg_write(dev, 0x00F1, 0xD1);
status = ad9361_reg_write(dev, 0x00F2, 0xE7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x26);
status = ad9361_reg_write(dev, 0x00F1, 0x54);
status = ad9361_reg_write(dev, 0x00F2, 0xF8);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x27);
status = ad9361_reg_write(dev, 0x00F1, 0x44);
status = ad9361_reg_write(dev, 0x00F2, 0x09);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x28);
status = ad9361_reg_write(dev, 0x00F1, 0x1A);
status = ad9361_reg_write(dev, 0x00F2, 0x0E);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x29);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x06);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2A);
status = ad9361_reg_write(dev, 0x00F1, 0x08);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2B);
status = ad9361_reg_write(dev, 0x00F1, 0x34);
status = ad9361_reg_write(dev, 0x00F2, 0xF7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2C);
status = ad9361_reg_write(dev, 0x00F1, 0x80);
status = ad9361_reg_write(dev, 0x00F2, 0xFA);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2D);
status = ad9361_reg_write(dev, 0x00F1, 0x51);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2E);
status = ad9361_reg_write(dev, 0x00F1, 0x6B);
status = ad9361_reg_write(dev, 0x00F2, 0x05);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2F);
status = ad9361_reg_write(dev, 0x00F1, 0x3A);
status = ad9361_reg_write(dev, 0x00F2, 0x04);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x30);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x31);
status = ad9361_reg_write(dev, 0x00F1, 0xD8);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x32);
status = ad9361_reg_write(dev, 0x00F1, 0xFD);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x33);
status = ad9361_reg_write(dev, 0x00F1, 0x75);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x34);
status = ad9361_reg_write(dev, 0x00F1, 0xAD);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x35);
status = ad9361_reg_write(dev, 0x00F1, 0xF8);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x36);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x37);
status = ad9361_reg_write(dev, 0x00F1, 0x38);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x38);
status = ad9361_reg_write(dev, 0x00F1, 0xD5);
status = ad9361_reg_write(dev, 0x00F2, 0xFE);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x39);
status = ad9361_reg_write(dev, 0x00F1, 0x77);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3A);
status = ad9361_reg_write(dev, 0x00F1, 0x4D);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3B);
status = ad9361_reg_write(dev, 0x00F1, 0xA3);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3C);
status = ad9361_reg_write(dev, 0x00F1, 0x61);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3D);
status = ad9361_reg_write(dev, 0x00F1, 0xEA);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3E);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3F);
status = ad9361_reg_write(dev, 0x00F1, 0xB6);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x40);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x41);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x42);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x43);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x44);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x45);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x46);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x47);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x48);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x49);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4A);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4B);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4C);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4D);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4E);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4F);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x98); // Disable clock to Rx Filter
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
status = ad9361_reg_write(dev, 0x0010, 0xC8); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
status = ad9361_reg_write(dev, 0x0010, 0xCC); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data)
@@ -646,7 +161,7 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
//************************************************************
// Setup GPO
//************************************************************
status = ad9361_reg_write(dev, 0x003A, 0x18); // Set number of REFCLK cycles for 1us delay timer
status = ad9361_reg_write(dev, 0x003A, 0x27); // Set number of REFCLK cycles for 1us delay timer
status = ad9361_reg_write(dev, 0x0020, 0x00); // GPO Auto Enable Setup in RX and TX
status = ad9361_reg_write(dev, 0x0027, 0x00); // GPO Manual and GPO auto value in ALERT
status = ad9361_reg_write(dev, 0x0028, 0x00); // GPO_0 RX Delay
@@ -683,74 +198,74 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x023D, 0x04); // Start RX CP cal
// Wait for CP cal to complete, Max RXCP Cal time: 737.280 (us)(Done when 0x244[7]==1)
// Wait for CP cal to complete, Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x0244, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x80) != 0x80 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x027D, 0x04); // Start TX CP cal
// Wait for CP cal to complete, Max TXCP Cal time: 737.280 (us)(Done when 0x284[7]==1)
// Wait for CP cal to complete, Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x0284, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x80) != 0x80 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x023D, 0x00); // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT
status = ad9361_reg_write(dev, 0x027D, 0x00); // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT
//************************************************************
// FDD RX,TX Synth Frequency: 125.000000,4125.000000 MHz
// FDD RX,TX Synth Frequency: 1268.250000,1268.250000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************
status = ad9361_reg_write(dev, 0x023A, 0x4A); // Set VCO Output level[3:0]
status = ad9361_reg_write(dev, 0x0239, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
status = ad9361_reg_write(dev, 0x0242, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
status = ad9361_reg_write(dev, 0x0238, 0x78); // Set VCO Cal Offset[3:0]
status = ad9361_reg_write(dev, 0x0239, 0xC0); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
status = ad9361_reg_write(dev, 0x0242, 0x0D); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
status = ad9361_reg_write(dev, 0x0238, 0x70); // Set VCO Cal Offset[3:0]
status = ad9361_reg_write(dev, 0x0245, 0x00); // Set VCO Cal Ref Tcf[2:0]
status = ad9361_reg_write(dev, 0x0251, 0x0B); // Set VCO Varactor Reference[3:0]
status = ad9361_reg_write(dev, 0x0251, 0x09); // Set VCO Varactor Reference[3:0]
status = ad9361_reg_write(dev, 0x0250, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
status = ad9361_reg_write(dev, 0x023B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
status = ad9361_reg_write(dev, 0x023E, 0xF4); // Set Synth Loop Filter C2 and C1
status = ad9361_reg_write(dev, 0x023B, 0x8F); // Set Synth Loop Filter charge pump current (Icp)
status = ad9361_reg_write(dev, 0x023E, 0xD4); // Set Synth Loop Filter C2 and C1
status = ad9361_reg_write(dev, 0x023F, 0xDF); // Set Synth Loop Filter R1 and C3
status = ad9361_reg_write(dev, 0x0240, 0x0A); // Set Synth Loop Filter R3
status = ad9361_reg_write(dev, 0x0240, 0x09); // Set Synth Loop Filter R3
//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************
status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
status = ad9361_reg_write(dev, 0x0279, 0xC0); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
status = ad9361_reg_write(dev, 0x0282, 0x0D); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
status = ad9361_reg_write(dev, 0x0278, 0x70); // Set VCO Cal Offset[3:0]
status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
status = ad9361_reg_write(dev, 0x0291, 0x09); // Set VCO Varactor Reference[3:0]
status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
status = ad9361_reg_write(dev, 0x027B, 0x8F); // Set Synth Loop Filter charge pump current (Icp)
status = ad9361_reg_write(dev, 0x027E, 0xD4); // Set Synth Loop Filter C2 and C1
status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
status = ad9361_reg_write(dev, 0x0280, 0x09); // Set Synth Loop Filter R3
//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************
status = ad9361_reg_write(dev, 0x0233, 0x00); // Write Rx Synth Fractional Freq Word[7:0]
status = ad9361_reg_write(dev, 0x0234, 0x00); // Write Rx Synth Fractional Freq Word[15:8]
status = ad9361_reg_write(dev, 0x0235, 0x00); // Write Rx Synth Fractional Freq Word[22:16]
status = ad9361_reg_write(dev, 0x0233, 0x8D); // Write Rx Synth Fractional Freq Word[7:0]
status = ad9361_reg_write(dev, 0x0234, 0x99); // Write Rx Synth Fractional Freq Word[15:8]
status = ad9361_reg_write(dev, 0x0235, 0x69); // Write Rx Synth Fractional Freq Word[22:16]
status = ad9361_reg_write(dev, 0x0232, 0x00); // Write Rx Synth Integer Freq Word[10:8]
status = ad9361_reg_write(dev, 0x0231, 0xA0); // Write Rx Synth Integer Freq Word[7:0]
status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting
status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
status = ad9361_reg_write(dev, 0x0231, 0x7E); // Write Rx Synth Integer Freq Word[7:0]
status = ad9361_reg_write(dev, 0x0005, 0x22); // Set LO divider setting
status = ad9361_reg_write(dev, 0x0273, 0x8D); // Write Tx Synth Fractional Freq Word[7:0]
status = ad9361_reg_write(dev, 0x0274, 0x99); // Write Tx Synth Fractional Freq Word[15:8]
status = ad9361_reg_write(dev, 0x0275, 0x69); // Write Tx Synth Fractional Freq Word[22:16]
status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting
status = ad9361_reg_write(dev, 0x0271, 0x7E); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
status = ad9361_reg_write(dev, 0x0005, 0x22); // Set LO divider setting
//************************************************************
// Program Mixer GM Sub-table
@@ -1542,12 +1057,12 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x011A, 0x27); // Initial LMT Gain Limit
status = ad9361_reg_write(dev, 0x0081, 0x00); // Tx Symbol Gain Control
//************************************************************
// RX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter
// Corner @ 10.500000 MHz)
// RX Baseband Filter Tuning (Real BW: 20.000000 MHz) 3dB Filter
// Corner @ 28.000000 MHz)
//************************************************************
status = ad9361_reg_write(dev, 0x01FB, 0x07); // RX Freq Corner (MHz)
status = ad9361_reg_write(dev, 0x01FC, 0x40); // RX Freq Corner (Khz)
status = ad9361_reg_write(dev, 0x01F8, 0x0D); // Rx BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x01FB, 0x14); // RX Freq Corner (MHz)
status = ad9361_reg_write(dev, 0x01FC, 0x00); // RX Freq Corner (Khz)
status = ad9361_reg_write(dev, 0x01F8, 0x05); // Rx BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x01F9, 0x1E); // RX BBF Tune Divider[8]
status = ad9361_reg_write(dev, 0x01D5, 0x3F); // Set Rx Mix LO CM
@@ -1556,56 +1071,56 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x01E3, 0x02); // Enable Rx2 Filter Tuner
status = ad9361_reg_write(dev, 0x0016, 0x80); // Start RX Filter Tune
// Wait for RX filter to tune, Max Cal Time: 6.884 us (Done when 0x016[7]==0)
// Wait for RX filter to tune, Max Cal Time: 2.648 us (Done when 0x016[7]==0)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x0016, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x80) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x80) != 0x00 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x01E2, 0x03); // Disable Rx Filter Tuner (Rx1)
status = ad9361_reg_write(dev, 0x01E3, 0x03); // Disable Rx Filter Tuner (Rx2)
//************************************************************
// TX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter
// Corner @ 12.000000 MHz)
// TX Baseband Filter Tuning (Real BW: 20.000000 MHz) 3dB Filter
// Corner @ 32.000000 MHz)
//************************************************************
status = ad9361_reg_write(dev, 0x00D6, 0x0B); // TX BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x00D6, 0x04); // TX BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x00D7, 0x1E); // TX BBF Tune Divider[8]
status = ad9361_reg_write(dev, 0x00CA, 0x22); // Enable Tx Filter Tuner
status = ad9361_reg_write(dev, 0x0016, 0x40); // Start Tx Filter Tune
// Wait for TX filter to tune, Max Cal Time: 3.390 us (Done when 0x016[6]==0)
// Wait for TX filter to tune, Max Cal Time: 1.233 us (Done when 0x016[6]==0)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x0016, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x40) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x40) != 0x00 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x00CA, 0x26); // Disable Tx Filter Tuner (Both Channels)
//************************************************************
// RX TIA Setup: Setup values scale based on RxBBF calibration
// results. See information in Calibration Guide.
//************************************************************
status = ad9361_reg_write(dev, 0x01DB, 0x60); // Set TIA selcc[2:0]
status = ad9361_reg_write(dev, 0x01DB, 0x20); // Set TIA selcc[2:0]
status = ad9361_reg_write(dev, 0x01DD, 0x00); // Set RX TIA1 C MSB[6:0]
status = ad9361_reg_write(dev, 0x01DF, 0x00); // Set RX TIA2 C MSB[6:0]
status = ad9361_reg_write(dev, 0x01DC, 0x72); // Set RX TIA1 C LSB[5:0]
status = ad9361_reg_write(dev, 0x01DE, 0x72); // Set RX TIA2 C LSB[5:0]
status = ad9361_reg_write(dev, 0x01DC, 0x47); // Set RX TIA1 C LSB[5:0]
status = ad9361_reg_write(dev, 0x01DE, 0x47); // Set RX TIA2 C LSB[5:0]
//************************************************************
// TX Secondary Filter Calibration Setup: Real Bandwidth
// 7.500000MHz, 3dB Corner @ 37.500000MHz
// 20.000000MHz, 3dB Corner @ 100.000000MHz
//************************************************************
status = ad9361_reg_write(dev, 0x00D2, 0x1E); // TX Secondary Filter PDF Cap cal[5:0]
status = ad9361_reg_write(dev, 0x00D2, 0x04); // TX Secondary Filter PDF Cap cal[5:0]
status = ad9361_reg_write(dev, 0x00D1, 0x0C); // TX Secondary Filter PDF Res cal[3:0]
status = ad9361_reg_write(dev, 0x00D0, 0x56); // Pdampbias
status = ad9361_reg_write(dev, 0x00D0, 0x57); // Pdampbias
//************************************************************
// ADC Setup: Tune ADC Performance based on RX analog filter tune
// corner. Real Bandwidth: 6.982753 MHz, ADC Clock Frequency:
// corner. Real Bandwidth: 18.155158 MHz, ADC Clock Frequency:
// 288.000000 MHz. The values in registers 0x200 - 0x227 need to be
// calculated using the equations in the Calibration Guide.
//************************************************************
@@ -1617,23 +1132,23 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x0204, 0x24);
status = ad9361_reg_write(dev, 0x0205, 0x00);
status = ad9361_reg_write(dev, 0x0206, 0x00);
status = ad9361_reg_write(dev, 0x0207, 0x7C);
status = ad9361_reg_write(dev, 0x0208, 0x46);
status = ad9361_reg_write(dev, 0x0209, 0x3C);
status = ad9361_reg_write(dev, 0x020A, 0x4C);
status = ad9361_reg_write(dev, 0x020B, 0x2C);
status = ad9361_reg_write(dev, 0x020C, 0x4F);
status = ad9361_reg_write(dev, 0x020D, 0x2A);
status = ad9361_reg_write(dev, 0x0207, 0x67);
status = ad9361_reg_write(dev, 0x0208, 0x55);
status = ad9361_reg_write(dev, 0x0209, 0x31);
status = ad9361_reg_write(dev, 0x020A, 0x3E);
status = ad9361_reg_write(dev, 0x020B, 0x35);
status = ad9361_reg_write(dev, 0x020C, 0x41);
status = ad9361_reg_write(dev, 0x020D, 0x34);
status = ad9361_reg_write(dev, 0x020E, 0x00);
status = ad9361_reg_write(dev, 0x020F, 0x7F);
status = ad9361_reg_write(dev, 0x0210, 0x7F);
status = ad9361_reg_write(dev, 0x0211, 0x7F);
status = ad9361_reg_write(dev, 0x0212, 0x4A);
status = ad9361_reg_write(dev, 0x0213, 0x4A);
status = ad9361_reg_write(dev, 0x0214, 0x4A);
status = ad9361_reg_write(dev, 0x0215, 0x4D);
status = ad9361_reg_write(dev, 0x0216, 0x4D);
status = ad9361_reg_write(dev, 0x0217, 0x4D);
status = ad9361_reg_write(dev, 0x020F, 0x6A);
status = ad9361_reg_write(dev, 0x0210, 0x6A);
status = ad9361_reg_write(dev, 0x0211, 0x6A);
status = ad9361_reg_write(dev, 0x0212, 0x3C);
status = ad9361_reg_write(dev, 0x0213, 0x3C);
status = ad9361_reg_write(dev, 0x0214, 0x3C);
status = ad9361_reg_write(dev, 0x0215, 0x3F);
status = ad9361_reg_write(dev, 0x0216, 0x3F);
status = ad9361_reg_write(dev, 0x0217, 0x3F);
status = ad9361_reg_write(dev, 0x0218, 0x2E);
status = ad9361_reg_write(dev, 0x0219, 0x9C);
status = ad9361_reg_write(dev, 0x021A, 0x1F);
@@ -1664,7 +1179,7 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status |= ad9361_reg_read(dev, 0x0016, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x01) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x0185, 0x20); // Set RF DC offset Wait Count
status = ad9361_reg_write(dev, 0x0186, 0x32); // Set RF DC Offset Count[7:0]
@@ -1680,21 +1195,21 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status |= ad9361_reg_read(dev, 0x0016, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x01) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH);
//************************************************************
// Tx Quadrature Calibration Settings
//************************************************************
status = ad9361_reg_write(dev, 0x00A0, 0x15); // Set TxQuadcal NCO frequency
status = ad9361_reg_write(dev, 0x00A3, 0x00); // Set TxQuadcal NCO frequency (Only update bits [7:6])
status = ad9361_reg_write(dev, 0x00A0, 0x5F); // Set TxQuadcal NCO frequency
status = ad9361_reg_write(dev, 0x00A3, 0x80); // Set TxQuadcal NCO frequency (Only update bits [7:6])
status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
@@ -1705,7 +1220,7 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status |= ad9361_reg_read(dev, 0x0016, &value);
mdelay(1);// Wait 1ms
time_out_cnt++;
} while((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
} while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH);
status = ad9361_reg_write(dev, 0x016A, 0x75); // Set Kexp Phase
status = ad9361_reg_write(dev, 0x016B, 0x95); // Set Kexp Amplitude & Prevent Positive Gain Bit
@@ -1736,11 +1251,5 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x0158, 0x0D); // RSSI Mode Select
status = ad9361_reg_write(dev, 0x015C, 0x67); // Power Measurement Duration
//************************************************************
// Enable External LO & External VCO Buffer
//************************************************************
status |= ad9361_reg_write(dev, 0x0005, 0x07);
status |= ad9361_reg_write(dev, 0x0057, 0x1C);
return status;
}
df_datalink_sp/src/dev_profile/ad9528_profile.c
+134
View File
@@ -0,0 +1,134 @@
#include "dev_profile.h"
#include "../config/app_config.h"
#include "../drivers/platform/xilinx_gpio.h"
#include "../drivers/axi_core/spi_engine/spi_engine.h"
#include "../drivers/frequency/ad9528/ad9528.h"
static struct spi_engine_init_param spi_engine_param = {
.ref_clk_hz = AD9528_SPI_ENGINE_REF_CLK,
.type = SPI_ENGINE,
.spi_engine_baseaddr = AD9528_SPI_ENGINE_BASEADDR,
.cs_delay = AD9528_SPI_ENGINE_CS_DELAY,
.data_width = AD9528_SPI_ENGINE_DATA_WIDTH
};
static struct xil_gpio_init_param xil_gpio_param = {
.type = GPIO_PS,
.device_id = AD9528_GPIO_DEVICE_ID
};
static struct spi_init_param ad9528_spi_init = {
.device_id = AD9528_SPI_DEVICE_ID,
.max_speed_hz = AD9528_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_0,
.chip_select = AD9528_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
static struct gpio_init_param ad9528_gpio_resetb_init = {
.number = AD9528_RESETB,
.platform_ops = &xil_gpio_ops,
.extra = &xil_gpio_param
};
static struct gpio_init_param ad9528_gpio_sysref_req_init = {
.number = AD9528_SYSREF_REQ,
.platform_ops = &xil_gpio_ops,
.extra = &xil_gpio_param
};
static ad9528pll1Settings_t clockPll1Settings = {
.refA_Frequency_Hz = 50000000,
.refA_Divider = 1,
.refA_bufferCtrl = SINGLE_ENDED,
.refB_Frequency_Hz = 0,
.refB_Divider = 1,
.refB_bufferCtrl = DISABLED,
.vcxo_Frequency_Hz = 50000000,
.vcxoBufferCtrl = SINGLE_ENDED,
.nDivider = 1
};
static ad9528pll2Settings_t clockPll2Settings = {
.rfDivider = 4,
.n2Divider = 20,
.totalNdiv = 80
};
/*******************************************************************
* Output Distribution Settings
* 9369CE02A uses the following clock outputs
* OUT 1: FPGA REFCLK
* OUT 3: FPGA SYSREF
* OUT 12: DUT SYSREF
* OUT 13: DUT REFCLK
*******************************************************************
*/
static ad9528outputSettings_t clockOutputSettings = {
.outPowerDown = 0xE001,
.outSource = {
AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV,
AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV,
AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV
},
.outBufferCtrl = {
0,0,0,0,0,
0,0,0,0,0,
0,0,0,0
},
.outAnalogDelay = {
0,0,0,0,0,
0,0,0,0,0,
0,0,0,0
},
.outDigitalDelay = {
0,0,0,0,0,
0,0,0,0,0,
0,0,0,0
},
.outChannelDiv = {
5,25,25,5,5,
5,5,8,5,5,
5,5,10,5
},
.outFrequency_Hz = {
200e6, 40e6, 40e6, 200e6, 200e6,
200e6, 200e6, 125e6, 200e6, 200e6,
200e6, 200e6, 100e6, 200e6
}
};
static ad9528sysrefSettings_t clockSysrefSettings = {
.sysrefRequestMethod = PIN,
.sysrefSource = INTERNAL,
.sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH,
.sysrefPinBufferMode = DISABLED,
.sysrefPatternMode = CONTINUOUS,
.sysrefNshotMode = FOUR_PULSES,
.sysrefDivide = 256
};
static ad9528spiSettings_t clockSpiSettings = {
.chipSelectIndex = AD9528_SPI_CS, //chip select Index, not used
.writeBitPolarity = 0, //Write bit polarity
.longInstructionWord = 1, //16bit instruction word
.MSBFirst = 1, //MSB first
.CPHA = 0, //Clock phase
.CPOL = 0, //Clock polarity
.enSpiStreaming = 0, //uint8_t enSpiStreaming;
.autoIncAddrUp = 1, //uint8_t autoIncAddrUp;
.fourWireMode = 1 //uint8_t fourWireMode;
};
ad9528Init_t ad9528_default_init_param = {
/* SPI */
.spi_init = &ad9528_spi_init,
.gpio_init_resetb = &ad9528_gpio_resetb_init,
.gpio_init_sysref_req = &ad9528_gpio_sysref_req_init,
.spiSettings = &clockSpiSettings,
.pll1Settings = &clockPll1Settings,
.pll2Settings = &clockPll2Settings,
.outputSettings = &clockOutputSettings,
.sysrefSettings = &clockSysrefSettings
};
df_datalink_sp/src/dev_profile/dev_profile.h
+4
View File
@@ -6,6 +6,7 @@
#include "../drivers/rf-transceiver/ad9361/ad9361_api.h"
#include "../drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
#include "../drivers/frequency/hmc7044/hmc7044.h"
#include "../drivers/frequency/ad9528/ad9528.h"
#include "../drivers/adc/ad9694/ad9694.h"
#include "../config/app_config.h"
@@ -17,6 +18,9 @@ extern struct global_timer_init_param globaltimer_init_param;
// HMC7044
extern struct hmc7044_init_param hmc7044_default_init_param;
// AD9528
extern ad9528Init_t ad9528_default_init_param;
// AD9361
extern AD9361_InitParam ad9361_default_init_param;
extern AD9361_RXFIRConfig rx_fir_config;
df_datalink_sp/src/dev_profile/hmc7044_profile.c
+9 -9
View File
@@ -23,7 +23,7 @@ static struct spi_init_param hmc7044_spi_init_param = {
.device_id = HMC7044_SPI_DEVICE_ID,
.max_speed_hz = HMC7044_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_4,
.chip_select = HMC7044_SPI_CS_HMC7044,
.chip_select = HMC7044_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
@@ -42,9 +42,9 @@ struct hmc7044_chan_spec hmc7044_chan_spec[4] = {
.dynamic_driver_enable = false,
.output_control0_rb4_enable = true,
.force_mute_enable = false,
.driver_mode = CML,
.driver_mode = HMC7044_CML,
.driver_impedance = INTERNAL_100OHM_PER_PIN,
.out_mux_mode = CHANNEL_DIV
.out_mux_mode = HMC7044_CHANNEL_DIV
},
/* FPGA_DAC_LOGIC_CLK */
{
@@ -58,9 +58,9 @@ struct hmc7044_chan_spec hmc7044_chan_spec[4] = {
.dynamic_driver_enable = false,
.output_control0_rb4_enable = true,
.force_mute_enable = false,
.driver_mode = CML,
.driver_mode = HMC7044_CML,
.driver_impedance = INTERNAL_100OHM_PER_PIN,
.out_mux_mode = CHANNEL_DIV
.out_mux_mode = HMC7044_CHANNEL_DIV
},
/* B_AD9361_XTAL */
{
@@ -74,9 +74,9 @@ struct hmc7044_chan_spec hmc7044_chan_spec[4] = {
.dynamic_driver_enable = false,
.output_control0_rb4_enable = true,
.force_mute_enable = false,
.driver_mode = CML,
.driver_mode = HMC7044_CML,
.driver_impedance = INTERNAL_100OHM_PER_PIN,
.out_mux_mode = CHANNEL_DIV
.out_mux_mode = HMC7044_CHANNEL_DIV
},
/* AD9361_RX_EXT_LO */
{
@@ -90,9 +90,9 @@ struct hmc7044_chan_spec hmc7044_chan_spec[4] = {
.dynamic_driver_enable = false,
.output_control0_rb4_enable = true,
.force_mute_enable = false,
.driver_mode = CML,
.driver_mode = HMC7044_CML,
.driver_impedance = INTERNAL_100OHM_PER_PIN,
.out_mux_mode = CHANNEL_DIV
.out_mux_mode = HMC7044_CHANNEL_DIV
},
};