forked from 0xha0/datalink_repo
310 lines
9.6 KiB
C
310 lines
9.6 KiB
C
/*****************************************************************************/
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/**
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* Description: Inter-Communication protocol, definitions and function
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* prototypes.
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*
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* Date: 2022-06-18 16:37
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* LastEditTime: 2023-04-24 17:38
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* Revisions: Rev 0.2
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* History:
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* [2022-06-18]: Initial version.
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* [2023-04-24]: Bug fix:
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* - Read frame type from PL status register.
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*
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* Copyright(c) 2022 Beijing Institute of Technology.
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* Lab of Communication and Networking
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*
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******************************************************************************/
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#ifndef INTER_COMM_H_
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#define INTER_COMM_H_
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/***************************** Include Files *********************************/
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#include <stdint.h>
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#include "../phy_ctrl/phy_ctrl.h"
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#include "xsysmon.h"
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#include "../config/app_config.h"
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/************************** Constant Definitions *****************************/
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#define COMMON_CRC_LEN 2
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#define INTER_MSG_LEN 512 //Byte
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#define INTER_MSG_CRC_LEN 2
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#define INTER_MSG_LEN_NONE UINT32_MAX
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#define TYPE_CODE_OFFSET 0x0000
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// self test request
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#define INTER_MSG_ST_REQ_LEN 0x00006
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#define INTER_MSG_ST_REQ_CODE 0x0011
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#define ST_CMD_OFFSET 0x0002
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#define ST_CMD_LEN 0x0002
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#define ST_CMD 0x1111
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// self test response
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#define INTER_MSG_ST_RSP_LEN 0x0008
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#define INTER_MSG_ST_RSP_CODE 0x0021
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#define ST_RSP_STATE_OFFSET 0x0002
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#define ST_RSP_STATE_LEN 0x0002
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#define ST_RSP_STATE_OK 0xAAAA
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#define ST_RSP_STATE_ERR 0x5555
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#define ST_RSP_MASK1_OFFSET 0x0004
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#define ST_RSP_MASK1_LEN 0x0002
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#define ST_RSP_MASK2_OFFSET 0x0006
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#define ST_RSP_MASK2_LEN 0x0002
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// wake up requirement/response
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#define INTER_MSG_WAKE_REQ_LEN 0x0006
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#define INTER_MSG_WAKE_REQ_CODE 0x0012
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#define INTER_MSG_WAKE_RSP_LEN 0x0006
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#define INTER_MSG_WAKE_RSP_CODE 0x0022
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#define WAKE_CMD_OFFSET 0x0002
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#define WAKE_CMD_LEN 0x0002
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#define WAKE_CMD_LPW_LPW 0xFFAA
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#define WAKE_CMD_UP_LPW 0xAAAA
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#define WAKE_CMD_UP_UP 0xFFCC
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#define WAKE_CMD_LPW_UP 0xCCCC
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// mode swicth command
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#define INTER_MSG_MODESW_LEN 0x0016 // 20byte + crc
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#define INTER_MSG_MODESW_CODE 0x0041
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#define MODESW_START_TIME_OFFSET 0x0002
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#define MODESW_START_TIME_LEN 0x0008
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#define MODESW_TIMEOUT_OFFSET 0x000A
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#define MODESW_TIMEOUT_LEN 0x0008
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#define MODESW_MODE_OFFSET 0x0012
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#define MODESW_MODE_LEN 0x0002
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#define MODESW_MODE_NORMAL 0x0001
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#define MODESW_MODE_NETSET 0x0002
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// physical layer control
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#define INTER_MSG_CTRL_LEN 0x00BC // 186byte + 2byte crc
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#define INTER_MSG_CTRL_CODE 0x0013
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#define CTRL_TIME_OFFSET 0x0002
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#define CTRL_TIME_LEN 0x0008
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#define CTRL_FRAME_TYPE_OFFSET 0x000A
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#define CTRL_FRAME_TYPE_LEN 0x0001
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#define CTRL_FRAME_10K10MS 0x01
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#define CTRL_FRAME_10K20MS 0x02
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#define CTRL_FRAME_200K5MS 0x03
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#define CTRL_FRAME_1M25MS 0x04
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#define CTRL_FRAME_2K20MS 0x05
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#define CTRL_FRAME_2K100MS 0x06
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#define CTRL_FRAME_40K10MS 0x07
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#define CTRL_FRAME_40K20MS 0x08
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#define INTER_MSG_CTRL_ANT_OFFSET 0x000B
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#define INTER_MSG_CTRL_ANT_LEN 0x0001
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#define CTRL_ANT_ALL 0x3F
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#define CTRL_ANT_FRONT 0x01
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#define CTRL_ANT_3QUAD2 0x02
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#define CTRL_ANT_3QUAD4 0x04
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#define CTRL_ANT_BOTT 0x08
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#define CTRL_ANT_RSV1 0x10
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#define CTRL_ANT_RSV2 0x20
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#define INTER_MSG_CTRL_TOR_OFFSET 0x000C
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#define INTER_MSG_CTRL_TOR_LEN 0x0001
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#define CTRL_TOR_TX 0xAA
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#define CTRL_TOR_RX 0xCC
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#define INTER_MSG_CTRL_SW_OFFSET 0x000D
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#define INTER_MSG_CTRL_SW_LEN 0x0001
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#define CTRL_SW_PW BIT(0)
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#define CTRL_SW_TR BIT(1)
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#define CTRL_SW_TOR BIT(2)
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#define INTER_MSG_CTRL_HOP_MODE_OFFSET 0x000E
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#define INTER_MSG_CTRL_HOP_MODE_LEN 0x0002
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#define CTRL_HOP_PRESET 0x2222
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#define CTRL_HOP_CONFIG 0x5555
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#define INTER_MSG_CTRL_HOP_PATTERN_OFFSET 0x0010
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#define INTER_MSG_CTRL_HOP_PATTERN_LEN 0x00A2
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#define INTER_MSG_CTRL_BEAM_MODE_OFFSET 0x00B2
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#define INTER_MSG_CTRL_BEAM_MODE_LEN 0x0001
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#define BEAM_MODE_WIDE 0x51
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#define BEAM_MODE_NRW 0x52
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#define BEAM_MODE_SUBNRW 0x53
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#define INTER_MSG_CTRL_BEAM_NO_OFFSET 0x00B3
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#define INTER_MSG_CTRL_BEAM_NO_LEN 0x0001
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#define INTER_MSG_CTRL_AMP_WT_OFFSET 0x00B4
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#define INTER_MSG_CTRL_AMP_WT_LEN 0x0002
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#define INTER_MSG_CTRL_OFFAX_OFFSET 0x00B6
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#define INTER_MSG_CTRL_OFFAX_LEN 0x0002
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#define INTER_MSG_CTRL_RNDAX_OFFSET 0x00B8
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#define INTER_MSG_CTRL_RNDAX_LEN 0x0002
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// data segment write
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#define MSG_DSEGWR_SUBPKG_MAX 3
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#define INTER_MSG_DSEGWR_LEN 0x0200 //510 byte + 2byte crc
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#define INTER_MSG_DSEGWR_CODE 0x0014
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#define DSEGWR_TYPE_OFFSET 0x0002
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#define DSEGWR_TYPE_LEN 0x0002
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#define DSEGWR_TYPE_PKN 0x0010
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#define DSEGWR_TYPE_PK1 0x0012
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#define DSEGWR_TYPE_PK2 0x0013
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#define DSEGWR_TYPE_PK3 0x0014
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#define DSEGWR_TIME_OFFSET 0x0004
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#define DSEGWR_TIME_LEN 0x0008
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#define DSEGWR_PDLEN_OFFSET 0x000C
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#define DSEGWR_PDLEN_LEN 0x0002
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#define DSEGWR_PD_OFFSET 0x000E
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#define DSEGWR_PD_LEN 0x01F0
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// data segment read
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#define MSG_DSEGRD_SUBPKG_MAX 3
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#define INTER_MSG_DSEGRD_LEN 0x0200 //510 byte + 2byte crc
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#define INTER_MSG_DSEGRD_CODE 0x0023
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#define DSEGRD_TYPE_OFFSET 0x0002
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#define DSEGRD_TYPE_LEN 0x0001
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#define DSEGRD_TYPE_PKN 0x0010
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#define DSEGRD_TYPE_PK1 0x0012
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#define DSEGRD_TYPE_PK2 0x0013
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#define DSEGRD_TYPE_PK3 0x0014
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#define DSEGRD_TIME_OFFSET 0x0004
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#define DSEGRD_TIME_LEN 0x0008
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#define DSEGRD_DPL_OFFSET 0x000C
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#define DSEGRD_DPL_LEN 0x0008
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#define DSEGRD_PDLEN_OFFSET 0x0016
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#define DSEGRD_PDLEN_LEN 0x0002
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#define DSEGRD_IACQ_OFFSET 0x0014
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#define DSEGRD_IACQ_LEN 0x0001
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#define DSEGRD_IACQ_BEAM_OFFSET 0x0015
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#define DSEGRD_IACQ_BEAM_LEN 0x0001
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#define DSEGRD_PD_OFFSET 0x0018
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#define DSEGRD_PD_LEN 0x01E6
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// Remote state test.
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#define INTER_MSG_RT_LEN 0x0022 // 32 bytes + 2byte crc
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#define INTER_MSG_RT_CODE 0x0031 // remote test.
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#define RT_PHY_OFFSET 0x0002
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#define RT_PHY_LEN 0x0002
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#define RT_TIME_OFFSET 0x0004
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#define RT_TIME_LEN 0x0008
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#define RT_BEAM_OFFSET 0x000C
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#define RT_BEAM_LEN 0x0004
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#define RT_SP_VOLT_OFFSET 0x0010
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#define RT_SP_VOLT_LEN 0x0002
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#define RT_SP_TEMP_OFFSET 0x0012
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#define RT_SP_TEMP_LEN 0x0002
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#define RT_SP_CHIP_OFFSET 0x0014
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#define RT_SP_CHIP_LEN 0x0002
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#define RT_ANT_VOLT_OFFSET 0x0016
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#define RT_ANT_VOLT_LEN 0x0002
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#define RT_ANT_TEMP_OFFSET 0x0018
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#define RT_ANT_TEMP_LEN 0x0002
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#define RT_ANT_LOCK_OFFSET 0x001A
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#define RT_ANT_LOCK_LEN 0x0001
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#define RT_ANT_MGC_OFFSET 0x001C
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#define RT_ANT_MGC_LEN 0x0002
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#define RT_ANT_STATE_OFFSET 0x001E
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#define RT_ANT_STATE_LEN 0x0001
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#ifdef ANT_DEVICE_ID
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#if ANT_DEVICE_ID == 0x0000
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#define INTER_MSG_DSEGRD_PKN_ADDR 0x0001
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#define INTER_MSG_DSEGRD_PK1_ADDR 0x0001
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#define INTER_MSG_DSEGRD_PK2_ADDR 0x0002
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#define INTER_MSG_DSEGRD_PK3_ADDR 0x0003
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#define INTER_MSG_RT_ADDR 0x0004
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#define INTER_MSG_OTHER_ADDR 0x0005
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#elif ANT_DEVICE_ID == 0x0001
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#define INTER_MSG_DSEGRD_PKN_ADDR 0x0006
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#define INTER_MSG_DSEGRD_PK1_ADDR 0x0006
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#define INTER_MSG_DSEGRD_PK2_ADDR 0x0007
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#define INTER_MSG_DSEGRD_PK3_ADDR 0x0008
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#define INTER_MSG_RT_ADDR 0x0009
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#define INTER_MSG_OTHER_ADDR 0x000A
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#elif ANT_DEVICE_ID == 0x0002
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#define INTER_MSG_DSEGRD_PKN_ADDR 0x000B
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#define INTER_MSG_DSEGRD_PK1_ADDR 0x000B
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#define INTER_MSG_DSEGRD_PK2_ADDR 0x000C
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#define INTER_MSG_DSEGRD_PK3_ADDR 0x000D
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#define INTER_MSG_RT_ADDR 0x000E
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#define INTER_MSG_OTHER_ADDR 0x000F
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#elif ANT_DEVICE_ID == 0x0003
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#define INTER_MSG_DSEGRD_PKN_ADDR 0x0010
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#define INTER_MSG_DSEGRD_PK1_ADDR 0x0010
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#define INTER_MSG_DSEGRD_PK2_ADDR 0x0011
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#define INTER_MSG_DSEGRD_PK3_ADDR 0x0012
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#define INTER_MSG_RT_ADDR 0x0013
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#define INTER_MSG_OTHER_ADDR 0x0014
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#elif ANT_DEVICE_ID == 0x0004
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#define INTER_MSG_DSEGRD_PKN_ADDR 0x0015
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#define INTER_MSG_DSEGRD_PK1_ADDR 0x0015
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#define INTER_MSG_DSEGRD_PK2_ADDR 0x0016
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#define INTER_MSG_DSEGRD_PK3_ADDR 0x0017
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#define INTER_MSG_RT_ADDR 0x0018
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#define INTER_MSG_OTHER_ADDR 0x0019
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#elif ANT_DEVICE_ID == 0x0005
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#define INTER_MSG_DSEGRD_PKN_ADDR 0x001A
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#define INTER_MSG_DSEGRD_PK1_ADDR 0x001A
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#define INTER_MSG_DSEGRD_PK2_ADDR 0x001B
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#define INTER_MSG_DSEGRD_PK3_ADDR 0x001C
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#define INTER_MSG_RT_ADDR 0x001D
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#define INTER_MSG_OTHER_ADDR 0x001E
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#elif ANT_DEVICE_ID == 0x0006
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#else
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#error Cannot Eval Antenna ID...
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#endif
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#else
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#error Antenna ID must be specified...
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#endif
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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typedef struct{
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PHY_INST* phyInstPtr;
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int32_t (*data_send) (void* buffPtr, int32_t dataLen, uint16_t subAddr);
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int32_t (*data_recv) (void* buffPtr, int32_t dataLen);
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}INTER_COMM_CONFIG;
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// FIXME: only support ONE physical device now.
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typedef struct{
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uint8_t* recvBuff;
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uint8_t* sendBuff;
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bool isSleep;
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uint32_t rxRemain;
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uint32_t txRemain;
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uint64_t lastCtrlTimeTag;
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uint64_t lastDataTimeTag;
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uint64_t lastPhyTimeTag;
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PHY_INST* phyInstPtr;
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uint8_t* phyRecvBuff;
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uint8_t* phySendBuff;
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int32_t (*data_send) (void* buffPtr, int32_t dataLen, uint16_t subAddr);
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int32_t (*data_recv) (void* buffPtr, int32_t buffSize);
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}INTER_COMM_INST;
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typedef struct {
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uint16_t glinkSubAddr;
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uint8_t extra[14];
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} C2C_EXTRA;
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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int32_t InterComm_Init(INTER_COMM_INST** instPtr, INTER_COMM_CONFIG* configPtr);
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void InterComm_Destroy(INTER_COMM_INST* instPtr);
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int32_t InterComm_RecvMsg(INTER_COMM_INST* instPtr);
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int32_t InterComm_SendMsg(INTER_COMM_INST* instPtr, int32_t dataLen, uint16_t subAddr);
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int32_t InterComm_MsgHandler(INTER_COMM_INST* instPtr);
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int32_t InterComm_SendRemotCheck(INTER_COMM_INST* instPtr, XSysMon* SysMonInstPtr, C2C_EXTRA* c2cExtraBuffPtr);
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int32_t InterComm_PhyDataUpload(INTER_COMM_INST* instPtr);
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// Helper functions
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int AppendCrc(uint8_t* buffPtr, uint32_t dataLen);
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bool CrcCheck(uint8_t* buffPtr, uint32_t dataLen);
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#endif
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