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feat(sys): change speed to 3.125, test pass.

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ZoroGH
2024-09-05 20:42:30 +08:00
parent 5e8d69a0b0
commit 3990e3081a
12 changed files with 624 additions and 515 deletions
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hdl/PAPR.v
+101 -56
View File
@@ -36,19 +36,32 @@ module PAPR #(
);
localparam SUM_WIDTH = 32;
localparam CNT_START = 16; // 32*4 / 8 * mag_valid signal is active high per 8 clk
localparam CNT_END = 44; // 88*4 / 8
localparam PULSE_PERIOD = 50;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg [MAG_WIDTH-1:0] vec_mag_reserved;
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 7:0] cnt;
wire [MAG_WIDTH-1:0] data_avg;
reg [SUM_WIDTH-1:0] data_sum;
assign data_avg = data_sum[SUM_WIDTH-1:10];
reg mag_valid_d1;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg frame_sync_d1;
always @(posedge clk) begin
mag_valid_d1 <= mag_valid;
if (rst) begin
vec_mag_d1 <= 'd0;
vec_mag_d2 <= 'd0;
vec_mag_d3 <= 'd0;
vec_mag_d1 <= 0;
vec_mag_d2 <= 0;
vec_mag_d3 <= 0;
end
else if (mag_valid) begin
vec_mag_d1 <= vec_mag;
@@ -61,9 +74,7 @@ module PAPR #(
vec_mag_d3 <= vec_mag_d3;
end
end
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 5:0] cnt;
shift_reg #(
.DATA_WIDTH(MAG_WIDTH),
@@ -77,10 +88,9 @@ module PAPR #(
);
reg [SUM_WIDTH-1:0] data_sum;
always @(posedge clk) begin
if (rst) begin
data_sum <= 'd0;
data_sum <= 0;
end
else begin
if (mag_valid) begin
@@ -92,58 +102,93 @@ module PAPR #(
end
end
wire [MAG_WIDTH-1:0] data_avg;
assign data_avg = data_sum[SUM_WIDTH-1:10];
// FSM
reg [2:0] cs = 0;
reg [2:0] ns = 0;
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
0: begin
if (mag_valid && vec_mag_1024 != 'd0 && data_avg != 'd0 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
ns = 1;
end
end
1: begin
if (cnt == CNT_START - 1) begin
ns = 2;
end
end
2: begin
if (vec_mag_reserved < {vec_mag[MAG_WIDTH-3:0], 2'b0}) begin
ns = 0;
end
else if (cnt == CNT_END - 1) begin
ns = 3;
end
end
3: begin
// generate pulse
ns = 4;
end
4: begin
if (cnt == PULSE_PERIOD - 1) begin
ns = 0;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
frame_sync <= 1'd0;
if (cs == 0 && ns == 1) begin
vec_mag_reserved <= vec_mag_d2;
end
else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
frame_sync <= 1'd1;
end
else if (cnt == 6'b111111) begin
frame_sync <= 1'd0;
end
else begin
frame_sync <= frame_sync;
else if (cs == 0) begin
vec_mag_reserved <= 0;
end
end
always @(posedge clk) begin
if (cs == 1 || cs == 2) begin
if (mag_valid) begin
cnt <= cnt + 1;
end
end
else if (cs == 4) begin
cnt <= cnt + 1;
end
else if (cs == 0) begin
cnt <= 0;
end
end
always @(posedge clk) begin
frame_sync_pulse <= (cs == 3);
if (cs == 4) begin
frame_sync <= 1;
end
else begin
frame_sync <= frame_sync;
frame_sync <= 0;
end
end
always @(posedge clk) begin
frame_sync_d1 <= frame_sync;
if (frame_sync && ~frame_sync_d1) begin
frame_sync_pulse <= 1'd1;
end
else begin
frame_sync_pulse <= 1'd0;
end
end
always @(posedge clk) begin
if (rst) begin
cnt <= 6'd0;
end
else if (frame_sync && mag_valid_d1) begin
cnt <= cnt + 6'd1;
end
else if (cnt == 6'b111111) begin
cnt <= 6'd0;
end
end
ila_frame_sync u_ila_frame_sync (
.clk (clk), // input wire clk
.probe0(vec_mag), // input wire [21:0] probe0
.probe1(data_avg), // input wire [21:0] probe0
.probe2(frame_sync) // input wire [0:0] probe2
.clk (clk), // input wire clk
.probe0(vec_mag), // input wire [21:0] probe0
.probe1(data_avg), // input wire [21:0] probe0
.probe2(cs), // input wire [2:0] probe2
.probe3(cnt), // input wire [7:0] probe2
.probe4(frame_sync), // input wire [0:0] probe2
.probe5(vec_mag_reserved) // input wire [21:0] probe2
);
hdl/RecvTop.v
+225 -128
View File
@@ -22,6 +22,8 @@ module RecvTop (
input clk,
input clk_2x, // clk_2x
input clk_4x,
input clk_half, // clk_1/2
input clk_quarter, // clk_1/4
input rst,
input rst2, // TODO： delete the signal
// phy wave
@@ -30,7 +32,7 @@ module RecvTop (
// mgc control
output [ 3:0] ad9361_ctrl_in,
output wire flag_mgc_done_pulse, // active high pulse signal
output wire frame_sync_pulse, // in domain clk
output wire frame_sync_pulse_1x, // in domain clk
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
@@ -46,7 +48,9 @@ module RecvTop (
output wire [31:0] rx_data_src_fifo_tdata,
output wire rx_data_src_fifo_tlast,
input wire rx_data_src_fifo_tready,
output wire rx_data_src_fifo_tvalid
output wire rx_data_src_fifo_tvalid,
// ber
output reg err_flag_pos
);
wire rst_TimeSync;
@@ -119,7 +123,8 @@ module RecvTop (
reg [ 7:0] cnt_mgc_delay;
wire mgc_start;
wire flag_mgc_done; // level flag
wire mgc_start_quarter;
wire flag_mgc_done; // level flag, under clk_1x
wire flag_mgc_done_4x; // level flag
// startup delay
@@ -136,6 +141,7 @@ module RecvTop (
end
assign mgc_start = (cnt_mgc_delay == 8'hFE);
assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE);
// * MGC module
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
@@ -153,7 +159,7 @@ module RecvTop (
reg MF_rdy; // flag_mgc_done_d1
wire MF_rst; // flag_mgc_done_pulse_d2
always @(posedge clk) begin
always @(posedge clk_quarter) begin
if (rst) begin
MF_rdy <= 0;
end
@@ -164,16 +170,21 @@ module RecvTop (
wire fifo_out_valid;
reg [ 2:0] cnt_fifo_out_valid;
reg [ 2:0] cnt_fifo_out_valid_sel = 1; // 根据speed mode对应的计数器边界值
reg [ 2:0] cnt_fifo_out_valid_sel = 7; // 根据speed mode对应的计数器边界值 // refer to Receiver.v
wire [31:0] fifo_out;
reg dmf_s_valid;
wire dmf_tvalid_interp4_i;
wire dmf_tvalid_interp4_q;
wire [31:0] mf_data_interp4_i;
wire [31:0] mf_data_interp4_q;
wire [23:0] dmf_tdata_interp4_i;
wire [23:0] dmf_tdata_interp4_q;
wire dmf_tvalid_interp16_i;
wire dmf_tvalid_interp16_q;
wire [31:0] mf_data_interp16_i;
wire [31:0] mf_data_interp16_q;
wire [23:0] dmf_tdata_interp16_i;
wire [23:0] dmf_tdata_interp16_q;
// in domain clk_quarter
wire [ 9:0] mf_data_downsample_i;
wire [ 9:0] mf_data_downsample_q;
// valid signal for dmf
always @(posedge clk_4x) begin
@@ -211,70 +222,107 @@ module RecvTop (
wire mf_fir_s_tready_q;
// Match filter
fir_match_interp4 u_fir_match_filter_interp4_i (
// fir_match_interp4 u_fir_match_filter_interp4_i (
// .aclk (clk), // input wire aclk
// .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
// .s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
// .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
// .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
// );
// fir_match_interp4 u_fir_match_filter_interp4_q (
// .aclk (clk), // input wire aclk
// .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
// .s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
// .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
// .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
// );
fir_match_interp16 u_fir_match_filter_interp16_i (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
.m_axis_data_tdata (mf_data_interp16_i) // output wire [31 : 0] m_axis_data_tdata
);
fir_match_interp4 u_fir_match_filter_interp4_q (
fir_match_interp16 u_fir_match_filter_interp16_q (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
.m_axis_data_tdata (mf_data_interp16_q) // output wire [31 : 0] m_axis_data_tdata
);
// CDC into clk_4x
fifo_shift u_fifo_shift (
// input
.s_aclk (clk), // input wire s_aclk
.s_aresetn (flag_mgc_done), // input wire s_aresetn
.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}), // input wire [31 : 0] s_axis_tdata
.s_aclk (clk), // input wire s_aclk
.s_aresetn (flag_mgc_done), // input wire s_aresetn
.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata ({8'd0, mf_data_interp16_q[31-:12], mf_data_interp16_i[31-:12]}), // input wire [31 : 0] s_axis_tdata
// output
.m_aclk (clk_4x), // input wire m_aclk
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
.m_axis_tready(1'b1), // input wire m_axis_tready
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
.m_aclk (clk_4x), // input wire m_aclk
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
.m_axis_tready(1'b1), // input wire m_axis_tready
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
.wr_rst_busy (),
.rd_rst_busy ()
);
fir_dmf_interp4 u_fir_dmf_interp4_i (
.aclk (clk_4x),
.s_axis_data_tvalid(dmf_s_valid),
.s_axis_data_tready(),
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
.m_axis_data_tvalid(dmf_tvalid_interp4_i),
.m_axis_data_tdata (dmf_tdata_interp4_i)
// fir_dmf_interp4 u_fir_dmf_interp4_i (
// .aclk (clk_4x),
// .s_axis_data_tvalid(dmf_s_valid),
// .s_axis_data_tready(),
// .s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
// .m_axis_data_tvalid(dmf_tvalid_interp4_i),
// .m_axis_data_tdata (dmf_tdata_interp4_i)
// );
// fir_dmf_interp4 u_fir_dmf_interp4_q (
// .aclk (clk_4x),
// .s_axis_data_tvalid(dmf_s_valid),
// .s_axis_data_tready(),
// .s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
// .m_axis_data_tvalid(dmf_tvalid_interp4_q),
// .m_axis_data_tdata (dmf_tdata_interp4_q)
// );
// dmf filter
fir_dmf_interp16 u_fir_dmf_interp16_i (
.aclk (clk_4x), // input wire aclk
.s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(dmf_tvalid_interp16_i), // output wire m_axis_data_tvalid
.m_axis_data_tdata (dmf_tdata_interp16_i) // output wire [31 : 0] m_axis_data_tdata
);
fir_dmf_interp4 u_fir_dmf_interp4_q (
.aclk (clk_4x),
.s_axis_data_tvalid(dmf_s_valid),
.s_axis_data_tready(),
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
.m_axis_data_tvalid(dmf_tvalid_interp4_q),
.m_axis_data_tdata (dmf_tdata_interp4_q)
fir_dmf_interp16 u_fir_dmf_interp16_q (
.aclk (clk_4x), // input wire aclk
.s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(dmf_tvalid_interp16_q), // output wire m_axis_data_tvalid
.m_axis_data_tdata (dmf_tdata_interp16_q) // output wire [31 : 0] m_axis_data_tdata
);
wire [7:0] cnt_chu_seq_sync_max_vio;
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
wire mag_valid;
wire frame_sync_4x;
// wire frame_sync_pulse;
wire frame_sync_pulse; // in baseband process clock domain, quater clock
reg flag_frame_sync; // active high level
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -282,9 +330,9 @@ module RecvTop (
) u_MagnitudeEstimator (
.clk (clk_4x),
.rst (rst),
.vec_valid(dmf_tvalid_interp4_i),
.I (dmf_tdata_interp4_i[20:0]),
.Q (dmf_tdata_interp4_q[20:0]),
.vec_valid(dmf_tvalid_interp16_i),
.I (dmf_tdata_interp16_i[20:0]),
.Q (dmf_tdata_interp16_q[20:0]),
.mag (mag),
.mag_valid(mag_valid)
);
@@ -301,8 +349,11 @@ module RecvTop (
.frame_sync_pulse() // under clk_4x
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
// ! ATTENTION
// frame_sync_pulse is under clk_quarter
always @(posedge clk_quarter) begin
if (frame_sync_pulse && ~flag_frame_sync) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
@@ -314,7 +365,9 @@ module RecvTop (
end
end
always @(posedge clk) begin
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
always @(posedge clk_quarter) begin
if (rst) begin
flag_frame_sync <= 0;
end
@@ -327,45 +380,71 @@ module RecvTop (
end
wire [ 9:0] FrameSync_douti;
wire [ 9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
wire [9:0] FrameSync_douti;
wire [9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
wire [9:0] dagc_data_in_i;
wire [9:0] dagc_data_in_q;
// * lost the connection with other nodes
reg [20:0] cnt_lost;
reg framelost;
reg [1:0] cnt_downsample = 0;
wire pulse_downsample_enable;
assign pulse_downsample_enable = (cnt_downsample == 3);
always @(posedge clk) begin
if (rst_frame_sync) begin
cnt_lost <= 21'd0;
framelost <= 1'b0;
end
else begin
if (cnt_lost >= 21'd750000) begin
cnt_lost <= 21'd0;
framelost <= 1'b1;
end
else begin
cnt_lost <= 21'd1 + cnt_lost;
framelost <= 1'b0;
end
end
cnt_downsample <= cnt_downsample + 1;
end
fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_i (
.rst (rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(clk_quarter), // input wire rd_clk
.din (mf_data_interp16_i[31-:10]), // input wire [9 : 0] din
.wr_en (pulse_downsample_enable), // input wire wr_en
.rd_en (1), // input wire rd_en
.dout (mf_data_downsample_i), // output wire [9 : 0] dout
.full (), // output wire full
.empty () // output wire empty
);
fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_q (
.rst (rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(clk_quarter), // input wire rd_clk
.din (mf_data_interp16_q[31-:10]), // input wire [9 : 0] din
.wr_en (pulse_downsample_enable), // input wire wr_en
.rd_en (1), // input wire rd_en
.dout (mf_data_downsample_q), // output wire [9 : 0] dout
.full (), // output wire full
.empty () // output wire empty
);
//* CLOCK_QUARTER DOMAIN
shift_register_64 u_shift_register_64_i (
.D (mf_data_downsample_i), // input wire [9 : 0] D
.CLK(clk_quarter), // input wire CLK
.Q (dagc_data_in_i) // output wire [9 : 0] Q
);
shift_register_64 u_shift_register_64_q (
.D (mf_data_downsample_q), // input wire [9 : 0] D
.CLK(clk_quarter), // input wire CLK
.Q (dagc_data_in_q) // output wire [9 : 0] Q
);
DAGC_v2 DAGC_v2 (
.clk (clk),
.clk (clk_quarter),
.rst (~flag_mgc_done),
.mgc1_rdy (MF_rdy),
.framesync_d0 (flag_frame_sync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(mf_data_interp4_i[29-:10]), // input,
.matchfilterout_q(mf_data_interp4_q[29-:10]), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
.matchfilterout_i(dagc_data_in_i), // input,
.matchfilterout_q(dagc_data_in_q), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
// debug
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
@@ -380,8 +459,8 @@ module RecvTop (
// CFO estimation
freqestm freqestm (
.clk (clk),
.rst (mgc_start),
.clk (clk_quarter),
.rst (mgc_start_quarter),
.mgc_rdy (mgc_rdy),
.framesync (dagc_rdy),
.datain_i (DAGC_out_i),
@@ -396,7 +475,7 @@ module RecvTop (
//位同步
wire [1:0] cnt_tsync;
TimeSync_top TimeSync_top (
.clk (clk),
.clk (clk_quarter),
.rst (rst_frame_sync),
.dini (freqdataout_i),
.dinq (freqdataout_q),
@@ -417,7 +496,7 @@ module RecvTop (
// SC-FDE
SC_FDE_TOP SC_FDE_TOP_djy (
.clk (clk),
.clk (clk_quarter),
.rst (rst_frame_sync),
// param
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
@@ -451,7 +530,7 @@ module RecvTop (
wire [9:0] phase_adjust_douti;
wire [9:0] phase_adjust_doutq;
phase_adjust phase_adjust (
.clk (clk),
.clk (clk_quarter),
.rst (rst_frame_sync),
.din_i (SC_FDE_douti),
.din_q (SC_FDE_doutq),
@@ -467,8 +546,8 @@ module RecvTop (
wire [7:0] IQmergedout;
IQmerge IQmerge (
.clk (clk),
.clk2 (clk_2x),
.clk (clk_quarter),
.clk2 (clk_half),
.rst (rst2 || rst_frame_sync),
.nd (phase_adjust_rdy),
.framesync (framesync_tsync),
@@ -487,7 +566,7 @@ module RecvTop (
wire [8:0] total_frames;
CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
.clk (clk_2x),
.clk (clk_half),
.Rst (rst2 || rst_frame_sync),
.FrameSync (ldpcsyncin),
.Nd (IQmergerdy),
@@ -501,8 +580,8 @@ module RecvTop (
);
extract_mac_frame u_extract_mac_frame (
.clk (clk_2x),
.rst (rst2 || rst_frame_sync || ~flag_frame_sync),
.clk (clk_half),
.rst (rst2 || rst_frame_sync),
.ldpc_dec_out_start (LDPC_SyncOut),
.ldpc_dec_out_valid (LDPC_Rdy),
.ldpc_dec_out_data (LDPC_Dout),
@@ -512,6 +591,22 @@ module RecvTop (
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
);
reg err_flag;
reg err_flag_d1;
// reg err_flag_pos;
always @(posedge clk) begin
if (rst2 || rst_frame_sync) begin
err_flag <= 0;
end
else if (total_frames == 105 && bad_frames > 0) begin
err_flag <= 1;
end
err_flag_d1 <= err_flag;
err_flag_pos <= err_flag & ~err_flag_d1;
end
@@ -530,60 +625,62 @@ module RecvTop (
);
xpm_cdc_pulse #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) xpm_cdc_frame_sync_pulse_inst (
.dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
// transfer is correctly initiated on src_pulse input. This output is
// combinatorial unless REG_OUTPUT is set to 1.
.dest_clk (clk), // 1-bit input: Destination clock.
.dest_rst (), // 1-bit input: optional; required when RST_USED = 1
.src_clk (clk_4x), // 1-bit input: Source clock.
.src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
// destination clock domain. The minimum gap between each pulse transfer must be
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
// between the falling edge of a src_pulse to the rising edge of the next
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
// will generate a pulse the size of one dest_clk period in the destination
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
// src_rst and/or dest_rst are asserted.
.src_rst () // 1-bit input: optional; required when RST_USED = 1
.DEST_SYNC_FF (4),
.INIT_SYNC_FF (1),
.REG_OUTPUT (1),
.RST_USED (0),
.SIM_ASSERT_CHK(1)
) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_1x (
.dest_pulse(frame_sync_pulse_1x),
.dest_clk (clk),
.dest_rst (),
.src_clk (clk_4x),
.src_pulse (frame_sync_4x),
.src_rst ()
);
xpm_cdc_pulse #(
.DEST_SYNC_FF (4),
.INIT_SYNC_FF (1),
.REG_OUTPUT (1),
.RST_USED (0),
.SIM_ASSERT_CHK(1)
) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_quarter (
.dest_pulse(frame_sync_pulse),
.dest_clk (clk_quarter),
.dest_rst (),
.src_clk (clk_4x),
.src_pulse (frame_sync_4x),
.src_rst ()
);
// ***** debug *****
vio_recv_top u_vio_recv_top (
.clk (clk),
.clk (clk_quarter),
.probe_out0(cnt_chu_seq_sync_max_vio)
);
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
.clk (clk_quarter),
.probe0 (dagc_data_in_i), // width: 12
.probe1 (dagc_data_in_q), // width: 12
.probe2 (flag_mgc_done), // width: 1
.probe3 (flag_frame_sync), // width: 1
.probe4 (flag_cfo_done), // width: 1
.probe5 (freqdataout_i), // width: 10
.probe6 (freqdataout_q), // width: 10
.probe7 (IntpARdy), // width: 1
.probe8 (IntpOuti), // width: 10
.probe9 (IntpOutq), // width: 10
.probe10(nd_SC_FDE_dout), // width: 1
.probe11(SC_FDE_douti), // width: 10
.probe12(SC_FDE_doutq), // width: 10
.probe13(phase_adjust_rdy), // width: 1
.probe14(phase_adjust_douti), // width: 10
.probe15(phase_adjust_doutq), // width: 10
.probe16(good_frames), // width: 9
.probe17(bad_frames) // width: 9
);
hdl/Transmitter.v
+32 -32
View File
@@ -521,41 +521,41 @@ module Transmitter #(
.m_axis_data_tdata (bb_wave_out_q_interp16)
);
fir_shape_interp8 u_fir_shape_interp8_i (
.aclk (clk),
.s_axis_data_tvalid(fir_tvalid_in),
.s_axis_data_tready(),
.s_axis_data_tdata (m_fir_tdata_i),
.m_axis_data_tvalid(),
.m_axis_data_tdata (bb_wave_out_i_interp8)
);
// fir_shape_interp8 u_fir_shape_interp8_i (
// .aclk (clk),
// .s_axis_data_tvalid(fir_tvalid_in),
// .s_axis_data_tready(),
// .s_axis_data_tdata (m_fir_tdata_i),
// .m_axis_data_tvalid(),
// .m_axis_data_tdata (bb_wave_out_i_interp8)
// );
fir_shape_interp8 u_fir_shape_interp8_q (
.aclk (clk),
.s_axis_data_tvalid(fir_tvalid_in),
.s_axis_data_tready(),
.s_axis_data_tdata (m_fir_tdata_q),
.m_axis_data_tvalid(),
.m_axis_data_tdata (bb_wave_out_q_interp8)
);
// fir_shape_interp8 u_fir_shape_interp8_q (
// .aclk (clk),
// .s_axis_data_tvalid(fir_tvalid_in),
// .s_axis_data_tready(),
// .s_axis_data_tdata (m_fir_tdata_q),
// .m_axis_data_tvalid(),
// .m_axis_data_tdata (bb_wave_out_q_interp8)
// );
fir_shape_interp4 u_fir_shape_interp4_i (
.aclk (clk),
.s_axis_data_tvalid(fir_tvalid_in),
.s_axis_data_tready(),
.s_axis_data_tdata (m_fir_tdata_i),
.m_axis_data_tvalid(),
.m_axis_data_tdata (bb_wave_out_i_interp4)
);
// fir_shape_interp4 u_fir_shape_interp4_i (
// .aclk (clk),
// .s_axis_data_tvalid(fir_tvalid_in),
// .s_axis_data_tready(),
// .s_axis_data_tdata (m_fir_tdata_i),
// .m_axis_data_tvalid(),
// .m_axis_data_tdata (bb_wave_out_i_interp4)
// );
fir_shape_interp4 u_fir_shape_interp4_q (
.aclk (clk),
.s_axis_data_tvalid(fir_tvalid_in),
.s_axis_data_tready(),
.s_axis_data_tdata (m_fir_tdata_q),
.m_axis_data_tvalid(),
.m_axis_data_tdata (bb_wave_out_q_interp4)
);
// fir_shape_interp4 u_fir_shape_interp4_q (
// .aclk (clk),
// .s_axis_data_tvalid(fir_tvalid_in),
// .s_axis_data_tready(),
// .s_axis_data_tdata (m_fir_tdata_q),
// .m_axis_data_tvalid(),
// .m_axis_data_tdata (bb_wave_out_q_interp4)
// );
hdl/ad9361_mgc_pin_ctrl.v
+12 -12
View File
@@ -162,18 +162,18 @@ module ad9361_mgc_pin_ctrl (
// .probe_out0(start) // output wire [0 : 0] probe_out0
// );
// ila_ad9361_mgc u_ila_ad9361_mgc (
// .clk (clk), // input wire clk
// .probe0(start_posedge), // input wire [0:0] probe0
// .probe1(rx_data_i), // input wire [11:0] probe1
// .probe2(u_power_measure.cs), // input wire [2:0] probe2
// .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
// .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
// .probe5(flag_too_high), // input wire [0:0] probe5
// .probe6(flag_too_low), // input wire [0:0] probe6
// .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
// .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
// );
ila_ad9361_mgc u_ila_ad9361_mgc (
.clk (clk), // input wire clk
.probe0(start_posedge), // input wire [0:0] probe0
.probe1(rx_data_i), // input wire [11:0] probe1
.probe2(u_power_measure.cs), // input wire [2:0] probe2
.probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
.probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
.probe5(flag_too_high), // input wire [0:0] probe5
.probe6(flag_too_low), // input wire [0:0] probe6
.probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
.probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
);
endmodule
hdl/descrambler.v
-161
View File
@@ -1,161 +0,0 @@
// * Engineer:
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
// * *************************************************** *
// * Update Date:
// * NOTE :
module scrambler #(
parameter ILA_ON = 0
) (
input clk,
input rst_n,
// s_axis_stream
input [31:0] s_axis_tdata,
input s_axis_tvalid,
output reg s_axis_tready,
input s_axis_tlast,
input [31:0] s_axis_rd_data_count,
// m_axis_stream
output reg [31:0] m_axis_tdata,
output reg m_axis_tvalid,
input m_axis_tready,
output reg m_axis_tlast
);
// ******** Wire & Reg ********
wire rst;
reg [ 2:0] addr_scramble = 0;
reg [ 2:0] addr_scramble_d1 = 0;
reg [ 2:0] addr_scramble_d2 = 0;
wire [31:0] data_scramble_mask;
reg [ 3:0] cnt_in;
reg [31:0] s_axis_tdata_d1;
reg [31:0] s_axis_tdata_d2;
reg s_axis_tready_d1;
reg s_axis_tlast_d1;
// fsm
reg [ 1:0] cs = 0;
reg [ 1:0] ns = 0;
localparam S_IDLE = 0;
localparam S_WORKING = 1;
// ******** Assingment ********
assign rst = ~rst_n;
// ******** Logic Block ********
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 16) begin
ns = S_WORKING;
end
end
S_WORKING: begin
if (addr_scramble_d2 == 3'h7) begin
ns = S_IDLE;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
addr_scramble <= 0;
end
else begin
addr_scramble <= addr_scramble + 1;
end
addr_scramble_d1 <= addr_scramble;
addr_scramble_d2 <= addr_scramble_d1;
end
always @(posedge clk) begin
if (cs == S_WORKING) begin
m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
end
else begin
m_axis_tdata <= 0;
end
end
always @(posedge clk) begin
if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
s_axis_tready <= 1;
end
else begin
s_axis_tready <= 0;
end
end
always @(posedge clk) begin
s_axis_tdata_d1 <= s_axis_tdata;
s_axis_tready_d1 <= s_axis_tready;
m_axis_tvalid <= s_axis_tready_d1;
s_axis_tlast_d1 <= s_axis_tlast;
m_axis_tlast <= s_axis_tlast_d1;
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
cnt_in <= 0;
end
else if (cs == S_WORKING && cnt_in < 4'd8) begin
cnt_in <= cnt_in + 1;
end
end
// ******** Inst ********
bram_scramble u_bram_scramble (
.clka (clk), // input wire clka
.addra(addr_scramble), // input wire [2 : 0] addra
.douta(data_scramble_mask) // output wire [31 : 0] douta
);
// ******** Debug ********
generate
if (ILA_ON)
ila_scrambler u_ila_scrambler (
.clk (clk), // input wire clk
.probe0(s_axis_tvalid), // input wire [0:0] probe0
.probe1(s_axis_tready), // input wire [0:0] probe1
.probe2(s_axis_tdata), // input wire [31:0] probe2
.probe3(s_axis_tlast), // input wire [0:0] probe3
.probe4(m_axis_tvalid), // input wire [0:0] probe4
.probe5(m_axis_tready), // input wire [0:0] probe5
.probe6(m_axis_tdata), // input wire [31:0] probe6
.probe7(m_axis_tlast), // input wire [0:0] probe7
.probe8(data_scramble_mask) // input wire [31:0] probe8
);
endgenerate
endmodule
hdl/net_city.v
+9 -9
View File
@@ -12,8 +12,8 @@ module net_city (
output reg [07:0] recv_id = 8'd0,
// rx signal
input frame_sync,
input recv_net_data_nd,
input [63:0] recv_net_data,
// input recv_net_data_nd,
// input [63:0] recv_net_data,
// net parameter
input [31:0] frame_sync_time,
input [07:0] id_num,
@@ -215,13 +215,13 @@ module net_city (
// if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
recv_id <= recv_net_data[63:56];
recv_video_id01 <= recv_net_data[55:48];
recv_video_id02 <= recv_net_data[47:40];
recv_video_id03 <= recv_net_data[39:32];
recv_connect_node <= recv_net_data[31:24];
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// recv_id <= recv_net_data[63:56];
// recv_video_id01 <= recv_net_data[55:48];
// recv_video_id02 <= recv_net_data[47:40];
// recv_video_id03 <= recv_net_data[39:32];
// recv_connect_node <= recv_net_data[31:24];
// end
// else begin
// state_net <= 8'd200;
hdl/power_measure.v
+1 -1
View File
@@ -30,7 +30,7 @@ module power_measure (
);
localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数
localparam CNT_MEASURING_MAX = 256; // * 观察64个周期
localparam CNT_MEASURING_MAX = 4096; // * 观察4096个周期
localparam CNT_ADJUST_TIMES_MAX = 25;
localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
// ******** Wire & Reg ********
hdl/system_top.v
+44 -34
View File
@@ -70,6 +70,8 @@ module system_top (
wire clk_1x;
wire clk_2x;
wire clk_4x;
wire clk_quarter;
wire clk_half;
// emio
wire [31:0] gpio_i;
@@ -134,6 +136,8 @@ module system_top (
wire tx_start_vio;
reg tx_start_vio_d1;
wire tx_start_vio_pos;
// rx
wire rx_err_flag_pos;
// vio
wire rst_manual;
@@ -174,13 +178,15 @@ module system_top (
// clock domain - ad9361 rx & tx
clk_wiz_baseband u_clk_wiz_baseband (
// Clock out ports
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
.clk_quarter(clk_quarter),
.clk_half (clk_half),
// Status and control signals
.locked (locked), // output locked
.locked (locked), // output locked
// Clock in ports
.clk_src(ad9361_rx_clk) // input clk_src
.clk_src (ad9361_rx_clk) // input clk_src
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
@@ -218,15 +224,16 @@ module system_top (
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl_tx_intr (intr_2ps | intr_2ps_vio_pos),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_2x),
.clk_rx_data_src_fifo (clk_half),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
@@ -245,17 +252,17 @@ module system_top (
.uart_tx (uart_tx)
);
// tdma u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (tdma_flag_is_master),
// .flag_frame_sync(frame_sync_pulse),
// .tdma_slot_len (tdma_slot_len[23:0]),
// .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (tdma_flag_is_master),
.flag_frame_sync(frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
@@ -303,9 +310,9 @@ module system_top (
Transmitter u_Transmitter (
.clk (clk_1x),
.rst (rst_sys | phy_rst),
.speed_mode (2),
.speed_mode (0),
.send_data_ready (send_data_ready),
.send_start (tx_start | tx_start_vio_pos),
.send_start (tx_start),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
@@ -322,13 +329,15 @@ module system_top (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst | rx_rst_vio),
.clk_half (clk_half),
.clk_quarter (clk_quarter),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse (flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.frame_sync_pulse_1x (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
@@ -340,7 +349,8 @@ module system_top (
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.err_flag_pos (rx_err_flag_pos)
);
@@ -388,22 +398,22 @@ module system_top (
// );
assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
always @(posedge clk_1x) begin
tx_start_vio_d1 <= tx_start_vio;
end
// assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// always @(posedge clk_1x) begin
// tx_start_vio_d1 <= tx_start_vio;
// end
assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
always @(posedge clk_1x) begin
intr_2ps_vio_d1 <= intr_2ps_vio;
end
// assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// always @(posedge clk_1x) begin
// intr_2ps_vio_d1 <= intr_2ps_vio;
// end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(rx_rst_vio),
.probe_out1(tx_start_vio),
.probe_out2(intr_2ps_vio)
.probe_out0(node_id),
.probe_out1(max_slot_num),
.probe_out2(rst_manual)
);
endmodule
hdl/tdma.v
+2 -1
View File
@@ -14,7 +14,8 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter TIC_FRAME_SYNC = 42344
// parameter TIC_FRAME_SYNC = 44392
parameter TIC_FRAME_SYNC = 177568
) (
input clk,
input rst,