ZoroGH 9d566f6b74 feat(top): add abnormal logic to pass 3rd test

2024-10-18 14:05:04 +08:00

bd

Init repo

2024-07-19 14:09:20 +08:00

coe

merge(sys): merge tdma update

2024-10-12 11:02:35 +08:00

contraint

feat(tdma): update tdma logic

2024-10-09 20:13:52 +08:00

hdl

feat(top): add abnormal logic to pass 3rd test

2024-10-18 14:05:04 +08:00

sim

feat(tdma): update tdma logic

2024-10-09 20:13:52 +08:00

.gitignore

refactor(recviver): simulation pass for ila data

2024-07-24 21:32:28 +08:00

.tags

feat(tdma): update tdma logic

2024-10-09 20:13:52 +08:00

create_sys.tcl

Init repo

2024-07-19 14:09:20 +08:00

util.tcl

fix(top): reverse iq in recv

2024-08-02 20:51:37 +08:00

S

Description

MM7020 project

1.1 MiB

Releases 3

第3方测试版本

Latest

2024-10-18 19:57:09 +08:00

Languages

Verilog 93.2%

Tcl 6.8%