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Author	SHA1	Message	Date
ZoroGH	9d566f6b74	feat(top): add abnormal logic to pass 3rd test ThirdTestRelease	2024-10-18 14:05:04 +08:00
ZoroGH	fea952e06a	merge(sys): merge tdma update	2024-10-12 11:02:35 +08:00
ZoroGH	ae78b3092d	feat(tdma): update tdma logic	2024-10-09 20:13:52 +08:00
ZoroGH	5e8d69a0b0	feat(top): new (de)scrambler, crc16	2024-08-13 22:07:58 +08:00
ZoroGH	a4eb609aae	refactor(top): set ps config param, adjust timing	2024-08-03 21:02:08 +08:00
ZoroGH	145e8c0930	fix(top): reverse iq in recv PhyTested	2024-08-02 20:51:37 +08:00
ZoroGH	92583b785c	feat(top): add mac layer control, half tested	2024-07-29 19:04:48 +08:00
ZoroGH	de8ca3db68	fix(tx): remap {Q,I} to {I,Q}, pass simu. PhyDone	2024-07-27 14:05:14 +08:00
ZoroGH	7751749856	fix(system): adjust cp len, frame sync pos, IQ map	2024-07-25 23:32:28 +08:00
ZoroGH	0bedb6c2ef	refactor(recviver): simulation pass for ila data	2024-07-24 21:32:28 +08:00
ZoroGH	09fe5b3f8d	refactor(recveiver): replace old agc & frame-sync	2024-07-22 21:27:17 +08:00
ZoroGH	51eee95b60	merge	2024-07-22 20:48:35 +08:00
ZoroGH	48c59b64ff	temp review	2024-07-22 20:45:33 +08:00
ZoroGH	da1073f750	stash pop	2024-07-22 15:09:15 +08:00
ZoroGH	d210233e74	reivew	2024-07-22 15:01:48 +08:00
ZoroGH	e33875ef8f	Add the recv hdl file	2024-07-19 21:31:49 +08:00
ZoroGH	9a1f168184	Init repo TxDone	2024-07-19 14:09:20 +08:00