refactor(recveiver): replace old agc & frame-sync

hdl/RecvTop.v

@@ -22,6 +22,7 @@ module RecvTop (
     input clk,
     input clk2,
     input clk_60M_mac,
+    input clk_4x,
     input rst,
     input rst2,
 
@@ -128,7 +129,7 @@ module RecvTop (
         end
     end
 
-    assign mgc_start = (cnt_mgc_delay == 8'hff);
+    assign mgc_start = (cnt_mgc_delay == 8'hFE);
 
     ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
         .clk           (clk),
@@ -140,8 +141,16 @@ module RecvTop (
         .flag_mgc_done (flag_mgc_done)
     );
 
-    wire        MF_rdy;  // flag_mgc_done_d1
-    wire        MF_rst;  // flag_mgc_done_pulse_d2
+    reg  MF_rdy;  // flag_mgc_done_d1
+    wire MF_rst;  // flag_mgc_done_pulse_d2
+    always @(posedge clk) begin
+        if (rst) begin
+            MF_rdy <= 0;
+        end
+        else begin
+            MF_rdy <= flag_mgc_done;
+        end
+    end
 
     wire        fifo_out_valid;
     reg  [ 2:0] cnt_fifo_out_valid;
@@ -247,6 +256,8 @@ module RecvTop (
     wire        mag_valid;
     wire        frame_sync_4x;
     wire        frame_sync_pulse;  // in domain clk
+    reg         flag_frame_sync;  // active high level
+    // calc the magnitude
     MagnitudeEstimator #(
         .VEC_WIDTH(21)
     ) u_MagnitudeEstimator (
@@ -271,6 +282,17 @@ module RecvTop (
         .frame_sync_pulse()
     );
 
+    always @(posedge clk) begin
+        if (rst) begin
+            flag_frame_sync <= 0;
+        end
+        else if (frame_sync_pulse) begin
+            flag_frame_sync <= 1;
+        end
+        else begin
+            flag_frame_sync <= flag_frame_sync;
+        end
+    end
     // wire [9:0] DAGC_out_i;
     // wire [9:0] DAGC_out_q;
 
@@ -285,26 +307,9 @@ module RecvTop (
     assign FrameSync_dini = DAGC_out_i;
     assign FrameSync_dinq = DAGC_out_q;
     // wire framesync;
-    wire Sync_rdy;
-    wire Pilot_rdy;
 
 
-
-    SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst (
-        .clk               (clk),
-        .rst               (MF_rst),
-        .rst_ready         (~MF_rdy),
-        .datain_i          (matchfilterout_i),
-        .datain_q          (matchfilterout_q),
-        .Sync_i            (FrameSync_douti),
-        .Sync_q            (FrameSync_doutq),
-        .Sync_rdy          (Sync_rdy),           // 帧同步找到了过门限峰值
-        .Pilot_rdy         (Pilot_rdy),          // 开始取导频的标志位 not used
-        .flag_sync         (framesync),          // high level flag not used
-        .Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1)  // not used
-    );
-
-    //
+    // * lost the connection with other nodes
     reg [20:0] cnt_lost;
     reg        framelost;
     always @(posedge clk) begin
@@ -327,9 +332,9 @@ module RecvTop (
 
     DAGC_v2 DAGC_v2 (
         .clk             (clk),
-        .rst             (~mgc1_rdy),
+        .rst             (~flag_mgc_done),
         .mgc1_rdy        (MF_rdy),
-        .framesync_d0    (framesync),
+        .framesync_d0    (flag_frame_sync),
         .vio_powertest_h (2'b00),
         .vio_powertest_l (2'b00),
         .matchfilterout_i(mf_data_interp4_i[29-:10]),  // input, 
@@ -357,7 +362,7 @@ module RecvTop (
 
     freqestm freqestm (
         .clk            (clk),
-        .rst            (MF_rst),
+        .rst            (mgc_start),
         .mgc_rdy        (mgc_rdy),
         .framesync      (dagc_rdy),
         .datain_i       (DAGC_out_i),
@@ -565,7 +570,7 @@ module RecvTop (
     );
 
 
-    // **** cdc ****
+    // ***** cdc *****
     xpm_cdc_single #(
         .DEST_SYNC_FF  (2),  // DECIMAL; range: 2-10
         .INIT_SYNC_FF  (1),  // DECIMAL; 0=disable simulation init values, 1=enable simulation init values

hdl/ad9361_mgc_pin_ctrl.v

@@ -21,7 +21,7 @@ module ad9361_mgc_pin_ctrl (
     input       [11:0] rx_data_q,
     // this port is from zynq to ad9361
     output wire [ 3:0] ad9361_ctrl_in,
-    output reg         flag_mgc_done
+    output reg         flag_mgc_done // active high level signal
 
 );