ZoroGH 09fe5b3f8d refactor(recveiver): replace old agc & frame-sync

2024-07-22 21:27:17 +08:00

bd

Init repo

2024-07-19 14:09:20 +08:00

coe

stash pop

2024-07-22 15:09:15 +08:00

contraint

Init repo

2024-07-19 14:09:20 +08:00

hdl

refactor(recveiver): replace old agc & frame-sync

2024-07-22 21:27:17 +08:00

sim

Init repo

2024-07-19 14:09:20 +08:00

.gitignore

stash pop

2024-07-22 15:09:15 +08:00

.tags

reivew

2024-07-22 15:01:48 +08:00

create_sys.tcl

Init repo

2024-07-19 14:09:20 +08:00

S

Description

MM7020 project

1.1 MiB

Releases 3

第3方测试版本

Latest

2024-10-18 19:57:09 +08:00

Languages

Verilog 93.2%

Tcl 6.8%