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speed_3125

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• 3bdfbd31dc feat(top): adjust rf control logic, ila for 3rd test speed_3125 ZoroGH 2024-10-18 19:14:09 +08:00
• 9d566f6b74 feat(top): add abnormal logic to pass 3rd test main ThirdTestRelease ZoroGH 2024-10-18 14:05:04 +08:00
• 6ddf033548 perf(sys): delete some ila, optimize timing release_3125_v1.1 ZoroGH 2024-10-13 19:34:35 +08:00
• fea952e06a merge(sys): merge tdma update ZoroGH 2024-10-12 11:02:35 +08:00
• 26c24ae5b2 bugfix(tdma): fix 3.125 frame sync tic pos(param) release_3125_v1 ZoroGH 2024-10-11 12:11:08 +08:00
• ae78b3092d feat(tdma): update tdma logic ZoroGH 2024-10-09 20:13:52 +08:00
• 4b4f9dc671 feat(sys): update tdma param updated from ps ZoroGH 2024-10-09 09:45:04 +08:00
• 3990e3081a feat(sys): change speed to 3.125, test pass. ZoroGH 2024-09-05 20:42:30 +08:00
• 5e8d69a0b0 feat(top): new (de)scrambler, crc16 ZoroGH 2024-08-13 22:07:58 +08:00
• a4eb609aae refactor(top): set ps config param, adjust timing ZoroGH 2024-08-03 21:02:08 +08:00
• 145e8c0930 fix(top): reverse iq in recv PhyTested ZoroGH 2024-08-02 20:51:37 +08:00
• 92583b785c feat(top): add mac layer control, half tested ZoroGH 2024-07-29 19:04:48 +08:00
• de8ca3db68 fix(tx): remap {Q,I} to {I,Q}, pass simu. PhyDone ZoroGH 2024-07-27 14:05:14 +08:00
• 7751749856 fix(system): adjust cp len, frame sync pos, IQ map ZoroGH 2024-07-25 23:32:28 +08:00
• 0bedb6c2ef refactor(recviver): simulation pass for ila data ZoroGH 2024-07-24 21:32:28 +08:00
• 09fe5b3f8d refactor(recveiver): replace old agc & frame-sync ZoroGH 2024-07-22 21:27:17 +08:00
• 51eee95b60 merge ZoroGH 2024-07-22 20:48:35 +08:00
• 48c59b64ff temp review ZoroGH 2024-07-22 20:45:33 +08:00
• da1073f750 stash pop ZoroGH 2024-07-22 15:09:15 +08:00
• d210233e74 reivew ZoroGH 2024-07-22 15:01:48 +08:00
• e33875ef8f Add the recv hdl file ZoroGH 2024-07-19 21:31:49 +08:00
• 9a1f168184 Init repo TxDone ZoroGH 2024-07-19 14:09:20 +08:00