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ZoroGH
/
MM7020
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speed_3125
T
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ZoroGH
3bdfbd31dc
feat(top): adjust rf control logic, ila for 3rd test
2024-10-18 19:14:09 +08:00
bd
Init repo
2024-07-19 14:09:20 +08:00
coe
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00
contraint
feat(top): adjust rf control logic, ila for 3rd test
2024-10-18 19:14:09 +08:00
hdl
feat(top): adjust rf control logic, ila for 3rd test
2024-10-18 19:14:09 +08:00
sim
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00
.gitignore
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
.tags
feat(sys): change speed to 3.125, test pass.
2024-09-05 20:42:30 +08:00
create_sys.tcl
Init repo
2024-07-19 14:09:20 +08:00
util.tcl
feat(sys): change speed to 3.125, test pass.
2024-09-05 20:42:30 +08:00
S
Description
MM7020 project
1.1
MiB
Releases
3
第3方测试版本
Latest
2024-10-18 19:57:09 +08:00
Languages
Verilog
93.2%
Tcl
6.8%
