ZoroGH de8ca3db68 fix(tx): remap {Q,I} to {I,Q}, pass simu.

2024-07-27 14:05:14 +08:00

bd

Init repo

2024-07-19 14:09:20 +08:00

coe

fix(system): adjust cp len, frame sync pos, IQ map

2024-07-25 23:32:28 +08:00

contraint

Init repo

2024-07-19 14:09:20 +08:00

hdl

fix(tx): remap {Q,I} to {I,Q}, pass simu.

2024-07-27 14:05:14 +08:00

sim

fix(system): adjust cp len, frame sync pos, IQ map

2024-07-25 23:32:28 +08:00

.gitignore

refactor(recviver): simulation pass for ila data

2024-07-24 21:32:28 +08:00

.tags

reivew

2024-07-22 15:01:48 +08:00

create_sys.tcl

Init repo

2024-07-19 14:09:20 +08:00

S

Description

MM7020 project

1.1 MiB

Releases 3

第3方测试版本

Latest

2024-10-18 19:57:09 +08:00

Languages

Verilog 93.2%

Tcl 6.8%