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feat(sys): change speed to 3.125, test pass.

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ZoroGH
2024-09-05 20:42:30 +08:00
parent 5e8d69a0b0
commit 3990e3081a
12 changed files with 624 additions and 515 deletions
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hdl/RecvTop.v
+225 -128
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@@ -22,6 +22,8 @@ module RecvTop (
input clk,
input clk_2x, // clk_2x
input clk_4x,
input clk_half, // clk_1/2
input clk_quarter, // clk_1/4
input rst,
input rst2, // TODO： delete the signal
// phy wave
@@ -30,7 +32,7 @@ module RecvTop (
// mgc control
output [ 3:0] ad9361_ctrl_in,
output wire flag_mgc_done_pulse, // active high pulse signal
output wire frame_sync_pulse, // in domain clk
output wire frame_sync_pulse_1x, // in domain clk
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
@@ -46,7 +48,9 @@ module RecvTop (
output wire [31:0] rx_data_src_fifo_tdata,
output wire rx_data_src_fifo_tlast,
input wire rx_data_src_fifo_tready,
output wire rx_data_src_fifo_tvalid
output wire rx_data_src_fifo_tvalid,
// ber
output reg err_flag_pos
);
wire rst_TimeSync;
@@ -119,7 +123,8 @@ module RecvTop (
reg [ 7:0] cnt_mgc_delay;
wire mgc_start;
wire flag_mgc_done; // level flag
wire mgc_start_quarter;
wire flag_mgc_done; // level flag, under clk_1x
wire flag_mgc_done_4x; // level flag
// startup delay
@@ -136,6 +141,7 @@ module RecvTop (
end
assign mgc_start = (cnt_mgc_delay == 8'hFE);
assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE);
// * MGC module
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
@@ -153,7 +159,7 @@ module RecvTop (
reg MF_rdy; // flag_mgc_done_d1
wire MF_rst; // flag_mgc_done_pulse_d2
always @(posedge clk) begin
always @(posedge clk_quarter) begin
if (rst) begin
MF_rdy <= 0;
end
@@ -164,16 +170,21 @@ module RecvTop (
wire fifo_out_valid;
reg [ 2:0] cnt_fifo_out_valid;
reg [ 2:0] cnt_fifo_out_valid_sel = 1; // 根据speed mode对应的计数器边界值
reg [ 2:0] cnt_fifo_out_valid_sel = 7; // 根据speed mode对应的计数器边界值 // refer to Receiver.v
wire [31:0] fifo_out;
reg dmf_s_valid;
wire dmf_tvalid_interp4_i;
wire dmf_tvalid_interp4_q;
wire [31:0] mf_data_interp4_i;
wire [31:0] mf_data_interp4_q;
wire [23:0] dmf_tdata_interp4_i;
wire [23:0] dmf_tdata_interp4_q;
wire dmf_tvalid_interp16_i;
wire dmf_tvalid_interp16_q;
wire [31:0] mf_data_interp16_i;
wire [31:0] mf_data_interp16_q;
wire [23:0] dmf_tdata_interp16_i;
wire [23:0] dmf_tdata_interp16_q;
// in domain clk_quarter
wire [ 9:0] mf_data_downsample_i;
wire [ 9:0] mf_data_downsample_q;
// valid signal for dmf
always @(posedge clk_4x) begin
@@ -211,70 +222,107 @@ module RecvTop (
wire mf_fir_s_tready_q;
// Match filter
fir_match_interp4 u_fir_match_filter_interp4_i (
// fir_match_interp4 u_fir_match_filter_interp4_i (
// .aclk (clk), // input wire aclk
// .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
// .s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
// .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
// .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
// );
// fir_match_interp4 u_fir_match_filter_interp4_q (
// .aclk (clk), // input wire aclk
// .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
// .s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
// .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
// .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
// );
fir_match_interp16 u_fir_match_filter_interp16_i (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
.m_axis_data_tdata (mf_data_interp16_i) // output wire [31 : 0] m_axis_data_tdata
);
fir_match_interp4 u_fir_match_filter_interp4_q (
fir_match_interp16 u_fir_match_filter_interp16_q (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
.m_axis_data_tdata (mf_data_interp16_q) // output wire [31 : 0] m_axis_data_tdata
);
// CDC into clk_4x
fifo_shift u_fifo_shift (
// input
.s_aclk (clk), // input wire s_aclk
.s_aresetn (flag_mgc_done), // input wire s_aresetn
.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}), // input wire [31 : 0] s_axis_tdata
.s_aclk (clk), // input wire s_aclk
.s_aresetn (flag_mgc_done), // input wire s_aresetn
.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata ({8'd0, mf_data_interp16_q[31-:12], mf_data_interp16_i[31-:12]}), // input wire [31 : 0] s_axis_tdata
// output
.m_aclk (clk_4x), // input wire m_aclk
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
.m_axis_tready(1'b1), // input wire m_axis_tready
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
.m_aclk (clk_4x), // input wire m_aclk
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
.m_axis_tready(1'b1), // input wire m_axis_tready
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
.wr_rst_busy (),
.rd_rst_busy ()
);
fir_dmf_interp4 u_fir_dmf_interp4_i (
.aclk (clk_4x),
.s_axis_data_tvalid(dmf_s_valid),
.s_axis_data_tready(),
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
.m_axis_data_tvalid(dmf_tvalid_interp4_i),
.m_axis_data_tdata (dmf_tdata_interp4_i)
// fir_dmf_interp4 u_fir_dmf_interp4_i (
// .aclk (clk_4x),
// .s_axis_data_tvalid(dmf_s_valid),
// .s_axis_data_tready(),
// .s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
// .m_axis_data_tvalid(dmf_tvalid_interp4_i),
// .m_axis_data_tdata (dmf_tdata_interp4_i)
// );
// fir_dmf_interp4 u_fir_dmf_interp4_q (
// .aclk (clk_4x),
// .s_axis_data_tvalid(dmf_s_valid),
// .s_axis_data_tready(),
// .s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
// .m_axis_data_tvalid(dmf_tvalid_interp4_q),
// .m_axis_data_tdata (dmf_tdata_interp4_q)
// );
// dmf filter
fir_dmf_interp16 u_fir_dmf_interp16_i (
.aclk (clk_4x), // input wire aclk
.s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(dmf_tvalid_interp16_i), // output wire m_axis_data_tvalid
.m_axis_data_tdata (dmf_tdata_interp16_i) // output wire [31 : 0] m_axis_data_tdata
);
fir_dmf_interp4 u_fir_dmf_interp4_q (
.aclk (clk_4x),
.s_axis_data_tvalid(dmf_s_valid),
.s_axis_data_tready(),
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
.m_axis_data_tvalid(dmf_tvalid_interp4_q),
.m_axis_data_tdata (dmf_tdata_interp4_q)
fir_dmf_interp16 u_fir_dmf_interp16_q (
.aclk (clk_4x), // input wire aclk
.s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(dmf_tvalid_interp16_q), // output wire m_axis_data_tvalid
.m_axis_data_tdata (dmf_tdata_interp16_q) // output wire [31 : 0] m_axis_data_tdata
);
wire [7:0] cnt_chu_seq_sync_max_vio;
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
wire mag_valid;
wire frame_sync_4x;
// wire frame_sync_pulse;
wire frame_sync_pulse; // in baseband process clock domain, quater clock
reg flag_frame_sync; // active high level
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -282,9 +330,9 @@ module RecvTop (
) u_MagnitudeEstimator (
.clk (clk_4x),
.rst (rst),
.vec_valid(dmf_tvalid_interp4_i),
.I (dmf_tdata_interp4_i[20:0]),
.Q (dmf_tdata_interp4_q[20:0]),
.vec_valid(dmf_tvalid_interp16_i),
.I (dmf_tdata_interp16_i[20:0]),
.Q (dmf_tdata_interp16_q[20:0]),
.mag (mag),
.mag_valid(mag_valid)
);
@@ -301,8 +349,11 @@ module RecvTop (
.frame_sync_pulse() // under clk_4x
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
// ! ATTENTION
// frame_sync_pulse is under clk_quarter
always @(posedge clk_quarter) begin
if (frame_sync_pulse && ~flag_frame_sync) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
@@ -314,7 +365,9 @@ module RecvTop (
end
end
always @(posedge clk) begin
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
always @(posedge clk_quarter) begin
if (rst) begin
flag_frame_sync <= 0;
end
@@ -327,45 +380,71 @@ module RecvTop (
end
wire [ 9:0] FrameSync_douti;
wire [ 9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
wire [9:0] FrameSync_douti;
wire [9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
wire [9:0] dagc_data_in_i;
wire [9:0] dagc_data_in_q;
// * lost the connection with other nodes
reg [20:0] cnt_lost;
reg framelost;
reg [1:0] cnt_downsample = 0;
wire pulse_downsample_enable;
assign pulse_downsample_enable = (cnt_downsample == 3);
always @(posedge clk) begin
if (rst_frame_sync) begin
cnt_lost <= 21'd0;
framelost <= 1'b0;
end
else begin
if (cnt_lost >= 21'd750000) begin
cnt_lost <= 21'd0;
framelost <= 1'b1;
end
else begin
cnt_lost <= 21'd1 + cnt_lost;
framelost <= 1'b0;
end
end
cnt_downsample <= cnt_downsample + 1;
end
fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_i (
.rst (rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(clk_quarter), // input wire rd_clk
.din (mf_data_interp16_i[31-:10]), // input wire [9 : 0] din
.wr_en (pulse_downsample_enable), // input wire wr_en
.rd_en (1), // input wire rd_en
.dout (mf_data_downsample_i), // output wire [9 : 0] dout
.full (), // output wire full
.empty () // output wire empty
);
fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_q (
.rst (rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(clk_quarter), // input wire rd_clk
.din (mf_data_interp16_q[31-:10]), // input wire [9 : 0] din
.wr_en (pulse_downsample_enable), // input wire wr_en
.rd_en (1), // input wire rd_en
.dout (mf_data_downsample_q), // output wire [9 : 0] dout
.full (), // output wire full
.empty () // output wire empty
);
//* CLOCK_QUARTER DOMAIN
shift_register_64 u_shift_register_64_i (
.D (mf_data_downsample_i), // input wire [9 : 0] D
.CLK(clk_quarter), // input wire CLK
.Q (dagc_data_in_i) // output wire [9 : 0] Q
);
shift_register_64 u_shift_register_64_q (
.D (mf_data_downsample_q), // input wire [9 : 0] D
.CLK(clk_quarter), // input wire CLK
.Q (dagc_data_in_q) // output wire [9 : 0] Q
);
DAGC_v2 DAGC_v2 (
.clk (clk),
.clk (clk_quarter),
.rst (~flag_mgc_done),
.mgc1_rdy (MF_rdy),
.framesync_d0 (flag_frame_sync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(mf_data_interp4_i[29-:10]), // input,
.matchfilterout_q(mf_data_interp4_q[29-:10]), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
.matchfilterout_i(dagc_data_in_i), // input,
.matchfilterout_q(dagc_data_in_q), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
// debug
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
@@ -380,8 +459,8 @@ module RecvTop (
// CFO estimation
freqestm freqestm (
.clk (clk),
.rst (mgc_start),
.clk (clk_quarter),
.rst (mgc_start_quarter),
.mgc_rdy (mgc_rdy),
.framesync (dagc_rdy),
.datain_i (DAGC_out_i),
@@ -396,7 +475,7 @@ module RecvTop (
//位同步
wire [1:0] cnt_tsync;
TimeSync_top TimeSync_top (
.clk (clk),
.clk (clk_quarter),
.rst (rst_frame_sync),
.dini (freqdataout_i),
.dinq (freqdataout_q),
@@ -417,7 +496,7 @@ module RecvTop (
// SC-FDE
SC_FDE_TOP SC_FDE_TOP_djy (
.clk (clk),
.clk (clk_quarter),
.rst (rst_frame_sync),
// param
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
@@ -451,7 +530,7 @@ module RecvTop (
wire [9:0] phase_adjust_douti;
wire [9:0] phase_adjust_doutq;
phase_adjust phase_adjust (
.clk (clk),
.clk (clk_quarter),
.rst (rst_frame_sync),
.din_i (SC_FDE_douti),
.din_q (SC_FDE_doutq),
@@ -467,8 +546,8 @@ module RecvTop (
wire [7:0] IQmergedout;
IQmerge IQmerge (
.clk (clk),
.clk2 (clk_2x),
.clk (clk_quarter),
.clk2 (clk_half),
.rst (rst2 || rst_frame_sync),
.nd (phase_adjust_rdy),
.framesync (framesync_tsync),
@@ -487,7 +566,7 @@ module RecvTop (
wire [8:0] total_frames;
CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
.clk (clk_2x),
.clk (clk_half),
.Rst (rst2 || rst_frame_sync),
.FrameSync (ldpcsyncin),
.Nd (IQmergerdy),
@@ -501,8 +580,8 @@ module RecvTop (
);
extract_mac_frame u_extract_mac_frame (
.clk (clk_2x),
.rst (rst2 || rst_frame_sync || ~flag_frame_sync),
.clk (clk_half),
.rst (rst2 || rst_frame_sync),
.ldpc_dec_out_start (LDPC_SyncOut),
.ldpc_dec_out_valid (LDPC_Rdy),
.ldpc_dec_out_data (LDPC_Dout),
@@ -512,6 +591,22 @@ module RecvTop (
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
);
reg err_flag;
reg err_flag_d1;
// reg err_flag_pos;
always @(posedge clk) begin
if (rst2 || rst_frame_sync) begin
err_flag <= 0;
end
else if (total_frames == 105 && bad_frames > 0) begin
err_flag <= 1;
end
err_flag_d1 <= err_flag;
err_flag_pos <= err_flag & ~err_flag_d1;
end
@@ -530,60 +625,62 @@ module RecvTop (
);
xpm_cdc_pulse #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) xpm_cdc_frame_sync_pulse_inst (
.dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
// transfer is correctly initiated on src_pulse input. This output is
// combinatorial unless REG_OUTPUT is set to 1.
.dest_clk (clk), // 1-bit input: Destination clock.
.dest_rst (), // 1-bit input: optional; required when RST_USED = 1
.src_clk (clk_4x), // 1-bit input: Source clock.
.src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
// destination clock domain. The minimum gap between each pulse transfer must be
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
// between the falling edge of a src_pulse to the rising edge of the next
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
// will generate a pulse the size of one dest_clk period in the destination
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
// src_rst and/or dest_rst are asserted.
.src_rst () // 1-bit input: optional; required when RST_USED = 1
.DEST_SYNC_FF (4),
.INIT_SYNC_FF (1),
.REG_OUTPUT (1),
.RST_USED (0),
.SIM_ASSERT_CHK(1)
) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_1x (
.dest_pulse(frame_sync_pulse_1x),
.dest_clk (clk),
.dest_rst (),
.src_clk (clk_4x),
.src_pulse (frame_sync_4x),
.src_rst ()
);
xpm_cdc_pulse #(
.DEST_SYNC_FF (4),
.INIT_SYNC_FF (1),
.REG_OUTPUT (1),
.RST_USED (0),
.SIM_ASSERT_CHK(1)
) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_quarter (
.dest_pulse(frame_sync_pulse),
.dest_clk (clk_quarter),
.dest_rst (),
.src_clk (clk_4x),
.src_pulse (frame_sync_4x),
.src_rst ()
);
// ***** debug *****
vio_recv_top u_vio_recv_top (
.clk (clk),
.clk (clk_quarter),
.probe_out0(cnt_chu_seq_sync_max_vio)
);
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
.clk (clk_quarter),
.probe0 (dagc_data_in_i), // width: 12
.probe1 (dagc_data_in_q), // width: 12
.probe2 (flag_mgc_done), // width: 1
.probe3 (flag_frame_sync), // width: 1
.probe4 (flag_cfo_done), // width: 1
.probe5 (freqdataout_i), // width: 10
.probe6 (freqdataout_q), // width: 10
.probe7 (IntpARdy), // width: 1
.probe8 (IntpOuti), // width: 10
.probe9 (IntpOutq), // width: 10
.probe10(nd_SC_FDE_dout), // width: 1
.probe11(SC_FDE_douti), // width: 10
.probe12(SC_FDE_doutq), // width: 10
.probe13(phase_adjust_rdy), // width: 1
.probe14(phase_adjust_douti), // width: 10
.probe15(phase_adjust_doutq), // width: 10
.probe16(good_frames), // width: 9
.probe17(bad_frames) // width: 9
);