ZoroGH/MM7020
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases 3 Wiki Activity

feat(sys): change speed to 3.125, test pass.

Browse Source
This commit is contained in:
ZoroGH
2024-09-05 20:42:30 +08:00
parent 5e8d69a0b0
commit 3990e3081a
12 changed files with 624 additions and 515 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hdl/ad9361_mgc_pin_ctrl.v
+12 -12
View File
@@ -162,18 +162,18 @@ module ad9361_mgc_pin_ctrl (
// .probe_out0(start) // output wire [0 : 0] probe_out0
// );
// ila_ad9361_mgc u_ila_ad9361_mgc (
// .clk (clk), // input wire clk
// .probe0(start_posedge), // input wire [0:0] probe0
// .probe1(rx_data_i), // input wire [11:0] probe1
// .probe2(u_power_measure.cs), // input wire [2:0] probe2
// .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
// .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
// .probe5(flag_too_high), // input wire [0:0] probe5
// .probe6(flag_too_low), // input wire [0:0] probe6
// .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
// .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
// );
ila_ad9361_mgc u_ila_ad9361_mgc (
.clk (clk), // input wire clk
.probe0(start_posedge), // input wire [0:0] probe0
.probe1(rx_data_i), // input wire [11:0] probe1
.probe2(u_power_measure.cs), // input wire [2:0] probe2
.probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
.probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
.probe5(flag_too_high), // input wire [0:0] probe5
.probe6(flag_too_low), // input wire [0:0] probe6
.probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
.probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
);
endmodule