ZoroGH/MM7020
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases 3 Wiki Activity

feat(sys): change speed to 3.125, test pass.

Browse Source
This commit is contained in:
ZoroGH
2024-09-05 20:42:30 +08:00
parent 5e8d69a0b0
commit 3990e3081a
12 changed files with 624 additions and 515 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hdl/system_top.v
+44 -34
View File
@@ -70,6 +70,8 @@ module system_top (
wire clk_1x;
wire clk_2x;
wire clk_4x;
wire clk_quarter;
wire clk_half;
// emio
wire [31:0] gpio_i;
@@ -134,6 +136,8 @@ module system_top (
wire tx_start_vio;
reg tx_start_vio_d1;
wire tx_start_vio_pos;
// rx
wire rx_err_flag_pos;
// vio
wire rst_manual;
@@ -174,13 +178,15 @@ module system_top (
// clock domain - ad9361 rx & tx
clk_wiz_baseband u_clk_wiz_baseband (
// Clock out ports
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
.clk_quarter(clk_quarter),
.clk_half (clk_half),
// Status and control signals
.locked (locked), // output locked
.locked (locked), // output locked
// Clock in ports
.clk_src(ad9361_rx_clk) // input clk_src
.clk_src (ad9361_rx_clk) // input clk_src
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
@@ -218,15 +224,16 @@ module system_top (
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl_tx_intr (intr_2ps | intr_2ps_vio_pos),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_2x),
.clk_rx_data_src_fifo (clk_half),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
@@ -245,17 +252,17 @@ module system_top (
.uart_tx (uart_tx)
);
// tdma u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (tdma_flag_is_master),
// .flag_frame_sync(frame_sync_pulse),
// .tdma_slot_len (tdma_slot_len[23:0]),
// .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (tdma_flag_is_master),
.flag_frame_sync(frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
@@ -303,9 +310,9 @@ module system_top (
Transmitter u_Transmitter (
.clk (clk_1x),
.rst (rst_sys | phy_rst),
.speed_mode (2),
.speed_mode (0),
.send_data_ready (send_data_ready),
.send_start (tx_start | tx_start_vio_pos),
.send_start (tx_start),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
@@ -322,13 +329,15 @@ module system_top (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst | rx_rst_vio),
.clk_half (clk_half),
.clk_quarter (clk_quarter),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse (flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.frame_sync_pulse_1x (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
@@ -340,7 +349,8 @@ module system_top (
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.err_flag_pos (rx_err_flag_pos)
);
@@ -388,22 +398,22 @@ module system_top (
// );
assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
always @(posedge clk_1x) begin
tx_start_vio_d1 <= tx_start_vio;
end
// assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// always @(posedge clk_1x) begin
// tx_start_vio_d1 <= tx_start_vio;
// end
assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
always @(posedge clk_1x) begin
intr_2ps_vio_d1 <= intr_2ps_vio;
end
// assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// always @(posedge clk_1x) begin
// intr_2ps_vio_d1 <= intr_2ps_vio;
// end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(rx_rst_vio),
.probe_out1(tx_start_vio),
.probe_out2(intr_2ps_vio)
.probe_out0(node_id),
.probe_out1(max_slot_num),
.probe_out2(rst_manual)
);
endmodule