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feat(sys): update tdma param updated from ps

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ZoroGH
2024-10-09 09:45:04 +08:00
parent 3990e3081a
commit 4b4f9dc671
4 changed files with 228 additions and 151 deletions
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hdl/phy_control.v
+24 -9
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@@ -71,7 +71,10 @@ module phy_control #(
// tdma parameters
output wire tdma_flag_is_master,
output wire [31:0] tdma_slot_len,
output wire [31:0] tdma_tic_2_ps
output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id
//--- ADD YOUR OWN PORTS END
);
@@ -339,12 +342,16 @@ module phy_control #(
localparam integer PHY_SR = 'h00000004 >> 2; // RW
localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
// Register definitions
reg [31:0] phy_cr_reg = 32'h0;
reg [31:0] phy_sr_reg = 32'h0;
reg [31:0] tdma_slot_len_reg = 32'h0;
reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0;
// Register Reading
always @(posedge local_clk) begin
@@ -369,25 +376,33 @@ module phy_control #(
PHY_SR: phy_sr_reg <= up_wdata_s;
TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
endcase
end
else begin
// self logic
if (tdma_recv_id_reg[8] == 1) begin
tdma_recv_id_reg[8] <= 0;
end
end
end
end
// control reg definition
assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_tx_iq_reverse = phy_cr_reg[2];
assign phy_rx_iq_reverse = phy_cr_reg[3];
assign tdma_flag_is_master = phy_cr_reg[4];
assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_tx_iq_reverse = phy_cr_reg[2];
assign phy_rx_iq_reverse = phy_cr_reg[3];
assign tdma_flag_is_master = phy_cr_reg[4];
// tdma
assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_id_cfg = tdma_id_cfg_reg;
// received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
vio_phy_param u_vio_phy_param (
.clk (local_clk),