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feat(sys): update tdma param updated from ps

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ZoroGH
2024-10-09 09:45:04 +08:00
parent 3990e3081a
commit 4b4f9dc671
4 changed files with 228 additions and 151 deletions
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hdl/system_top.v
+74 -110
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@@ -124,6 +124,10 @@ module system_top (
wire tdma_flag_is_master;
wire [31:0] tdma_slot_len;
wire [31:0] tdma_tic_2_ps;
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
// tx signal
wire frame_sync_pulse;
@@ -190,107 +194,91 @@ module system_top (
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_half),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.clk_rx_data_src_fifo (clk_half),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
// phy clock and rst to ps
.clk_phy (clk_1x),
.rst_phy_n (~rst_sys),
// phy control signal
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (tdma_flag_is_master),
.flag_frame_sync(frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
.clk (clk_1x),
.rst (rst_sys),
.flag_frame_sync (frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]),
.local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start
enc_control u_enc_control (
@@ -353,11 +341,6 @@ module system_top (
.err_flag_pos (rx_err_flag_pos)
);
// ---- PHY layer logic end
@@ -397,23 +380,4 @@ module system_top (
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// );
// assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// always @(posedge clk_1x) begin
// tx_start_vio_d1 <= tx_start_vio;
// end
// assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// always @(posedge clk_1x) begin
// intr_2ps_vio_d1 <= intr_2ps_vio;
// end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(node_id),
.probe_out1(max_slot_num),
.probe_out2(rst_manual)
);
endmodule