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feat(sys): update tdma param updated from ps

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ZoroGH
2024-10-09 09:45:04 +08:00
parent 3990e3081a
commit 4b4f9dc671
4 changed files with 228 additions and 151 deletions
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contraint/mm7020_timing.xdc
+4 -1
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@@ -9,7 +9,10 @@ set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rx_iq_reverse]
set_false_path -through [get_nets tdma_flag_is_master] set_false_path -through [get_nets tdma_flag_is_master]
set_false_path -through [get_nets tdma_slot_len*] set_false_path -through [get_nets tdma_slot_len*]
set_false_path -through [get_nets tdma_tic_2_ps*] set_false_path -through [get_nets tdma_tic_2_ps*]
set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
set_false_path -through [get_nets rx_rst]
set_false_path -through [get_nets rst_sys]
set_false_path -through [get_nets rst20]
set_false_path -through [get_nets u_RecvTop/flag_mgc_done] set_false_path -through [get_nets u_RecvTop/flag_mgc_done]
set_false_path -through [get_nets u_RecvTop/flag_frame_sync] set_false_path -through [get_nets u_RecvTop/flag_frame_sync]
hdl/phy_control.v
+24 -9
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@@ -71,7 +71,10 @@ module phy_control #(
// tdma parameters // tdma parameters
output wire tdma_flag_is_master, output wire tdma_flag_is_master,
output wire [31:0] tdma_slot_len, output wire [31:0] tdma_slot_len,
output wire [31:0] tdma_tic_2_ps output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id
//--- ADD YOUR OWN PORTS END //--- ADD YOUR OWN PORTS END
); );
@@ -339,12 +342,16 @@ module phy_control #(
localparam integer PHY_SR = 'h00000004 >> 2; // RW localparam integer PHY_SR = 'h00000004 >> 2; // RW
localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2; localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2; localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
// Register definitions // Register definitions
reg [31:0] phy_cr_reg = 32'h0; reg [31:0] phy_cr_reg = 32'h0;
reg [31:0] phy_sr_reg = 32'h0; reg [31:0] phy_sr_reg = 32'h0;
reg [31:0] tdma_slot_len_reg = 32'h0; reg [31:0] tdma_slot_len_reg = 32'h0;
reg [31:0] tdma_tic_2_ps_reg = 32'h0; reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0;
// Register Reading // Register Reading
always @(posedge local_clk) begin always @(posedge local_clk) begin
@@ -369,25 +376,33 @@ module phy_control #(
PHY_SR: phy_sr_reg <= up_wdata_s; PHY_SR: phy_sr_reg <= up_wdata_s;
TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s; TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s; TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
endcase endcase
end end
else begin else begin
// self logic // self logic
if (tdma_recv_id_reg[8] == 1) begin
tdma_recv_id_reg[8] <= 0;
end
end end
end end
end end
// control reg definition // control reg definition
assign phy_rst = ~phy_cr_reg[0]; assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1]; assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_tx_iq_reverse = phy_cr_reg[2]; assign phy_tx_iq_reverse = phy_cr_reg[2];
assign phy_rx_iq_reverse = phy_cr_reg[3]; assign phy_rx_iq_reverse = phy_cr_reg[3];
assign tdma_flag_is_master = phy_cr_reg[4]; assign tdma_flag_is_master = phy_cr_reg[4];
// tdma // tdma
assign tdma_slot_len = tdma_slot_len_reg; assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg; assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_id_cfg = tdma_id_cfg_reg;
// received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
vio_phy_param u_vio_phy_param ( vio_phy_param u_vio_phy_param (
.clk (local_clk), .clk (local_clk),
hdl/system_top.v
+74 -110
View File
@@ -124,6 +124,10 @@ module system_top (
wire tdma_flag_is_master; wire tdma_flag_is_master;
wire [31:0] tdma_slot_len; wire [31:0] tdma_slot_len;
wire [31:0] tdma_tic_2_ps; wire [31:0] tdma_tic_2_ps;
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
// tx signal // tx signal
wire frame_sync_pulse; wire frame_sync_pulse;
@@ -190,107 +194,91 @@ module system_top (
); );
MM7020_BD_wrapper u_MM7020_BD_wrapper ( MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk), .ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn), .ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso), .ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi), .ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron), .clk_ps (clk_poweron),
.rst_ps (rst_sys), .rst_ps (rst_sys),
// ddr // ddr
.ddr_addr (ddr_addr), .ddr_addr (ddr_addr),
.ddr_ba (ddr_ba), .ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n), .ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n), .ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p), .ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke), .ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n), .ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm), .ddr_dm (ddr_dm),
.ddr_dq (ddr_dq), .ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n), .ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p), .ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt), .ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n), .ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n), .ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n), .ddr_we_n (ddr_we_n),
// fixed io // fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio), .fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb), .fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps // gpio ps
.gpio_i (gpio_i), .gpio_i (gpio_i),
.gpio_o (gpio_o), .gpio_o (gpio_o),
.gpio_t (gpio_t), .gpio_t (gpio_t),
// intr pl to ps // intr pl to ps
.pl_tx_intr (intr_2ps), .pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast), .pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos), .pl_intr0 (rx_err_flag_pos),
// tx fifo // tx fifo
.tx_data_src_count (tx_data_src_count), .tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata), .tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready), .tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid), .tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo // rx fifo
.clk_rx_data_src_fifo (clk_half), .clk_rx_data_src_fifo (clk_half),
.rst_rx_data_src_fifo (rx_rst), .rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata), .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast), .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready), .rx_data_src_fifo_tready (rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid), .rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
// phy clock and rst to ps
.clk_phy (clk_1x),
.rst_phy_n (~rst_sys),
// phy control signal // phy control signal
.phy_rst (phy_rst), .phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag), .phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse), .phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse), .phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master), .tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len), .tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps), .tdma_tic_2_ps (tdma_tic_2_ps),
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
// uart // uart
.uart_rx (uart_rx), .uart_rx (uart_rx),
.uart_tx (uart_tx) .uart_tx (uart_tx)
); );
tdma u_tdma ( tdma u_tdma (
.clk (clk_1x), .clk (clk_1x),
.rst (rst_sys), .rst (rst_sys),
.flag_is_master (tdma_flag_is_master), .flag_frame_sync (frame_sync_pulse),
.flag_frame_sync(frame_sync_pulse), .tdma_slot_len (tdma_slot_len[23:0]),
.tdma_slot_len (tdma_slot_len[23:0]), .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]), .tdma_slot_num (tdma_id_cfg[15:8]),
.intr_2ps (intr_2ps), .local_id (tdma_id_cfg[7:0]),
.tx_start (tx_start), .recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.rx_rst (rx_rst) .recevied_cur_slot_id (tdma_recv_cur_slot_id),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
); );
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start // ---- PHY layer logic start
enc_control u_enc_control ( enc_control u_enc_control (
@@ -353,11 +341,6 @@ module system_top (
.err_flag_pos (rx_err_flag_pos) .err_flag_pos (rx_err_flag_pos)
); );
// ---- PHY layer logic end // ---- PHY layer logic end
@@ -397,23 +380,4 @@ module system_top (
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1 // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// ); // );
// assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// always @(posedge clk_1x) begin
// tx_start_vio_d1 <= tx_start_vio;
// end
// assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// always @(posedge clk_1x) begin
// intr_2ps_vio_d1 <= intr_2ps_vio;
// end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(node_id),
.probe_out1(max_slot_num),
.probe_out2(rst_manual)
);
endmodule endmodule
hdl/tdma.v
+126 -31
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@@ -14,53 +14,144 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID // ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE // ! WHEN U INSTANTIATE THIS MODULE
module tdma #( module tdma #(
// parameter TIC_FRAME_SYNC = 44392 parameter TIC_FRAME_SYNC = 44432
parameter TIC_FRAME_SYNC = 177568
) ( ) (
input clk, input clk,
input rst, input rst,
input flag_is_master, // PHY parameter
input flag_frame_sync, input flag_frame_sync,
// general parameter, update only once
input wire [23:0] tdma_slot_len, input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps, input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num,
input wire [ 7:0] local_id, // ID number for this device
// update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
input wire [ 7:0] recevied_cur_slot_id,
output intr_2ps, output intr_2ps,
output tx_start, output tx_start,
output reg rx_rst output reg rx_rst
); );
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ******** // ******** Wire & Reg ********
reg flag_is_tx_slot; reg flag_next_slot_is_tx_slot;
reg [23:0] cnt; reg [23:0] cnt_tdma_slot_len;
reg [ 7:0] cur_slot_id;
wire flag_end_of_one_slot; // the last period of the slot
wire [23:0] tdma_tic_frame_sync_vio;
// fsm
localparam S_IDLE = 0;
localparam S_RX = 1;
localparam S_TX = 2;
reg [1:0] cs = 0;
reg [1:0] ns = 0;
// ******** Assingment ******** // ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10); assign flag_end_of_one_slot = (cnt_tdma_slot_len == tdma_slot_len - 1);
assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1); assign tx_start = (cs == S_TX) & (cnt_tdma_slot_len == 16'd10);
assign intr_2ps = flag_next_slot_is_tx_slot & (cnt_tdma_slot_len == tdma_tic_2_ps - 1);
// ******** Logic Block ******** // ******** Logic Block ********
// fsm
always @(posedge clk) begin
if (rst) begin
cs <= S_IDLE;
end
else begin
cs <= ns;
end
end
// conditional transition
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
// if this device is master node, ps should first send one packet to the fifo
if (local_id == 1) begin
ns = S_TX;
end
else if (recevied_cur_slot_id_valid) begin
ns = S_RX;
end
end
S_RX: begin
if (flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_TX;
end
end
S_TX: begin
if (~flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_RX;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin always @(posedge clk) begin
if (rst) begin if (rst) begin
cnt <= 0; cnt_tdma_slot_len <= 0;
end
else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_tic_frame_sync_vio;
end end
else begin else begin
if (!flag_is_master && flag_frame_sync) begin // if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
// slave update cnt // cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
cnt <= TIC_FRAME_SYNC; // end
// else begin
// cnt_tdma_slot_len <= 0;
// end
if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0;
end end
else begin else begin
// master cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
if (cnt < tdma_slot_len - 1) begin end
cnt <= cnt + 1; end
end
always @(*) begin
if (cs == S_TX || cnt_tdma_slot_len <= 10) begin
rx_rst <= 1;
end
else begin
rx_rst <= 0;
end
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
if (ns == S_TX) begin // indicating master node
cur_slot_id <= 1;
end
else if (recevied_cur_slot_id_valid) begin // from ps update, first sync, indicating slave
cur_slot_id <= recevied_cur_slot_id;
end
else begin
cur_slot_id <= 0;
end
end
else begin
if (recevied_cur_slot_id_valid) begin // from ps update
cur_slot_id <= recevied_cur_slot_id;
end
else if (flag_end_of_one_slot) begin // at the changing moment
if (cur_slot_id == tdma_slot_num) begin
cur_slot_id <= 1;
end end
else begin else begin
cnt <= 0; cur_slot_id <= cur_slot_id + 1;
end end
end end
end end
@@ -68,11 +159,11 @@ module tdma #(
always @(posedge clk) begin always @(posedge clk) begin
if (flag_is_master) begin if (local_id == 1) begin
rx_rst <= 1; flag_next_slot_is_tx_slot <= (cur_slot_id == tdma_slot_num);
end end
else begin else begin
rx_rst <= flag_is_master | (cnt <= 16'd4); flag_next_slot_is_tx_slot <= (cur_slot_id + 1 == local_id);
end end
end end
@@ -81,20 +172,24 @@ module tdma #(
// ******** Debug ******** // ******** Debug ********
vio_tdma u_vio_tdma ( vio_tdma u_vio_tdma (
.clk (clk), .clk (clk),
.probe_in0(tdma_slot_len), .probe_in0 (tdma_slot_len),
.probe_in1(tdma_tic_2_ps), .probe_in1 (tdma_tic_2_ps),
.probe_in2(flag_is_master) .probe_in2 (tdma_slot_num),
.probe_in3 (local_id),
.probe_out0(tdma_tic_frame_sync_vio)
); );
ila_mac_layer u_ila_mac_layer ( ila_mac_layer u_ila_mac_layer (
.clk (clk), .clk (clk),
.probe0(cnt), // width: 24 .probe0(cnt_tdma_slot_len), // width: 24
.probe1(tx_start), // width: 1 .probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1 .probe2(rx_rst), // width: 1
.probe3(flag_is_master), // width: 1 .probe3(cur_slot_id), // width: 8
.probe4(intr_2ps), // width: 1 .probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync) // width: 1 .probe5(flag_frame_sync), // width: 1
.probe6(recevied_cur_slot_id), // width: 8
.probe7(recevied_cur_slot_id_valid) // width: 1
); );