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fix(system): adjust cp len, frame sync pos, IQ map

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ZoroGH
2024-07-25 23:32:28 +08:00
parent 0bedb6c2ef
commit 7751749856
9 changed files with 10900 additions and 42 deletions
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hdl/Transmitter.v
+36 -12
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@@ -9,16 +9,16 @@
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
// * *************************************************** *
// * Create Date: 2023/12/18
// * Update Date: 2024/03/17
// * Update Date: 2024/07/24
// NOTE: 接口中的hop_wait和参数GAP_LEN均是为了等待，hop是为了跳频切换，gap是为了满足帧同步延迟,！！！将hop_wait设置为0并不能去掉改状态
module Transmitter #(
parameter AGC_HEADER_LEN = 2130,
parameter AGC_HEADER_LEN = 10586,
parameter FRAME_HEADER_LEN = 512,
parameter BLOCK_NUM = 28,
parameter PHASE1_LEN = 2112, // (8 cp + 256 sym)* 8 ( total 2048 valid sym)
parameter PREFIX_LEN = 8,
parameter CHU_SEQ_LEN = 128,
parameter BLOCK_NUM = 42,
parameter PHASE1_LEN = 2880, // (32 cp + 256 sym)* 10 ( total 2880 valid sym)
parameter PREFIX_LEN = 32,
parameter CHU_SEQ_LEN = 256,
parameter GAP_LEN = 160
) (
// general
@@ -65,10 +65,12 @@ module Transmitter #(
reg [ 3:0] interp;
reg [ 3:0] cnt_interp;
reg [13:0] agc_addr;
wire [ 1:0] agc_data;
reg [ 8:0] mseqs_addr;
reg [ 8:0] mseqs_addr_d1;
reg [ 8:0] mseqs_addr_d2;
reg [ 6:0] chu_seq_addr;
reg [ 7:0] chu_seq_addr = 0;
wire [31:0] chu_seq;
wire mseqs;
reg [31:0] bb_wave_out_i; // shape filter result
@@ -86,7 +88,7 @@ module Transmitter #(
reg [ 3:0] rtz; // return to zero
reg [12:0] addr_tx_test = 'd0;
wire [7:0] data_tx_test;
wire [ 7:0] data_tx_test;
// ******** Assingment ********
@@ -328,7 +330,11 @@ module Transmitter #(
// truncation
always @(*) begin
if (cs == S_SEND_FRAME_HEADER) begin
if (cs == S_SEND_AGC) begin
m_fir_tdata_i = agc_data[0] ? 16'h8001 : 16'h7FFF;
m_fir_tdata_q = agc_data[1] ? 16'h8001 : 16'h7FFF;
end
else if (cs == S_SEND_FRAME_HEADER) begin
m_fir_tdata_i = mseqs ? 16'h8001 : 16'h7FFF;
m_fir_tdata_q = mseqs ? 16'h8001 : 16'h7FFF;
end
@@ -336,7 +342,7 @@ module Transmitter #(
m_fir_tdata_i = tx_data_src_tdata[15-:16];
m_fir_tdata_q = tx_data_src_tdata[31-:16];
end
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC) begin
else if (cs == S_SEND_CHU_POS) begin
m_fir_tdata_i = chu_seq[15-:16];
m_fir_tdata_q = chu_seq[31-:16];
end
@@ -417,11 +423,23 @@ module Transmitter #(
end
end
// chu seq addr control
always @(posedge clk) begin
if (cs == S_IDLE) begin
agc_addr <= 0;
end
else if (cs == S_SEND_AGC) begin
if (fir_tvalid_in == 1'b1) begin
agc_addr <= agc_addr + 1;
end
end
end
// chu seq addr control
always @(posedge clk) begin
if (ns != cs) begin
// chu_seq_addr <= 7'h7F - 7'h7; // 8 cp
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 8 cp
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 32 cp
end
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC || cs == S_SEND_CHU_NEG) begin
if (fir_tvalid_in == 1'b1) begin
@@ -456,6 +474,12 @@ module Transmitter #(
// ******** Inst ********
bram_agc_header u_bram_agc_header (
.clka (clk), // input wire clka
.addra(agc_addr), // input wire [13 : 0] addra
.douta(agc_data) // output wire [1 : 0] douta
);
bram_m_seqs_512 u_bram_m_seqs_512 (
.clka (clk),
.addra(mseqs_addr),
@@ -465,7 +489,7 @@ module Transmitter #(
bram_chu_seq u_bram_chu_seq (
.clka (clk), // input wire clka
.addra(chu_seq_addr), // input wire [6 : 0] addra
.addra(chu_seq_addr), // input wire [7 : 0] addra
.douta(chu_seq) // output wire [31 : 0] douta
);