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fix(system): adjust cp len, frame sync pos, IQ map

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ZoroGH
2024-07-25 23:32:28 +08:00
parent 0bedb6c2ef
commit 7751749856
9 changed files with 10900 additions and 42 deletions
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hdl/enc_control.v
+4 -4
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@@ -134,7 +134,7 @@ module enc_control #(
// and the width convert fifo is empty
// and the finally stage fifo is almost empty
// TODO:check the conditions, done 2024年5月27日
if (s_axis_fifo_tvalid && data_src_count != 0 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
if (s_axis_fifo_tvalid && data_src_count >= 32 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
ns = S_START;
end
else begin
@@ -297,13 +297,13 @@ module enc_control #(
add_prefix #(
.WIDTH (2), // ! if this parameter is changed, make sure the shift IP inside is also changed
.DATA_LEN (256),
.PREFIX_LEN(8)
.DATA_LEN (256), //! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
.PREFIX_LEN(32)
) u_add_prefix (
.clk (clk),
.start (add_prefix_start),
.ready (add_prefix_in_ready),
.data_in (data_add_prefix_in),
.data_in ({data_add_prefix_in[0], data_add_prefix_in[1]}), // NOTE : reverse to adjust to IQmerge module
.data_in_ready (data_add_prefix_in_ready),
.data_out (data_add_prefix_out),
.data_out_valid(data_add_prefix_out_valid)