ZoroGH/MM7020
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases 3 Wiki Activity

fix(system): adjust cp len, frame sync pos, IQ map

Browse Source
This commit is contained in:
ZoroGH
2024-07-25 23:32:28 +08:00
parent 0bedb6c2ef
commit 7751749856
9 changed files with 10900 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
coe/agc.coe
+10589
View File
File diff suppressed because it is too large Load Diff
coe/chu256.coe
+2
View File
@@ -0,0 +1,2 @@
memory_initialization_radix=16;
memory_initialization_vector=00007FFF 01927FFD 06487FD8 0E1C7F37 18F97D89 26A87A05 36BA73B5 4869698B 5A825A82 6B4A45CD 78842B1F 7F860AFB 7D89E707 7022C248 55F5A129 2F878928 00008001 CD928A5B A129AA0B 8512DC5A 827718F9 9E105268 D4E17884 1A827D39 5A825A82 7DD5176E 73B5C946 3AF28E63 E7078277 9C12B005 80280648 A69C5B9C 00007FFF 5B9C5964 7FD8F9B8 4FFB9C12 E7078277 8E63C50E 8C4B36BA E8927DD5 5A825A82 7D39E57E 2B1F877C AD989E10 827718F9 DC5A7AEE 5ED755F5 75A5CD92 00008001 8928D079 AA0B5ED7 3DB87022 7D89E707 0AFB807A 877CD4E1 BA336B4A 5A825A82 698BB797 C9468C4B 85FB26A8 18F97D89 7F37F1E4 F9B88028 80030192 00007FFF 7FFDFE6E F9B88028 80C90E1C 18F97D89 7A05D958 C9468C4B 96754869 5A825A82 45CD94B6 877CD4E1 F5057F86 7D89E707 C2488FDE AA0B5ED7 76D82F87 00008001 8A5B326E 5ED755F5 23A68512 827718F9 526861F0 2B1F877C 82C71A82 5A825A82 176E822B 8C4B36BA 719D3AF2 E7078277 B00563EE 7FD8F9B8 A464A69C 00007FFF 5964A464 80280648 63EE4FFB E7078277 C50E719D 73B5C946 822BE892 5A825A82 E57E82C7 D4E17884 61F0AD98 827718F9 7AEE23A6 A129AA0B 326E75A5 00008001 D07976D8 55F5A129 8FDE3DB8 7D89E707 807AF505 78842B1F 94B6BA33 5A825A82 B7979675 36BA73B5 D95885FB 18F97D89 F1E480C9 06487FD8 FE6E8003 00007FFF FE6E8003 06487FD8 F1E480C9 18F97D89 D95885FB 36BA73B5 B7979675 5A825A82 94B6BA33 78842B1F 807AF505 7D89E707 8FDE3DB8 55F5A129 D07976D8 00008001 326E75A5 A129AA0B 7AEE23A6 827718F9 61F0AD98 D4E17884 E57E82C7 5A825A82 822BE892 73B5C946 C50E719D E7078277 63EE4FFB 80280648 5964A464 00007FFF A464A69C 7FD8F9B8 B00563EE E7078277 719D3AF2 8C4B36BA 176E822B 5A825A82 82C71A82 2B1F877C 526861F0 827718F9 23A68512 5ED755F5 8A5B326E 00008001 76D82F87 AA0B5ED7 C2488FDE 7D89E707 F5057F86 877CD4E1 45CD94B6 5A825A82 96754869 C9468C4B 7A05D958 18F97D89 80C90E1C F9B88028 7FFDFE6E 00007FFF 80030192 F9B88028 7F37F1E4 18F97D89 85FB26A8 C9468C4B 698BB797 5A825A82 BA336B4A 877CD4E1 0AFB807A 7D89E707 3DB87022 AA0B5ED7 8928D079 00008001 75A5CD92 5ED755F5 DC5A7AEE 827718F9 AD989E10 2B1F877C 7D39E57E 5A825A82 E8927DD5 8C4B36BA 8E63C50E E7078277 4FFB9C12 7FD8F9B8 5B9C5964 00007FFF A69C5B9C 80280648 9C12B005 E7078277 3AF28E63 73B5C946 7DD5176E 5A825A82 1A827D39 D4E17884 9E105268 827718F9 8512DC5A A129AA0B CD928A5B 00008001 2F878928 55F5A129 7022C248 7D89E707 7F860AFB 78842B1F 6B4A45CD 5A825A82 4869698B 36BA73B5 26A87A05 18F97D89 0E1C7F37 06487FD8 01927FFD;
coe/fir_interp4.coe
+24 -24
View File
@@ -1,28 +1,28 @@
radix=10;
coefdata=
-1053
1199
3216
3453
1180
-2791
-6185
-6256
-1263
8366
19870
29190
-761
-441
766
1954
1708
-660
-4042
-5641
-2532
6186
18176
28624
32767
29190
19870
8366
-1263
-6256
-6185
-2791
1180
3453
3216
1199
-1053
28624
18176
6186
-2532
-5641
-4042
-660
1708
1954
766
-441
-761
;
coe/fir_interp4_0.15.coe
+28
View File
@@ -0,0 +1,28 @@
radix=10;
coefdata=
-1053
1199
3216
3453
1180
-2791
-6185
-6256
-1263
8366
19870
29190
32767
29190
19870
8366
-1263
-6256
-6185
-2791
1180
3453
3216
1199
-1053
;
hdl/RecvTop.v
+1 -1
View File
@@ -255,7 +255,7 @@ module RecvTop (
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
localparam CNT_CHU_SEQ_SYNC_MAX = 8;//! should not less than 3 due to the minimum rst of aresetn
localparam CNT_CHU_SEQ_SYNC_MAX = 40;//! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
wire mag_valid;
hdl/Transmitter.v
+36 -12
View File
@@ -9,16 +9,16 @@
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
// * *************************************************** *
// * Create Date: 2023/12/18
// * Update Date: 2024/03/17
// * Update Date: 2024/07/24
// NOTE: 接口中的hop_wait和参数GAP_LEN均是为了等待，hop是为了跳频切换，gap是为了满足帧同步延迟,！！！将hop_wait设置为0并不能去掉改状态
module Transmitter #(
parameter AGC_HEADER_LEN = 2130,
parameter AGC_HEADER_LEN = 10586,
parameter FRAME_HEADER_LEN = 512,
parameter BLOCK_NUM = 28,
parameter PHASE1_LEN = 2112, // (8 cp + 256 sym)* 8 ( total 2048 valid sym)
parameter PREFIX_LEN = 8,
parameter CHU_SEQ_LEN = 128,
parameter BLOCK_NUM = 42,
parameter PHASE1_LEN = 2880, // (32 cp + 256 sym)* 10 ( total 2880 valid sym)
parameter PREFIX_LEN = 32,
parameter CHU_SEQ_LEN = 256,
parameter GAP_LEN = 160
) (
// general
@@ -65,10 +65,12 @@ module Transmitter #(
reg [ 3:0] interp;
reg [ 3:0] cnt_interp;
reg [13:0] agc_addr;
wire [ 1:0] agc_data;
reg [ 8:0] mseqs_addr;
reg [ 8:0] mseqs_addr_d1;
reg [ 8:0] mseqs_addr_d2;
reg [ 6:0] chu_seq_addr;
reg [ 7:0] chu_seq_addr = 0;
wire [31:0] chu_seq;
wire mseqs;
reg [31:0] bb_wave_out_i; // shape filter result
@@ -86,7 +88,7 @@ module Transmitter #(
reg [ 3:0] rtz; // return to zero
reg [12:0] addr_tx_test = 'd0;
wire [7:0] data_tx_test;
wire [ 7:0] data_tx_test;
// ******** Assingment ********
@@ -328,7 +330,11 @@ module Transmitter #(
// truncation
always @(*) begin
if (cs == S_SEND_FRAME_HEADER) begin
if (cs == S_SEND_AGC) begin
m_fir_tdata_i = agc_data[0] ? 16'h8001 : 16'h7FFF;
m_fir_tdata_q = agc_data[1] ? 16'h8001 : 16'h7FFF;
end
else if (cs == S_SEND_FRAME_HEADER) begin
m_fir_tdata_i = mseqs ? 16'h8001 : 16'h7FFF;
m_fir_tdata_q = mseqs ? 16'h8001 : 16'h7FFF;
end
@@ -336,7 +342,7 @@ module Transmitter #(
m_fir_tdata_i = tx_data_src_tdata[15-:16];
m_fir_tdata_q = tx_data_src_tdata[31-:16];
end
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC) begin
else if (cs == S_SEND_CHU_POS) begin
m_fir_tdata_i = chu_seq[15-:16];
m_fir_tdata_q = chu_seq[31-:16];
end
@@ -417,11 +423,23 @@ module Transmitter #(
end
end
// chu seq addr control
always @(posedge clk) begin
if (cs == S_IDLE) begin
agc_addr <= 0;
end
else if (cs == S_SEND_AGC) begin
if (fir_tvalid_in == 1'b1) begin
agc_addr <= agc_addr + 1;
end
end
end
// chu seq addr control
always @(posedge clk) begin
if (ns != cs) begin
// chu_seq_addr <= 7'h7F - 7'h7; // 8 cp
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 8 cp
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 32 cp
end
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC || cs == S_SEND_CHU_NEG) begin
if (fir_tvalid_in == 1'b1) begin
@@ -456,6 +474,12 @@ module Transmitter #(
// ******** Inst ********
bram_agc_header u_bram_agc_header (
.clka (clk), // input wire clka
.addra(agc_addr), // input wire [13 : 0] addra
.douta(agc_data) // output wire [1 : 0] douta
);
bram_m_seqs_512 u_bram_m_seqs_512 (
.clka (clk),
.addra(mseqs_addr),
@@ -465,7 +489,7 @@ module Transmitter #(
bram_chu_seq u_bram_chu_seq (
.clka (clk), // input wire clka
.addra(chu_seq_addr), // input wire [6 : 0] addra
.addra(chu_seq_addr), // input wire [7 : 0] addra
.douta(chu_seq) // output wire [31 : 0] douta
);
hdl/add_prefix.v
+1 -1
View File
@@ -4,7 +4,7 @@ module add_prefix #(
//! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
parameter WIDTH = 2,
parameter DATA_LEN = 256,
parameter PREFIX_LEN = 8
parameter PREFIX_LEN = 32
) (
input clk,
input start,
hdl/enc_control.v
+4 -4
View File
@@ -134,7 +134,7 @@ module enc_control #(
// and the width convert fifo is empty
// and the finally stage fifo is almost empty
// TODO:check the conditions, done 2024年5月27日
if (s_axis_fifo_tvalid && data_src_count != 0 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
if (s_axis_fifo_tvalid && data_src_count >= 32 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
ns = S_START;
end
else begin
@@ -297,13 +297,13 @@ module enc_control #(
add_prefix #(
.WIDTH (2), // ! if this parameter is changed, make sure the shift IP inside is also changed
.DATA_LEN (256),
.PREFIX_LEN(8)
.DATA_LEN (256), //! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
.PREFIX_LEN(32)
) u_add_prefix (
.clk (clk),
.start (add_prefix_start),
.ready (add_prefix_in_ready),
.data_in (data_add_prefix_in),
.data_in ({data_add_prefix_in[0], data_add_prefix_in[1]}), // NOTE : reverse to adjust to IQmerge module
.data_in_ready (data_add_prefix_in_ready),
.data_out (data_add_prefix_out),
.data_out_valid(data_add_prefix_out_valid)
sim/tb_sys_tx_rx_e_d.v
+215
View File
@@ -0,0 +1,215 @@
`timescale 1ns / 100ps
module tb_sys_tx_rx_e_d ();
reg ad9361_rx_clk = 0; // 50MHz 20ns
reg clk_crystal = 0; // 40MHz 25ns
always #(10) ad9361_rx_clk = ~ad9361_rx_clk;
always #(12.5) clk_crystal = ~clk_crystal;
// ******** Wire & Reg ********
// power on clock domain
wire clk_poweron;
(*max_fanout = 256 *)
wire rst_sys;
wire poweron_locked;
// ad9361 clock domain
wire locked;
wire clk_1x;
wire clk_2x;
wire clk_4x;
// enc signal
wire enc_fifo_rd_en;
wire [31:0] enc_fifo_dout_map;
wire enc_fifo_empty;
// tx bus
wire clk_tx_data_src;
reg [31:0] tx_data_src_count;
reg [31:0] tx_data_src_tdata;
wire tx_data_src_tready;
reg tx_data_src_tvalid;
// tx signal
wire tx_test_flag;
// baseband signal
wire [11:0] ad9361_rx_data_i;
wire [11:0] ad9361_rx_data_q;
wire ad9361_rx_frame_i;
wire ad9361_rx_frame_q;
wire [11:0] ad9361_tx_data_i;
wire [11:0] ad9361_tx_data_q;
wire [ 2:0] speed_mode;
// phy control signal
wire phy_rst_vio;
wire phy_rst_ps;
wire phy_rst;
wire phy_tx_test_flag_vio;
wire phy_tx_test_flag;
// ***** simulation *****
reg [ 3:0] cnt_delay = 0;
reg [31:0] idx = 0;
reg send_start = 0;
reg [31:0] mem [0:31]; // 1024 bit
initial begin
$readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/enc_src.txt", mem);
end
always @(posedge clk_1x) send_start <= (cnt_delay >= 4'hA) && (cnt_delay <= 4'hE);
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
// ******** Logic Block ********
// ************************ ************************
// ************************ simulation ************************
// ************************ ************************
always @(posedge clk_poweron) begin
if (rst_sys) begin
cnt_delay <= 0;
end
else if (cnt_delay < 4'hF) begin
cnt_delay <= cnt_delay + 1;
end
end
always @(posedge clk_poweron) begin
if (rst_sys) begin
idx <= 0;
tx_data_src_tvalid <= 0;
tx_data_src_tdata <= 0;
tx_data_src_count <= 32;
end
else if (cnt_delay == 4'hF) begin
tx_data_src_tvalid <= 1;
tx_data_src_tdata <= mem[idx];
if (tx_data_src_tready) begin
if (idx < 31) begin
idx <= idx + 1;
tx_data_src_count <= tx_data_src_count - 1;
end
else begin
idx <= 0;
tx_data_src_count <= 32;
end
end
end
end
// ************************************************************
// ************************ simulation ************************
// ************************************************************
// ******** Inst ********
clk_wiz_poweron u_clk_wiz_poweron (
// Clock out ports
.clk_poweron(clk_poweron), // output clk_poweron
// Status and control signals
.locked (poweron_locked), // output locked
// Clock in ports
.clk_crystal(clk_crystal) // input clk_crystal
);
// clock domain - ad9361 rx & tx
clk_wiz_baseband u_clk_wiz_baseband (
// Clock out ports
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
// Status and control signals
.locked (locked), // output locked
// Clock in ports
.clk_src(ad9361_rx_clk) // input clk_src
);
// ************************************************************
// *************************** TX *****************************
// ************************************************************
enc_control u_enc_control (
.clk (clk_poweron),
.rst (rst_sys),
.s_axis_fifo_tvalid (tx_data_src_tvalid),
.s_axis_fifo_tready (tx_data_src_tready),
.s_axis_fifo_tdata (tx_data_src_tdata),
.data_src_count (tx_data_src_count),
.fifo_enc_out_rd_clk (clk_1x),
.fifo_enc_out_rd_en (enc_fifo_rd_en),
.fifo_enc_out_dout_map(enc_fifo_dout_map),
.fifo_enc_out_empty (enc_fifo_empty)
);
Transmitter #(
.AGC_HEADER_LEN(2500)
) u_Transmitter (
.clk (clk_1x),
.rst (rst_sys),
.speed_mode (2),
.send_data_ready (send_data_ready),
.send_start (send_start),
.send_over (send_over),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
.tx_data_src_tready(enc_fifo_rd_en),
.tx_data_src_tvalid(~enc_fifo_empty),
.hopping_freq (),
.ad9361_tx_data_i (ad9361_tx_data_i),
.ad9361_tx_data_q (ad9361_tx_data_q),
.test (0),
.hop_wait (100)
);
// ************************************************************
// *************************** RX *****************************
// ************************************************************
RecvTop u_RecvTop (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys),
.rst2 (rst_sys),
.dini (ad9361_tx_data_i),
.dinq (ad9361_tx_data_q),
.ad9361_ctrl_in (),
.vio_tsync_inter16(1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd)
);
endmodule