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commit 9a1f168184
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2020/10/04 13:29:02
+// Design Name:
+// Module Name: shift_reg
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module shift_reg #(
+    parameter DATA_WIDTH = 8,
+    parameter DEPTH = 4
+) (
+                           input                   clk,
+    (* max_fanout = 256 *) input                   rst,
+                           input                   we,
+                           input  [DATA_WIDTH-1:0] din,
+                           output [DATA_WIDTH-1:0] dout
+);
+    // generate
+    //     if (DEPTH > 1) begin
+    //         reg [DEPTH-1:0] shift_register[DATA_WIDTH-1:0];
+    //         genvar shift_bit_cnt;
+    //         for (shift_bit_cnt = 0; shift_bit_cnt < DATA_WIDTH; shift_bit_cnt = shift_bit_cnt + 1) begin : shift_each_bit
+    //             always @(posedge clk) begin
+    //                 if (we) shift_register[shift_bit_cnt] <= {din[shift_bit_cnt], shift_register[shift_bit_cnt][DEPTH-1:1]};
+    //                 else shift_register[shift_bit_cnt] <= shift_bit_cnt[shift_bit_cnt];
+    //             end
+    //         end
+    //         genvar output_bit_cnt;
+    //         for (output_bit_cnt = 0; output_bit_cnt < DATA_WIDTH; output_bit_cnt = output_bit_cnt + 1) begin : output_each_bit
+    //             assign dout[output_bit_cnt] = shift_register[output_bit_cnt][0];
+    //         end
+    //     end
+    //     else  // just a reg
+    //     begin
+    //         reg [DATA_WIDTH-1:0] shift_register;
+    //         always @(posedge clk) begin
+    //             if (we) shift_register <= din;
+    //             else shift_register <= shift_register;
+    //         end
+    //         assign dout = shift_register;
+    //     end
+    // endgenerate
+
+
+    generate
+        if (DEPTH > 1) begin
+            reg [DATA_WIDTH-1:0] shift_register[DEPTH-1:0];
+            genvar shift_reg_cnt;
+            for (shift_reg_cnt = 0; shift_reg_cnt < DEPTH; shift_reg_cnt = shift_reg_cnt + 1) begin : shift_each_reg
+                always @(posedge clk) begin
+                    if (rst) begin
+                        shift_register[shift_reg_cnt][DATA_WIDTH-1:0] <= 'd0;
+                    end
+                    else if (we) begin
+                        if (shift_reg_cnt == 0) begin
+                            shift_register[shift_reg_cnt] <= din;
+                        end
+                        else begin
+                            shift_register[shift_reg_cnt] <= shift_register[shift_reg_cnt-1];
+                        end
+                    end
+                    else shift_register[shift_reg_cnt] <= shift_register[shift_reg_cnt];
+                end
+            end
+            assign dout = shift_register[DEPTH-1];
+        end
+        else  // just a reg
+        begin
+            reg [DATA_WIDTH-1:0] shift_register;
+            always @(posedge clk) begin
+                if (we) shift_register <= din;
+                else shift_register <= shift_register;
+            end
+            assign dout = shift_register;
+        end
+    endgenerate
+
+endmodule