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ZoroGH
2024-07-19 14:09:20 +08:00
commit 9a1f168184
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sim/TB_sys.v
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`timescale 10ns / 10ns
module TB_sys ();
reg clk;
reg req;
always #1 clk <= ~clk;
// ******** Wire & Reg ********
// power on clock domain
wire clk_poweron;
(*max_fanout = 256 *)
wire rst_sys;
wire poweron_locked;
// ad9361 clock domain
wire locked;
wire clk_1x;
wire clk_2x;
wire clk_4x;
// emio
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
// enc signal
wire enc_fifo_rd_en;
wire [31:0] enc_fifo_dout_map;
wire enc_fifo_empty;
// tx bus
wire clk_tx_data_src;
wire [31:0] tx_data_src_count;
wire [15:0] tx_data_src_tdata;
wire tx_data_src_tready;
wire tx_data_src_tvalid;
// baseband signal
wire [11:0] ad9361_rx_data_i;
wire [11:0] ad9361_rx_data_q;
wire ad9361_rx_frame_i;
wire ad9361_rx_frame_q;
wire [11:0] ad9361_tx_data_i;
wire [11:0] ad9361_tx_data_q;
// test
wire flag_transmitter_test;
reg pl2ps_intr2;
reg [31:0] cnt;
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
// ad9361 control
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
// ******** Logic Block ********
always @(posedge clk) begin
if (rst_sys) begin
pl2ps_intr2 <= 0;
cnt <= 0;
end
else begin
cnt <= cnt + 1;
if (cnt == 1000 || cnt == 1500 || cnt == 2000) begin
pl2ps_intr2 <= 1;
end
else begin
pl2ps_intr2 <= 0;
end
end
end
// ******** Inst ********
clk_wiz_poweron u_clk_wiz_poweron (
// Clock out ports
.clk_poweron(clk_poweron), // output clk_poweron
// Status and control signals
.locked (poweron_locked), // output locked
// Clock in ports
.clk_crystal(clk_crystal) // input clk_crystal
);
// clock domain - ad9361 rx & tx
clk_wiz_baseband u_clk_wiz_baseband (
// Clock out ports
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
// Status and control signals
.locked (locked), // output locked
// Clock in ports
.clk_src(ad9361_rx_clk) // input clk_src
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl2ps_intr2 (pl2ps_intr2),
.pl2ps_intr3 (pl2ps_intr3),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready(tx_data_src_tready),
.tx_data_src_tvalid(tx_data_src_tvalid),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
// ---- PHY layer logic start
// enc_control u_enc_control (
// .clk (clk_poweron),
// .rst (rst_sys),
// .s_axis_fifo_tvalid(tx_data_src_tvalid),
// .s_axis_fifo_tready(tx_data_src_tready),
// .s_axis_fifo_tdata (tx_data_src_tdata),
// .data_src_count (tx_data_src_count),
// .fifo_rd_clk (clk_1x),
// .fifo_rd_en (enc_fifo_rd_en),
// .fifo_dout_map (enc_fifo_dout_map),
// .fifo_empty (enc_fifo_empty)
// );
// Transmitter u_Transmitter (
// .clk (clk_1x),
// .rst (rst_sys),
// .speed_mode (0),
// .send_data_ready (send_data_ready),
// .send_start (send_start),
// .send_over (send_over),
// .clk_data_src (clk_data_src),
// .tx_data_src_tdata (enc_fifo_dout_map),
// .tx_data_src_tready(enc_fifo_rd_en),
// .tx_data_src_tvalid(~enc_fifo_empty),
// .hopping_freq (),
// .ad9361_tx_data_i (ad9361_tx_data_i),
// .ad9361_tx_data_q (ad9361_tx_data_q),
// .test (flag_transmitter_test),
// .hop_wait (2000)
// );
endmodule
sim/tb_Receiver.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/04/15 20:17:12
// Design Name:
// Module Name: tb_Receiver
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_Receiver ();
reg clk;
reg clk_2x;
reg clk_4x;
reg rst;
localparam CLK_PERIOD = 20_0;
always #(10) clk = ~clk;
always #(5) clk_2x = ~clk_2x;
always #(2.5) clk_4x = ~clk_4x;
// * start
reg [11:0] ad9361_rx_data_i;
reg [11:0] ad9361_rx_data_q;
reg flag;
reg [11:0] mem_i [10000:0];
reg [11:0] mem_q [10000:0];
initial begin
clk <= 1'b0;
clk_2x <= 1'b0;
clk_4x <= 1'b0;
$readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_i_testbench.txt", mem_i);
$readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_q_testbench.txt", mem_q);
rst <= 1'b0;
flag <= 0;
#(CLK_PERIOD * 50) rst <= 1;
#(CLK_PERIOD * 10) rst <= 0;
#(CLK_PERIOD * 100) flag <= 1;
end
Receiver u_Receiver (
.clk (clk),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst),
.speed_mode (3'd0),
.ad9361_rx_data_i(ad9361_rx_data_i),
.ad9361_rx_data_q(ad9361_rx_data_q)
);
reg [15:0] index = 16'd0;
always @(posedge clk) begin
if (rst) begin
index <= 'd0;
ad9361_rx_data_i <= 'd0;
ad9361_rx_data_q <= 'd0;
end
else if (flag) begin
ad9361_rx_data_i <= mem_i[index];
ad9361_rx_data_q <= mem_q[index];
index <= index + 16'd1;
end
end
endmodule
sim/tb_Transmitter.v
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`timescale 1ns / 1ns
module tb_Transmitter ();
reg clk = 1;
reg clk_tx = 1;
reg rst = 1;
always #1 clk <= ~clk;
always #2 clk_tx <= ~clk_tx;
reg intr = 0;
reg test=0;
initial begin
#100 rst <= 0;
#1000 test <=1;
#1000 test <=0;
#1000 test <=1;
#1000 test <=1;
end
Transmitter #(
.AGC_HEADER_LEN(200),
.FRAME_HEADER_LEN(512),
.BLOCK_NUM(3),
.PHASE1_LEN(2112),
.PREFIX_LEN(8),
.CHU_SEQ_LEN(128),
.GAP_LEN(128)
) u_Transmitter (
.clk (clk_tx),
.rst (rst),
.speed_mode (0),
.send_data_ready (),
.send_start (),
.send_over (),
.clk_data_src (),
.tx_data_src_tdata (),
.tx_data_src_tready(),
.tx_data_src_tvalid(),
.hopping_freq (),
.ad9361_tx_data_i (),
.ad9361_tx_data_q (),
.test (test),
.hop_wait (2000)
);
endmodule
sim/tb_add_prefix.v
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`timescale 1ns / 1ns
module tb_add_prefix ();
reg clk = 0;
reg rst = 0;
always #1 clk <= ~clk;
reg start;
wire ready;
reg [31:0] data_in = 0;
wire [31:0] data_out;
wire data_out_valid;
initial begin
#20 rst <= 1'b1;
#20 rst <= 0;
start <= 1'b0;
#100 start <= 1'b1;
#2 start <= 1'b0;
end
add_prefix #(
.WIDTH (32),
.DATA_LEN (256),
.PREFIX_LEN(8)
) u_add_prefix (
.clk (clk),
.start (start),
.ready (ready),
.data_in (data_in),
.data_in_ready (data_in_ready),
.data_out (data_out),
.data_out_valid(data_out_valid)
);
always @(posedge clk) begin
if (rst == 1'b1) begin
data_in <= 0;
end
else if (start || data_in > 0) begin
data_in <= data_in + 32'd1;
end
else begin
data_in <= 0;
end
end
endmodule
sim/tb_enc_control.v
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`timescale 1ns / 1ns
module tb_enc_control ();
reg clk = 1;
reg rst = 1;
always #1 clk <= ~clk;
reg intr = 0;
reg s_axis_fifo_tvalid = 1'b0;
wire s_axis_fifo_tready;
reg [31:0] s_axis_fifo_tdata;
reg [31:0] data_src_count;
wire enc_dout_intr;
wire enc_dout_valid;
wire [15:0] enc_dout;
reg fifo_enc_out_rd_en;
wire [31:0] fifo_enc_out_dout_map;
wire fifo_enc_out_empty;
reg [ 1:0] cnt_div = 0;
wire clk_div;
assign enc_dout_valid = ~fifo_enc_out_empty;
assign clk_div = cnt_div[1];
initial begin
#100 rst <= 1'b0;
end
reg [31:0] cnt_start;
always @(posedge clk) begin
if (rst) begin
cnt_start <= 0;
s_axis_fifo_tvalid <= 0;
end
else if (cnt_start < 70) begin
cnt_start <= cnt_start + 1;
s_axis_fifo_tvalid <= 0;
end
else if (cnt_start < 1500) begin
cnt_start <= cnt_start + 1;
s_axis_fifo_tvalid <= 1;
end
else if (cnt_start < 25000) begin
cnt_start <= cnt_start + 1;
s_axis_fifo_tvalid <= 0;
end
else if (cnt_start < 50000) begin
cnt_start <= cnt_start + 1;
s_axis_fifo_tvalid <= 1;
end
else begin
s_axis_fifo_tvalid <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
data_src_count <= 0;
s_axis_fifo_tdata <= $random();
end
else begin
if (s_axis_fifo_tready) begin
s_axis_fifo_tdata <= $random();
end
data_src_count <= 1000;
end
end
enc_control u_enc_control (
.clk (clk),
.rst (rst),
.s_axis_fifo_tvalid (s_axis_fifo_tvalid),
.s_axis_fifo_tready (s_axis_fifo_tready),
.s_axis_fifo_tdata (s_axis_fifo_tdata),
.data_src_count (data_src_count),
.fifo_enc_out_rd_clk (clk_div),
.fifo_enc_out_rd_en (fifo_enc_out_rd_en),
.fifo_enc_out_dout_map(fifo_enc_out_dout_map),
.fifo_enc_out_empty (fifo_enc_out_empty)
);
reg [1:0] cnt_rd;
always @(posedge clk_div) begin
if (rst) begin
cnt_rd <= 0;
end
else begin
if (enc_dout_valid) cnt_rd <= cnt_rd + 1;
end
end
always @(posedge clk_div) begin
if (cnt_rd == 2'b11) fifo_enc_out_rd_en <= 1;
else fifo_enc_out_rd_en <= 0;
end
always @(posedge clk) begin
cnt_div <= cnt_div + 1;
end
endmodule
sim/tb_led.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/10 18:06:49
// Design Name:
// Module Name: tb_led
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_led(
);
endmodule
sim/tb_tdma.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/04/26 17:05:11
// Design Name:
// Module Name: tb_tdma
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_tdma ();
reg clk = 1;
reg clk_tx = 1;
reg rst = 1;
always #1 clk <= ~clk;
initial begin
#1000 rst <= 1'b0;
end
wire flag_frame_sync_m;
reg flag_frame_sync_s = 0;
wire intr_2ps_m;
wire intr_2ps_s;
wire tic_hop_m;
wire tic_hop_s;
wire tx_start_m;
wire tx_start_s;
assign flag_frame_sync_m = 1'b0;
tdma #(
.SLOT_LEN (1250000),
.TIC_TO_PS_LEN (1200000),
.TIC_FRAME_SYNC(42272)
) u_tdma_master (
.clk (clk),
.rst (rst),
.flag_is_master (1'b1),
.flag_frame_sync(flag_frame_sync_m),
.intr_2ps (intr_2ps_m),
// .tic_hop (tic_hop_m),
.tx_start (tx_start_m)
);
tdma #(
.SLOT_LEN (20000),
.TIC_TO_PS_LEN (18000),
.TIC_FRAME_SYNC(2000)
) u_tdma_slave (
.clk (clk),
.rst (rst),
.flag_is_master (1'b0),
.flag_frame_sync(flag_frame_sync_s),
.intr_2ps (intr_2ps_s),
// .tic_hop (tic_hop_s),
.tx_start (tx_start_s)
);
initial begin
#12000 flag_frame_sync_s <= 1'b1;
#3 flag_frame_sync_s <= 1'b0;
end
endmodule
sim/tb_tx_with_enc.v
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`timescale 1ns / 1ns
module tb_tx_with_enc ();
reg clk_crystal = 0; // 25MHz
reg ad9361_rx_clk = 0; // 50MHz
always #2 clk_crystal <= ~clk_crystal;
always #1 ad9361_rx_clk <= ~ad9361_rx_clk;
// ******** Wire & Reg ********
// power on clock domain
wire clk_poweron;
(*max_fanout = 256 *)
wire rst_sys;
wire poweron_locked;
// ad9361 clock domain
wire locked;
wire clk_1x;
wire clk_2x;
wire clk_4x;
// emio
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
// enc signal
wire enc_fifo_rd_en;
wire [31:0] enc_fifo_dout_map;
wire enc_fifo_empty;
// tx bus
wire clk_tx_data_src;
wire [31:0] tx_data_src_count;
wire [31:0] tx_data_src_tdata;
wire tx_data_src_tready;
wire tx_data_src_tvalid;
// baseband signal
wire [11:0] ad9361_rx_data_i;
wire [11:0] ad9361_rx_data_q;
wire ad9361_rx_frame_i;
wire ad9361_rx_frame_q;
wire [11:0] ad9361_tx_data_i;
wire [11:0] ad9361_tx_data_q;
// test
wire tx_test_flag_ps;
wire tx_test_flag;
wire frame_sync_pulse;
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
// ad9361 control
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
// ******** Logic Block ********
// ******** Inst ********
clk_wiz_poweron u_clk_wiz_poweron (
// Clock out ports
.clk_poweron(clk_poweron), // output clk_poweron
// Status and control signals
.locked (poweron_locked), // output locked
// Clock in ports
.clk_crystal(clk_crystal) // input clk_crystal
);
// clock domain - ad9361 rx & tx
clk_wiz_baseband u_clk_wiz_baseband (
// Clock out ports
.clk_1x (clk_1x), // output clk_1x
.clk_2x (clk_2x), // output clk_2x
.clk_4x (clk_4x), // output clk_4x
// Status and control signals
.locked (locked), // output locked
// Clock in ports
.clk_src(ad9361_rx_clk) // input clk_src
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl2ps_intr2 (intr_2ps),
.pl2ps_intr3 (pl2ps_intr3),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready(tx_data_src_tready),
.tx_data_src_tvalid(tx_data_src_tvalid),
//tx flag
.tx_test_flag (tx_test_flag_ps),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
// ---- PHY layer logic start
enc_control u_enc_control (
.clk (clk_poweron),
.rst (rst_sys),
.s_axis_fifo_tvalid (tx_data_src_tvalid),
.s_axis_fifo_tready (tx_data_src_tready),
.s_axis_fifo_tdata (tx_data_src_tdata),
.data_src_count (tx_data_src_count),
.fifo_enc_out_rd_clk (clk_1x),
.fifo_enc_out_rd_en (enc_fifo_rd_en),
.fifo_enc_out_dout_map(enc_fifo_dout_map),
.fifo_enc_out_empty (enc_fifo_empty)
);
tdma #(
.SLOT_LEN (1250000), // 50MHz--> 25ms
.TIC_TO_PS_LEN (1200000),
.TIC_FRAME_SYNC(42272)
) u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (1'b0),
.flag_frame_sync(frame_sync_pulse),
.intr_2ps (intr_2ps),
.tx_start (tx_start)
);
Transmitter u_Transmitter (
.clk (clk_1x),
.rst (rst_sys),
.speed_mode (0),
.send_data_ready (send_data_ready),
.send_start (tx_start),
.send_over (send_over),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
.tx_data_src_tready(enc_fifo_rd_en),
.tx_data_src_tvalid(~enc_fifo_empty),
.hopping_freq (),
.ad9361_tx_data_i (ad9361_tx_data_i),
.ad9361_tx_data_q (ad9361_tx_data_q),
.test (tx_test_flag),
.hop_wait (2000)
);
endmodule
sim/tb_width_convert.v
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`timescale 1ns / 1ps
module tb_width_convert ();
reg clk = 1;
reg rst = 1;
always #(2) clk <= ~clk;
initial begin
#10 rst <= 1'b0;
end
reg [31:0] data_in;
reg data_in_valid;
wire data_in_ready;
wire data_out_valid;
wire [ 0:0] data_out;
width_convert #(
.INPUT_WIDTH (32),
.OUTPUT_WIDTH(1)
) u_width_convert (
.clk (clk),
.rst (rst),
.data_in_valid (data_in_valid),
.data_in_ready (data_in_ready),
.data_in (data_in),
.data_out_valid(data_out_valid),
.data_out (data_out)
);
reg [5:0] cnt_startup;
reg [3:0] cnt_data_in;
always @(posedge clk) begin
if (rst) begin
cnt_startup <= 0;
end
else if (cnt_startup < 6'b111111) begin
cnt_startup <= cnt_startup + 1;
end
end
reg [5:0] cnt_in;
localparam CNT_IN_MAX = 32;
always @(posedge clk) begin
if (rst) begin
cnt_in <= 0;
end
else if (cnt_in == CNT_IN_MAX) begin
cnt_in <= 0;
end
else begin
cnt_in <= cnt_in + 1;
end
end
always @(posedge clk) begin
if (rst) begin
data_in <= $random();
cnt_data_in <= 0;
end
else if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX && cnt_data_in < 5) begin
data_in <= $random();
cnt_data_in <= cnt_data_in + 1;
end
end
always @(posedge clk) begin
// if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX) begin
// data_in_valid <= 1;
// end
// else begin
// data_in_valid <= 0;
// end
if (rst) begin
data_in_valid <= 0;
end
else if (cnt_startup == 6'b111_111 && cnt_data_in < 5) begin
data_in_valid <= 1;
end
else begin
data_in_valid <= 0;
end
end
endmodule