Init repo

sim/tb_add_prefix.v

@@ -0,0 +1,55 @@
+`timescale 1ns / 1ns
+
+module tb_add_prefix ();
+
+
+    reg clk = 0;
+    reg rst = 0;
+
+
+    always #1 clk <= ~clk;
+
+    reg         start;
+    wire        ready;
+    reg  [31:0] data_in = 0;
+    wire [31:0] data_out;
+    wire        data_out_valid;
+
+    initial begin
+        #20 rst <= 1'b1;
+        #20 rst <= 0;
+        start <= 1'b0;
+        #100 start <= 1'b1;
+        #2 start <= 1'b0;
+    end
+
+    add_prefix #(
+        .WIDTH     (32),
+        .DATA_LEN  (256),
+        .PREFIX_LEN(8)
+    ) u_add_prefix (
+        .clk           (clk),
+        .start         (start),
+        .ready         (ready),
+        .data_in       (data_in),
+        .data_in_ready (data_in_ready),
+        .data_out      (data_out),
+        .data_out_valid(data_out_valid)
+    );
+
+
+    always @(posedge clk) begin
+        if (rst == 1'b1) begin
+            data_in <= 0;
+        end
+        else if (start || data_in > 0) begin
+            data_in <= data_in + 32'd1;
+        end
+        else begin
+            data_in <= 0;
+        end
+    end
+
+
+
+endmodule