Init repo

sim/tb_enc_control.v

@@ -0,0 +1,110 @@
+`timescale 1ns / 1ns
+
+
+module tb_enc_control ();
+
+
+    reg clk = 1;
+    reg rst = 1;
+
+    always #1 clk <= ~clk;
+
+    reg         intr = 0;
+
+
+    reg         s_axis_fifo_tvalid = 1'b0;
+    wire        s_axis_fifo_tready;
+    reg  [31:0] s_axis_fifo_tdata;
+    reg  [31:0] data_src_count;
+    wire        enc_dout_intr;
+    wire        enc_dout_valid;
+    wire [15:0] enc_dout;
+
+    reg         fifo_enc_out_rd_en;
+    wire [31:0] fifo_enc_out_dout_map;
+    wire        fifo_enc_out_empty;
+    reg  [ 1:0] cnt_div = 0;
+    wire        clk_div;
+
+    assign enc_dout_valid = ~fifo_enc_out_empty;
+    assign clk_div        = cnt_div[1];
+
+
+    initial begin
+        #100 rst <= 1'b0;
+    end
+
+    reg [31:0] cnt_start;
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_start          <= 0;
+            s_axis_fifo_tvalid <= 0;
+        end
+        else if (cnt_start < 70) begin
+            cnt_start          <= cnt_start + 1;
+            s_axis_fifo_tvalid <= 0;
+        end
+        else if (cnt_start < 1500) begin
+            cnt_start          <= cnt_start + 1;
+            s_axis_fifo_tvalid <= 1;
+        end
+        else if (cnt_start < 25000) begin
+            cnt_start          <= cnt_start + 1;
+            s_axis_fifo_tvalid <= 0;
+        end
+        else if (cnt_start < 50000) begin
+            cnt_start          <= cnt_start + 1;
+            s_axis_fifo_tvalid <= 1;
+        end
+        else begin
+            s_axis_fifo_tvalid <= 0;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            data_src_count    <= 0;
+            s_axis_fifo_tdata <= $random();
+        end
+        else begin
+            if (s_axis_fifo_tready) begin
+                s_axis_fifo_tdata <= $random();
+            end
+            data_src_count <= 1000;
+        end
+    end
+
+    enc_control u_enc_control (
+        .clk                  (clk),
+        .rst                  (rst),
+        .s_axis_fifo_tvalid   (s_axis_fifo_tvalid),
+        .s_axis_fifo_tready   (s_axis_fifo_tready),
+        .s_axis_fifo_tdata    (s_axis_fifo_tdata),
+        .data_src_count       (data_src_count),
+        .fifo_enc_out_rd_clk  (clk_div),
+        .fifo_enc_out_rd_en   (fifo_enc_out_rd_en),
+        .fifo_enc_out_dout_map(fifo_enc_out_dout_map),
+        .fifo_enc_out_empty   (fifo_enc_out_empty)
+    );
+
+    reg [1:0] cnt_rd;
+    always @(posedge clk_div) begin
+        if (rst) begin
+            cnt_rd <= 0;
+        end
+        else begin
+            if (enc_dout_valid) cnt_rd <= cnt_rd + 1;
+        end
+    end
+
+    always @(posedge clk_div) begin
+        if (cnt_rd == 2'b11) fifo_enc_out_rd_en <= 1;
+        else fifo_enc_out_rd_en <= 0;
+    end
+
+    always @(posedge clk) begin
+        cnt_div <= cnt_div + 1;
+    end
+
+
+endmodule