Init repo
This commit is contained in:
@@ -0,0 +1,3 @@
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adi_library
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c/**
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ip
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@@ -0,0 +1,941 @@
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################################################################
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# This is a generated script based on design: MM7020_BD
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2023.2
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
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} else {
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source MM7020_BD_script.tcl
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# The design that will be created by this Tcl script contains the following
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# module references:
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# axi_lite_control, ad9361_spi_interface
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# Please add the sources of those modules before sourcing this Tcl script.
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z020clg400-2
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name MM7020_BD
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_dma:7.1\
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xilinx.com:ip:smartconnect:1.0\
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xilinx.com:ip:axis_data_fifo:2.0\
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xilinx.com:ip:processing_system7:5.5\
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xilinx.com:ip:proc_sys_reset:5.0\
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xilinx.com:ip:xlconcat:2.1\
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xilinx.com:ip:vio:3.0\
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xilinx.com:ip:mdm:3.2\
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xilinx.com:ip:axis_dwidth_converter:1.1\
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analog.com:user:spi_engine_execution:1.0\
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analog.com:user:axi_spi_engine:1.0\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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##################################################################
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# CHECK Modules
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##################################################################
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set bCheckModules 1
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if { $bCheckModules == 1 } {
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set list_check_mods "\
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axi_lite_control\
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ad9361_spi_interface\
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"
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set list_mods_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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lappend list_mods_missing $mod_vlnv
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}
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Hierarchical cell: ad9361_driver
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proc create_hier_cell_ad9361_driver { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ad9361_driver() - Empty argument(s)!"}
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return
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}
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||||
# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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||||
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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||||
return
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||||
}
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||||
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||||
# Save current instance; Restore later
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||||
set oldCurInst [current_bd_instance .]
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||||
# Set parent object as current
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||||
current_bd_instance $parentObj
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||||
# Create cell and set as current instance
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||||
set hier_obj [create_bd_cell -type hier $nameHier]
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current_bd_instance $hier_obj
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||||
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||||
# Create interface pins
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||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
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||||
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||||
# Create pins
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||||
create_bd_pin -dir I -type clk clk_sys
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||||
create_bd_pin -dir I -type rst s_axi_aresetn
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create_bd_pin -dir I ad9361_spi_miso
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||||
create_bd_pin -dir O ad9361_spi_csn
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||||
create_bd_pin -dir O -type clk ad9361_spi_clk
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||||
create_bd_pin -dir O ad9361_spi_mosi
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||||
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# Create instance: spi_engine_execution_0, and set properties
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set spi_engine_execution_0 [ create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 spi_engine_execution_0 ]
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set_property CONFIG.NUM_OF_CS {2} $spi_engine_execution_0
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||||
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||||
# Create instance: axi_spi_engine_0, and set properties
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set axi_spi_engine_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi_spi_engine_0 ]
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||||
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# Create instance: ad9361_spi_interface, and set properties
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||||
set block_name ad9361_spi_interface
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set block_cell_name ad9361_spi_interface
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||||
if { [catch {set ad9361_spi_interface [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $ad9361_spi_interface eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M01_AXI [get_bd_intf_pins s_axi] [get_bd_intf_pins axi_spi_engine_0/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_spi_engine_0_spi_engine_ctrl [get_bd_intf_pins axi_spi_engine_0/spi_engine_ctrl] [get_bd_intf_pins spi_engine_execution_0/ctrl]
|
||||
connect_bd_intf_net -intf_net axi_spi_engine_spi [get_bd_intf_pins ad9361_spi_interface/spi] [get_bd_intf_pins spi_engine_execution_0/spi]
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||||
|
||||
# Create port connections
|
||||
connect_bd_net -net Net1 [get_bd_pins clk_sys] [get_bd_pins axi_spi_engine_0/s_axi_aclk] [get_bd_pins axi_spi_engine_0/spi_clk] [get_bd_pins spi_engine_execution_0/clk]
|
||||
connect_bd_net -net ad9361_spi_interface_1_ad9361_spi_clk [get_bd_pins ad9361_spi_interface/ad9361_spi_clk] [get_bd_pins ad9361_spi_clk]
|
||||
connect_bd_net -net ad9361_spi_interface_1_ad9361_spi_csn [get_bd_pins ad9361_spi_interface/ad9361_spi_csn] [get_bd_pins ad9361_spi_csn]
|
||||
connect_bd_net -net ad9361_spi_interface_1_ad9361_spi_mosi [get_bd_pins ad9361_spi_interface/ad9361_spi_mosi] [get_bd_pins ad9361_spi_mosi]
|
||||
connect_bd_net -net ad9361_spi_miso_0_1 [get_bd_pins ad9361_spi_miso] [get_bd_pins ad9361_spi_interface/ad9361_spi_miso]
|
||||
connect_bd_net -net axi_spi_engine_0_spi_resetn [get_bd_pins axi_spi_engine_0/spi_resetn] [get_bd_pins spi_engine_execution_0/resetn]
|
||||
connect_bd_net -net axi_spi_engine_active_0 [get_bd_pins spi_engine_execution_0/active] [get_bd_pins ad9361_spi_interface/spi_active]
|
||||
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_spi_engine_0/s_axi_aresetn]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr ]
|
||||
|
||||
set fixed_io [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io ]
|
||||
|
||||
set tx_data_src [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data_src ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $tx_data_src
|
||||
|
||||
|
||||
# Create ports
|
||||
set ad9361_spi_clk [ create_bd_port -dir O -type clk ad9361_spi_clk ]
|
||||
set ad9361_spi_csn [ create_bd_port -dir O ad9361_spi_csn ]
|
||||
set ad9361_spi_miso [ create_bd_port -dir I ad9361_spi_miso ]
|
||||
set ad9361_spi_mosi [ create_bd_port -dir O ad9361_spi_mosi ]
|
||||
set uart_rx [ create_bd_port -dir I uart_rx ]
|
||||
set uart_tx [ create_bd_port -dir O uart_tx ]
|
||||
set gpio_i [ create_bd_port -dir I -from 31 -to 0 gpio_i ]
|
||||
set gpio_o [ create_bd_port -dir O -from 31 -to 0 gpio_o ]
|
||||
set gpio_t [ create_bd_port -dir O -from 31 -to 0 gpio_t ]
|
||||
set tx_data_src_count [ create_bd_port -dir O -from 31 -to 0 tx_data_src_count ]
|
||||
set pl2ps_intr2 [ create_bd_port -dir I -from 0 -to 0 pl2ps_intr2 ]
|
||||
set pl2ps_intr3 [ create_bd_port -dir I -from 0 -to 0 pl2ps_intr3 ]
|
||||
set clk_ps [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_ps ]
|
||||
set rst_ps [ create_bd_port -dir I -type rst rst_ps ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_HIGH} \
|
||||
] $rst_ps
|
||||
set tx_test_flag [ create_bd_port -dir O tx_test_flag ]
|
||||
|
||||
# Create instance: axi_dma_0, and set properties
|
||||
set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.c_include_mm2s {1} \
|
||||
CONFIG.c_include_mm2s_dre {0} \
|
||||
CONFIG.c_include_s2mm {0} \
|
||||
CONFIG.c_include_sg {0} \
|
||||
CONFIG.c_micro_dma {0} \
|
||||
CONFIG.c_mm2s_burst_size {256} \
|
||||
CONFIG.c_sg_length_width {17} \
|
||||
] $axi_dma_0
|
||||
|
||||
|
||||
# Create instance: axi_interconnect, and set properties
|
||||
set axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect ]
|
||||
set_property CONFIG.NUM_MI {4} $axi_interconnect
|
||||
|
||||
|
||||
# Create instance: axi_smc, and set properties
|
||||
set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
|
||||
set_property CONFIG.NUM_SI {1} $axi_smc
|
||||
|
||||
|
||||
# Create instance: axis_data_src_fifo, and set properties
|
||||
set axis_data_src_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_src_fifo ]
|
||||
set_property -dict [list \
|
||||
CONFIG.FIFO_DEPTH {16384} \
|
||||
CONFIG.HAS_RD_DATA_COUNT {1} \
|
||||
CONFIG.IS_ACLK_ASYNC {0} \
|
||||
] $axis_data_src_fifo
|
||||
|
||||
|
||||
# Create instance: ps, and set properties
|
||||
set ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {350.000000} \
|
||||
CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
|
||||
CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
|
||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.062893} \
|
||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
|
||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
|
||||
CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
|
||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {58.333332} \
|
||||
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
|
||||
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {350} \
|
||||
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
|
||||
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
|
||||
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_CLK0_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK1_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
||||
CONFIG.PCW_CORE0_FIQ_INTR {0} \
|
||||
CONFIG.PCW_CORE0_IRQ_INTR {0} \
|
||||
CONFIG.PCW_CORE1_FIQ_INTR {0} \
|
||||
CONFIG.PCW_CORE1_IRQ_INTR {0} \
|
||||
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {767} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
|
||||
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
|
||||
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
|
||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
|
||||
CONFIG.PCW_DM_WIDTH {4} \
|
||||
CONFIG.PCW_DQS_WIDTH {4} \
|
||||
CONFIG.PCW_DQ_WIDTH {32} \
|
||||
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
|
||||
CONFIG.PCW_EN_4K_TIMER {0} \
|
||||
CONFIG.PCW_EN_CAN0 {0} \
|
||||
CONFIG.PCW_EN_CAN1 {0} \
|
||||
CONFIG.PCW_EN_CLK0_PORT {0} \
|
||||
CONFIG.PCW_EN_CLK1_PORT {0} \
|
||||
CONFIG.PCW_EN_CLK2_PORT {0} \
|
||||
CONFIG.PCW_EN_CLK3_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
|
||||
CONFIG.PCW_EN_DDR {1} \
|
||||
CONFIG.PCW_EN_EMIO_CAN0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_CAN1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_ENET0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_ENET1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_GPIO {1} \
|
||||
CONFIG.PCW_EN_EMIO_I2C0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_I2C1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_PJTAG {0} \
|
||||
CONFIG.PCW_EN_EMIO_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SPI0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SPI1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
|
||||
CONFIG.PCW_EN_EMIO_TRACE {0} \
|
||||
CONFIG.PCW_EN_EMIO_TTC0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_TTC1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_UART0 {1} \
|
||||
CONFIG.PCW_EN_EMIO_UART1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_WDT {0} \
|
||||
CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_ENET0 {1} \
|
||||
CONFIG.PCW_EN_ENET1 {0} \
|
||||
CONFIG.PCW_EN_GPIO {0} \
|
||||
CONFIG.PCW_EN_I2C0 {0} \
|
||||
CONFIG.PCW_EN_I2C1 {0} \
|
||||
CONFIG.PCW_EN_MODEM_UART0 {0} \
|
||||
CONFIG.PCW_EN_MODEM_UART1 {0} \
|
||||
CONFIG.PCW_EN_PJTAG {0} \
|
||||
CONFIG.PCW_EN_PTP_ENET0 {0} \
|
||||
CONFIG.PCW_EN_PTP_ENET1 {0} \
|
||||
CONFIG.PCW_EN_QSPI {1} \
|
||||
CONFIG.PCW_EN_RST0_PORT {0} \
|
||||
CONFIG.PCW_EN_RST1_PORT {0} \
|
||||
CONFIG.PCW_EN_RST2_PORT {0} \
|
||||
CONFIG.PCW_EN_RST3_PORT {0} \
|
||||
CONFIG.PCW_EN_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_SMC {0} \
|
||||
CONFIG.PCW_EN_SPI0 {0} \
|
||||
CONFIG.PCW_EN_SPI1 {0} \
|
||||
CONFIG.PCW_EN_TRACE {0} \
|
||||
CONFIG.PCW_EN_TTC0 {1} \
|
||||
CONFIG.PCW_EN_TTC1 {0} \
|
||||
CONFIG.PCW_EN_UART0 {1} \
|
||||
CONFIG.PCW_EN_UART1 {0} \
|
||||
CONFIG.PCW_EN_USB0 {0} \
|
||||
CONFIG.PCW_EN_USB1 {0} \
|
||||
CONFIG.PCW_EN_WDT {0} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \
|
||||
CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
|
||||
CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
|
||||
CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \
|
||||
CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
|
||||
CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_IO {32} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {32} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \
|
||||
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
|
||||
CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
|
||||
CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
|
||||
CONFIG.PCW_IRQ_F2P_INTR {1} \
|
||||
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
|
||||
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_16_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_16_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_17_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_17_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_18_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_18_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_19_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_19_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_1_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_20_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_20_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_21_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_21_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_22_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_22_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_23_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_23_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_24_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_24_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_25_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_25_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_26_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_26_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_27_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_27_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_2_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_30_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_30_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_31_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_31_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_3_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_4_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_52_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_52_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_53_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_53_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_5_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_6_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_PRIMITIVE {54} \
|
||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet\
|
||||
0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#unassigned#unassigned#Timer 0#Timer 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet\
|
||||
0#Enet 0} \
|
||||
CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#unassigned#unassigned#wave_out#clk_in#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#mdc#mdio}\
|
||||
\
|
||||
CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
|
||||
CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
|
||||
CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
|
||||
CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_AR {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_RC {11} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_REA {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_RR {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_WC {11} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_WP {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_PC {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_RC {11} \
|
||||
CONFIG.PCW_NOR_CS0_T_TR {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_WC {11} \
|
||||
CONFIG.PCW_NOR_CS0_T_WP {1} \
|
||||
CONFIG.PCW_NOR_CS0_WE_TIME {0} \
|
||||
CONFIG.PCW_NOR_CS1_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_CS1_T_PC {1} \
|
||||
CONFIG.PCW_NOR_CS1_T_RC {11} \
|
||||
CONFIG.PCW_NOR_CS1_T_TR {1} \
|
||||
CONFIG.PCW_NOR_CS1_T_WC {11} \
|
||||
CONFIG.PCW_NOR_CS1_T_WP {1} \
|
||||
CONFIG.PCW_NOR_CS1_WE_TIME {0} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
|
||||
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
|
||||
CONFIG.PCW_P2F_UART0_INTR {0} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.096} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.102} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.100} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.090} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.054} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.040} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.041} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.010} \
|
||||
CONFIG.PCW_PACKAGE_NAME {clg400} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
|
||||
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
|
||||
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
||||
CONFIG.PCW_SMC_CYCLE_T0 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T1 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T2 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T3 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T4 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T5 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T6 {NA} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
|
||||
CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
|
||||
CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
|
||||
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_TTC0_TTC0_IO {MIO 30 .. 31} \
|
||||
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
|
||||
CONFIG.PCW_UART0_BAUD_RATE {115200} \
|
||||
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
|
||||
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_UART0_UART0_IO {EMIO} \
|
||||
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {200.000000} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_AL {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BL {8} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.521} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.636} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.54} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.621} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.0515} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.0515} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.0515} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.0515} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {133.8645} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {119.997} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {121.146} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {90.125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.226} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.278} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.184} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.309} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {111.7605} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {123.5525} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {120.714} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {100.836} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
|
||||
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {200} \
|
||||
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
|
||||
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
|
||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
|
||||
CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \
|
||||
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
|
||||
CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
|
||||
CONFIG.PCW_USE_AXI_NONSECURE {0} \
|
||||
CONFIG.PCW_USE_CORESIGHT {0} \
|
||||
CONFIG.PCW_USE_CROSS_TRIGGER {0} \
|
||||
CONFIG.PCW_USE_CR_FABRIC {1} \
|
||||
CONFIG.PCW_USE_DDR_BYPASS {0} \
|
||||
CONFIG.PCW_USE_DEBUG {0} \
|
||||
CONFIG.PCW_USE_DMA0 {0} \
|
||||
CONFIG.PCW_USE_DMA1 {0} \
|
||||
CONFIG.PCW_USE_DMA2 {0} \
|
||||
CONFIG.PCW_USE_DMA3 {0} \
|
||||
CONFIG.PCW_USE_EXPANDED_IOP {0} \
|
||||
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
|
||||
CONFIG.PCW_USE_HIGH_OCM {0} \
|
||||
CONFIG.PCW_USE_M_AXI_GP0 {1} \
|
||||
CONFIG.PCW_USE_M_AXI_GP1 {0} \
|
||||
CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
|
||||
CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
|
||||
CONFIG.PCW_USE_S_AXI_ACP {0} \
|
||||
CONFIG.PCW_USE_S_AXI_GP0 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_GP1 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP0 {1} \
|
||||
CONFIG.PCW_USE_S_AXI_HP1 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP2 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP3 {0} \
|
||||
CONFIG.PCW_USE_TRACE {0} \
|
||||
CONFIG.PCW_VALUE_SILVERSION {3} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
|
||||
] $ps
|
||||
|
||||
|
||||
# Create instance: rst_ps7_100M, and set properties
|
||||
set rst_ps7_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_100M ]
|
||||
|
||||
# Create instance: xlconcat_0, and set properties
|
||||
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
|
||||
set_property CONFIG.NUM_PORTS {5} $xlconcat_0
|
||||
|
||||
|
||||
# Create instance: vio_0, and set properties
|
||||
set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
|
||||
CONFIG.C_NUM_PROBE_IN {1} \
|
||||
] $vio_0
|
||||
|
||||
|
||||
# Create instance: mdm_0, and set properties
|
||||
set mdm_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_MB_DBG_PORTS {0} \
|
||||
CONFIG.C_USE_UART {1} \
|
||||
] $mdm_0
|
||||
|
||||
|
||||
# Create instance: ad9361_driver
|
||||
create_hier_cell_ad9361_driver [current_bd_instance .] ad9361_driver
|
||||
|
||||
# Create instance: axis_dwidth_converter_0, and set properties
|
||||
set axis_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_0 ]
|
||||
set_property CONFIG.M_TDATA_NUM_BYTES {1} $axis_dwidth_converter_0
|
||||
|
||||
|
||||
# Create instance: axis_data_fifo_0, and set properties
|
||||
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.FIFO_DEPTH {16} \
|
||||
CONFIG.FIFO_MEMORY_TYPE {distributed} \
|
||||
CONFIG.HAS_RD_DATA_COUNT {0} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.IS_ACLK_ASYNC {0} \
|
||||
] $axis_data_fifo_0
|
||||
|
||||
|
||||
# Create instance: axi_lite_control_0, and set properties
|
||||
set block_name axi_lite_control
|
||||
set block_cell_name axi_lite_control_0
|
||||
if { [catch {set axi_lite_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_lite_control_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect/S00_AXI] [get_bd_intf_pins ps/M_AXI_GP0]
|
||||
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_src_fifo/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M00_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins axi_interconnect/M00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M01_AXI [get_bd_intf_pins axi_interconnect/M01_AXI] [get_bd_intf_pins ad9361_driver/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M02_AXI [get_bd_intf_pins axi_interconnect/M02_AXI] [get_bd_intf_pins axi_lite_control_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M03_AXI [get_bd_intf_pins axi_interconnect/M03_AXI] [get_bd_intf_pins mdm_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ps/S_AXI_HP0]
|
||||
connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_ports tx_data_src] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_data_src_fifo_M_AXIS [get_bd_intf_pins axis_data_src_fifo/M_AXIS] [get_bd_intf_pins axis_dwidth_converter_0/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins axis_dwidth_converter_0/M_AXIS] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports ddr] [get_bd_intf_pins ps/DDR]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports fixed_io] [get_bd_intf_pins ps/FIXED_IO]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ARESETN_1 [get_bd_pins rst_ps7_100M/interconnect_aresetn] [get_bd_pins axi_interconnect/ARESETN]
|
||||
connect_bd_net -net GPIO_I_1_1 [get_bd_ports gpio_i] [get_bd_pins ps/GPIO_I]
|
||||
connect_bd_net -net In2_0_1 [get_bd_ports pl2ps_intr2] [get_bd_pins xlconcat_0/In2]
|
||||
connect_bd_net -net In3_0_1 [get_bd_ports pl2ps_intr3] [get_bd_pins xlconcat_0/In3]
|
||||
connect_bd_net -net Net1 [get_bd_ports clk_ps] [get_bd_pins ps/M_AXI_GP0_ACLK] [get_bd_pins ps/S_AXI_HP0_ACLK] [get_bd_pins ad9361_driver/clk_sys] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_interconnect/ACLK] [get_bd_pins axi_interconnect/S00_ACLK] [get_bd_pins axi_interconnect/M00_ACLK] [get_bd_pins axi_interconnect/M01_ACLK] [get_bd_pins axi_interconnect/M02_ACLK] [get_bd_pins axi_interconnect/M03_ACLK] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_data_src_fifo/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_dwidth_converter_0/aclk] [get_bd_pins mdm_0/S_AXI_ACLK] [get_bd_pins rst_ps7_100M/slowest_sync_clk] [get_bd_pins vio_0/clk] [get_bd_pins axi_lite_control_0/s_axi_aclk] [get_bd_pins axi_lite_control_0/clk]
|
||||
connect_bd_net -net ad9361_spi_interface_1_ad9361_spi_clk [get_bd_pins ad9361_driver/ad9361_spi_clk] [get_bd_ports ad9361_spi_clk]
|
||||
connect_bd_net -net ad9361_spi_interface_1_ad9361_spi_csn [get_bd_pins ad9361_driver/ad9361_spi_csn] [get_bd_ports ad9361_spi_csn]
|
||||
connect_bd_net -net ad9361_spi_interface_1_ad9361_spi_mosi [get_bd_pins ad9361_driver/ad9361_spi_mosi] [get_bd_ports ad9361_spi_mosi]
|
||||
connect_bd_net -net ad9361_spi_miso_0_1 [get_bd_ports ad9361_spi_miso] [get_bd_pins ad9361_driver/ad9361_spi_miso]
|
||||
connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0]
|
||||
connect_bd_net -net axi_lite_control_0_tx_test_flag [get_bd_pins axi_lite_control_0/tx_test_flag] [get_bd_ports tx_test_flag]
|
||||
connect_bd_net -net axis_data_fifo_0_axis_rd_data_count [get_bd_pins axis_data_src_fifo/axis_rd_data_count] [get_bd_ports tx_data_src_count] [get_bd_pins vio_0/probe_in0]
|
||||
connect_bd_net -net mdm_0_Interrupt [get_bd_pins mdm_0/Interrupt] [get_bd_pins xlconcat_0/In4]
|
||||
connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins ps/GPIO_O] [get_bd_ports gpio_o]
|
||||
connect_bd_net -net processing_system7_0_GPIO_T [get_bd_pins ps/GPIO_T] [get_bd_ports gpio_t]
|
||||
connect_bd_net -net processing_system7_0_UART0_TX [get_bd_pins ps/UART0_TX] [get_bd_ports uart_tx]
|
||||
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins rst_ps7_100M/peripheral_aresetn] [get_bd_pins ad9361_driver/s_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_interconnect/S00_ARESETN] [get_bd_pins axi_interconnect/M00_ARESETN] [get_bd_pins axi_interconnect/M01_ARESETN] [get_bd_pins axi_interconnect/M02_ARESETN] [get_bd_pins axi_interconnect/M03_ARESETN] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_data_src_fifo/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_dwidth_converter_0/aresetn] [get_bd_pins mdm_0/S_AXI_ARESETN] [get_bd_pins axi_lite_control_0/s_axi_aresetn] [get_bd_pins axi_lite_control_0/rstn]
|
||||
connect_bd_net -net rst_ps_1 [get_bd_ports rst_ps] [get_bd_pins rst_ps7_100M/ext_reset_in]
|
||||
connect_bd_net -net uart0_rx_1 [get_bd_ports uart_rx] [get_bd_pins ps/UART0_RX]
|
||||
connect_bd_net -net vio_0_probe_out0 [get_bd_pins vio_0/probe_out0] [get_bd_pins xlconcat_0/In1] [get_bd_pins axi_lite_control_0/req]
|
||||
connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins ps/IRQ_F2P]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x00020000 -with_name SEG_processing_system7_0_HP0_DDR_LOWOCM -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs ps/S_AXI_HP0/HP0_DDR_LOWOCM] -force
|
||||
assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
|
||||
assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/Data] [get_bd_addr_segs axi_lite_control_0/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/Data] [get_bd_addr_segs ad9361_driver/axi_spi_engine_0/s_axi/axi_lite] -force
|
||||
assign_bd_address -offset 0x43400000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/Data] [get_bd_addr_segs mdm_0/S_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
memory_initialization_radix=2;
|
||||
memory_initialization_vector =
|
||||
1100111110100111100101001111010010011111101001011010000011011000
|
||||
1000101110110011000111011000111111001010011111101010100010111011
|
||||
1010011110101110011111101110100010100110100001011000000011100011
|
||||
1110100100100010111110011110000100110011010110011011001010000100
|
||||
1001000111110111001010101110100011110010110101101011111101111000
|
||||
0011000010100001111110000011101100111100110110111101010001100011
|
||||
1100111010010101110000001110110000011111011000001001001101110000
|
||||
1101011111100111100100011100100001110000001000101001110000011110
|
||||
0111000111101111001111111101111101100000111000101000011110000100
|
||||
0111100010010011010011011011001010000101110111101100100111011100
|
||||
0000111010010101110000010000001100000000100010110110101111001101
|
||||
1101001011011010111110000101110010101110011100110010001000010000
|
||||
1000001100100110111011101000001111000001111110111010010101101111
|
||||
1101110100010101101100101101110110110011000111111110011111110010
|
||||
0011101110100000101110110100001111111000001111000110011110111101
|
||||
1010000111110110101011101110010001101010111011110100111001100010
|
||||
0101011001010000100000110111100000001100101010001001101011001010
|
||||
1010011100001100110011111011010010101000100010001010111000110101
|
||||
0001001000010000111110101101000011101100100101100000001011001100
|
||||
1000110010010110101100001010100001101101001110011001011010100011
|
||||
1100000010110000011111111101110110100111001101000101010011000010
|
||||
0101001010010101111101110010101111010101000000000100111010000000
|
||||
1010110011001111100101110011111111000011000000100110000111001001
|
||||
1001000001010010010110101010000011001011101000000000011010111101
|
||||
1001111100000111100111110000100110100100000001011111011111111000
|
||||
0111101011011001100001000010100100001001011011110010101001111110
|
||||
1110101110001100100110110001001110111000010011000000011011100100
|
||||
0010100001000011101001000111011010001001101010011100010100101000
|
||||
1101101010101010000110100001011101011111010110011000110111001111
|
||||
1101101110101101010000100110110010100100001110101101010001111001
|
||||
0001101110100111100000110010011011100111010111110011100011101011
|
||||
0110111011010000100110100100010100110000001110100110010000100101
|
||||
0100100011110100001000000011001110110111101110011010000001010001
|
||||
0100100111011100100000111001110010010000001010010001111010011000
|
||||
1001101100101100111010111110010100001010011111000010110000100110
|
||||
0100111111000110111001111101011001110100000001100011010110001001
|
||||
1111010110110110110111101010111010111111011100100001000001101011
|
||||
1010100111100110011001110110010101100100110000010111000100110100
|
||||
0110110101011001010101000101010110001101001000110101000110010001
|
||||
0101000010101010111110001000110101110000000010001110011000110100
|
||||
0001111110101001011000101111101110101011100001100100101001011111
|
||||
1000011001111100100111010110110011110100111000001000011110101010
|
||||
0101110101111010101001100111010010111010010010110001110110001100
|
||||
1101011110101110100100011000011011110001110100111011001000111011
|
||||
0000010001111111000100010010011110010001111011101001011110110110
|
||||
0011111110110111101101011000111111110011101110010100111010010101
|
||||
1001001110111110001110011010011000110110010111000110011010111000
|
||||
0111011110101101001100010110100101100101101001110010111101011011
|
||||
0001101101011000111110001000111001001001110000000000110111000110
|
||||
1011001101011000010101011011111111110010001010001010000010001000
|
||||
0101110010001110110101000111101101100001111011101100011001101011
|
||||
0101000000000100111110110110111001100101110010111110110011110011
|
||||
0111011101111000100110011001100011111110100000001001001001011110
|
||||
0000001000110111111101010111000011100000010011000101111101011011
|
||||
1110110101100111011101100110000111101011011111111100001110000010
|
||||
0101101010110101110101011101100101101000110000001000000010001100
|
||||
0010101111011011100000101000101100011001010110010011111101000001
|
||||
0110011100011011100011010000110101000001110111110001001101101100
|
||||
1100101101000111010101010011110010011011001111110000111010100000
|
||||
0001011011001100000101010101010011000011010111100110101001111101
|
||||
1001011101011000011111111110101010010001110100100000100110001110
|
||||
0001001001101110101001110011110011000111100001100101100010100110
|
||||
1010110111100001100101110001000100100000100000011000011011001010
|
||||
1001010111000111010000010111101000010101011010010000110001000101
|
||||
1011111010011100000101101001110110001000100100110011100111011001
|
||||
0110010101001100100101110110101010000101110011111101100111110111
|
||||
0100011111000100000101001000111000111011010001110001001011011010
|
||||
1010001110111010110100011010110101110001100001110011110100111010
|
||||
0001110011010110001100001100001101000010110001011110101110111001
|
||||
0001100000111010110111101001101111101111001010010100111010001110
|
||||
0111000000010100110000000111011110100101111110010110111101110101
|
||||
1011111001010110011011001000011001101001011001001101000000011100
|
||||
1110011100101010110001000011101000110101101011010010000101100110
|
||||
0111001011101011101100110010010110011011011101111111100110111011
|
||||
0001100011011010100010110000100100011001010011111010000111110000
|
||||
1110100001110110101000001000000011001001110101101010001110011111
|
||||
1000000010011011000101101000101000111101100010001110100011101001
|
||||
0011110110011001010111001110010100100011001011000010110111000010
|
||||
1100011111001111101001000100101000110110001111110110001010001010
|
||||
0110011010001101010001101100001110011000110010101111100101101111
|
||||
1101010101111101101110110010010010101110001001111010110010100001
|
||||
0111000101101111100011101010000110111000101010100001000010000110
|
||||
0111101101110111100101101111010010101000011011110001111111010101
|
||||
0100110001110101011101101010110100000001110001101000100101010011
|
||||
1110011101011011111001111001100100000010010001001000001000110110
|
||||
1000111100000110100101100101100011110111101010101010111110110000
|
||||
1001011101011111001110101111011110010101111001111000110100100101
|
||||
0101100001110001110001110001101101001111010010110111011111110110
|
||||
0110010111001101100111000011010110011011101100101010100000101101
|
||||
0101001101010011111000000000011100010110011010111101110101000001
|
||||
0010110001010100010001110011000101001101101100000010011110110001
|
||||
0000101100010011000000000111000110101101000000111001100011010001
|
||||
1101111000011001101111000111101001101011101111001111011010100000
|
||||
1111111100000010000110101010101111110001001010010010000010100101
|
||||
0101100010111010111011010100100001001010111110001001111000101001
|
||||
1101010011011011110000010111000011001110111100011101001101101001
|
||||
0100110000110011000010110010110100010001111000010101101101011100
|
||||
1011001110000001010111100000100101100000010100110011100010100110
|
||||
0111010111100011110100011010001101010100000111100000111000101000
|
||||
0100111101100101010101101101011010001101001111001000101010011110
|
||||
1110010110111011001110110010100101111101101101100010110011010010
|
||||
1001000001111111000010011001100101101001011001111010000011110100
|
||||
1111111100110011101011101110111000101100100010100100101001010010
|
||||
1111110011001111010111000011100111010011010101011100001110011100
|
||||
0101111111100101111100001001101010111010011010111100110011100000
|
||||
0010101001110011010000000001111001011111100001111110101011000010
|
||||
1101011101010111000000101111010011110101011101100111000011011111
|
||||
1010011100001011000111000000000000101111010100100011111011101010
|
||||
0110110011100001110011100010111000000101110101000010000011001011
|
||||
1000011001111110110000000001011001101011100011100101001110101001
|
||||
1001110111111001100000000001101000011100001100110000010110001101
|
||||
1101000100010110101000001010111001110010011110001011101110111001
|
||||
0100110011110000101100001100011110010010110111011000111111011011
|
||||
0011111011001110101011100110111100101011011111110110011000111101
|
||||
0001000001101010000111000010100101101110010001111100000101001100
|
||||
0001010010011000101100000100010111010101011111011110111110110101
|
||||
1001011010001111011011011000110001111001000000100110001111000011
|
||||
0101001111001111001100000111111011111001000011000001111100100001
|
||||
0110011011100110101101100011001011110110011000010100111001011000
|
||||
0010011001111110111100001001011011000011011101110001100010100011
|
||||
0011110101000110111001011101000100001110100110010011111010110110
|
||||
1101111110000001010100011000111110001000010111101101101000011011
|
||||
0110111111110101000110001111110101001000101110111000111010011101
|
||||
1101101111101101010010101100000011110100111101011110101110001001
|
||||
1011110011000110010011010010000110100110010111011011001101111001
|
||||
1010101111100010111001001101110000100001111100010000100111111111
|
||||
0010111011000000110011100111101101011101010000001001011100111101
|
||||
0001001111101100111101110001001110110000000111000110111100010000
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
memory_initialization_radix=16;
|
||||
memory_initialization_vector=00007FFF F6967FA6 DAD87A7C B14164E8 89BF30FB 84A4DDDD C3AA8F1E 398C8DAC 7FFF0000 28267989 8F1E3C56 C0E990A2 7641CF05 0FAB7F09 8584DAD8 60EBAC65 00007FFF AC659F15 7A7C2528 80F70FAB 7641CF05 90A23F17 70E2C3AA 86772826 7FFF0000 8DACC674 3C5670E2 222384A4 89BF30FB 64E84EBF 25288584 805AF696 00007FFF 7FA6096A 25288584 9B18B141 89BF30FB DDDD7B5C 3C5670E2 7254398C 7FFF0000 7989D7DA 70E2C3AA 6F5EC0E9 7641CF05 7F09F055 7A7C2528 539B60EB 00007FFF 9F15539B 8584DAD8 F05580F7 7641CF05 3F176F5E 8F1E3C56 D7DA8677 7FFF0000 C6747254 C3AA8F1E 7B5C2223 89BF30FB 4EBF9B18 DAD87A7C 096A805A 00007FFF 096A805A DAD87A7C 4EBF9B18 89BF30FB 7B5C2223 C3AA8F1E C6747254 7FFF0000 D7DA8677 8F1E3C56 3F176F5E 7641CF05 F05580F7 8584DAD8 9F15539B 00007FFF 539B60EB 7A7C2528 7F09F055 7641CF05 6F5EC0E9 70E2C3AA 7989D7DA 7FFF0000 7254398C 3C5670E2 DDDD7B5C 89BF30FB 9B18B141 25288584 7FA6096A 00007FFF 805AF696 25288584 64E84EBF 89BF30FB 222384A4 3C5670E2 8DACC674 7FFF0000 86772826 70E2C3AA 90A23F17 7641CF05 80F70FAB 7A7C2528 AC659F15 00007FFF 60EBAC65 8584DAD8 0FAB7F09 7641CF05 C0E990A2 8F1E3C56 28267989 7FFF0000 398C8DAC C3AA8F1E 84A4DDDD 89BF30FB B14164E8 DAD87A7C F6967FA6;
|
||||
@@ -0,0 +1,66 @@
|
||||
memory_initialization_radix=2;
|
||||
memory_initialization_vector =
|
||||
11001111101001111001010011110100100111111010010110100000110110001000101110110011000111011000111111001010011111101010100010111011
|
||||
10100111101011100111111011101000101001101000010110000000111000111110100100100010111110011110000100110011010110011011001010000100
|
||||
10010001111101110010101011101000111100101101011010111111011110000011000010100001111110000011101100111100110110111101010001100011
|
||||
11001110100101011100000011101100000111110110000010010011011100001101011111100111100100011100100001110000001000101001110000011110
|
||||
01110001111011110011111111011111011000001110001010000111100001000111100010010011010011011011001010000101110111101100100111011100
|
||||
00001110100101011100000100000011000000001000101101101011110011011101001011011010111110000101110010101110011100110010001000010000
|
||||
10000011001001101110111010000011110000011111101110100101011011111101110100010101101100101101110110110011000111111110011111110010
|
||||
00111011101000001011101101000011111110000011110001100111101111011010000111110110101011101110010001101010111011110100111001100010
|
||||
01010110010100001000001101111000000011001010100010011010110010101010011100001100110011111011010010101000100010001010111000110101
|
||||
00010010000100001111101011010000111011001001011000000010110011001000110010010110101100001010100001101101001110011001011010100011
|
||||
11000000101100000111111111011101101001110011010001010100110000100101001010010101111101110010101111010101000000000100111010000000
|
||||
10101100110011111001011100111111110000110000001001100001110010011001000001010010010110101010000011001011101000000000011010111101
|
||||
10011111000001111001111100001001101001000000010111110111111110000111101011011001100001000010100100001001011011110010101001111110
|
||||
11101011100011001001101100010011101110000100110000000110111001000010100001000011101001000111011010001001101010011100010100101000
|
||||
11011010101010100001101000010111010111110101100110001101110011111101101110101101010000100110110010100100001110101101010001111001
|
||||
00011011101001111000001100100110111001110101111100111000111010110110111011010000100110100100010100110000001110100110010000100101
|
||||
01001000111101000010000000110011101101111011100110100000010100010100100111011100100000111001110010010000001010010001111010011000
|
||||
10011011001011001110101111100101000010100111110000101100001001100100111111000110111001111101011001110100000001100011010110001001
|
||||
11110101101101101101111010101110101111110111001000010000011010111010100111100110011001110110010101100100110000010111000100110100
|
||||
01101101010110010101010001010101100011010010001101010001100100010101000010101010111110001000110101110000000010001110011000110100
|
||||
00011111101010010110001011111011101010111000011001001010010111111000011001111100100111010110110011110100111000001000011110101010
|
||||
01011101011110101010011001110100101110100100101100011101100011001101011110101110100100011000011011110001110100111011001000111011
|
||||
00000100011111110001000100100111100100011110111010010111101101100011111110110111101101011000111111110011101110010100111010010101
|
||||
10010011101111100011100110100110001101100101110001100110101110000111011110101101001100010110100101100101101001110010111101011011
|
||||
00011011010110001111100010001110010010011100000000001101110001101011001101011000010101011011111111110010001010001010000010001000
|
||||
01011100100011101101010001111011011000011110111011000110011010110101000000000100111110110110111001100101110010111110110011110011
|
||||
01110111011110001001100110011000111111101000000010010010010111100000001000110111111101010111000011100000010011000101111101011011
|
||||
11101101011001110111011001100001111010110111111111000011100000100101101010110101110101011101100101101000110000001000000010001100
|
||||
00101011110110111000001010001011000110010101100100111111010000010110011100011011100011010000110101000001110111110001001101101100
|
||||
11001011010001110101010100111100100110110011111100001110101000000001011011001100000101010101010011000011010111100110101001111101
|
||||
10010111010110000111111111101010100100011101001000001001100011100001001001101110101001110011110011000111100001100101100010100110
|
||||
10101101111000011001011100010001001000001000000110000110110010101001010111000111010000010111101000010101011010010000110001000101
|
||||
10111110100111000001011010011101100010001001001100111001110110010110010101001100100101110110101010000101110011111101100111110111
|
||||
01000111110001000001010010001110001110110100011100010010110110101010001110111010110100011010110101110001100001110011110100111010
|
||||
00011100110101100011000011000011010000101100010111101011101110010001100000111010110111101001101111101111001010010100111010001110
|
||||
01110000000101001100000001110111101001011111100101101111011101011011111001010110011011001000011001101001011001001101000000011100
|
||||
11100111001010101100010000111010001101011010110100100001011001100111001011101011101100110010010110011011011101111111100110111011
|
||||
00011000110110101000101100001001000110010100111110100001111100001110100001110110101000001000000011001001110101101010001110011111
|
||||
10000000100110110001011010001010001111011000100011101000111010010011110110011001010111001110010100100011001011000010110111000010
|
||||
11000111110011111010010001001010001101100011111101100010100010100110011010001101010001101100001110011000110010101111100101101111
|
||||
11010101011111011011101100100100101011100010011110101100101000010111000101101111100011101010000110111000101010100001000010000110
|
||||
01111011011101111001011011110100101010000110111100011111110101010100110001110101011101101010110100000001110001101000100101010011
|
||||
11100111010110111110011110011001000000100100010010000010001101101000111100000110100101100101100011110111101010101010111110110000
|
||||
10010111010111110011101011110111100101011110011110001101001001010101100001110001110001110001101101001111010010110111011111110110
|
||||
01100101110011011001110000110101100110111011001010101000001011010101001101010011111000000000011100010110011010111101110101000001
|
||||
00101100010101000100011100110001010011011011000000100111101100010000101100010011000000000111000110101101000000111001100011010001
|
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||||
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|
||||
File diff suppressed because it is too large
Load Diff
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|
||||
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|
||||
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||||
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||||
@@ -0,0 +1,2 @@
|
||||
memory_initialization_radix=2;
|
||||
memory_initialization_vector=1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 0 0 1 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0;
|
||||
@@ -0,0 +1,4 @@
|
||||
memory_initialization_radix=2;
|
||||
memory_initialization_vector=
|
||||
1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0
|
||||
;
|
||||
@@ -0,0 +1,2 @@
|
||||
radix=10;
|
||||
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|
||||
@@ -0,0 +1,2 @@
|
||||
radix=10;
|
||||
coefdata=1 1 1 1 -1 1 1 1 -1 -1 1 1 -1 1 1 1 -1 -1 -1 1 -1 1 -1 1 -1 -1 1 -1 -1 1 1 1 -1 -1 -1 1 1 1 -1 1 1 -1 1 -1 1 -1 1 1 1 -1 -1 1 -1 -1 1 1 -1 -1 -1 -1 -1 1 1 -1 -1 -1 -1 1 1 1 -1 1 -1 -1 1 -1 -1 -1 1 1 -1 1 -1 1 1 -1 1 1 1 1 1 -1 1 1 -1 -1 1 1 -1 -1 -1 1 -1 1 1 1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 1 1 1 1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 1 1 1 -1 -1 -1 -1 1 -1 -1 -1 1 1 1 1 -1 1 -1 -1 1 1 -1 -1 1 -1 -1 1 -1 -1 -1 -1 1 -1 1 1 1 1 -1 -1 -1 1 1 -1 -1 1 1 1 1 -1 1 1 -1 1 1 1 -1 1 -1 1 -1 -1 -1 1 -1 1 -1 -1 -1 -1 1 1 -1 1 1 -1 1 -1 -1 -1 1 1 -1 -1 -1 1 1 1 1 1 1 -1 -1 -1 1 -1 -1 -1 1 -1 1 1 -1 -1 -1 -1 1 -1 1 -1 1 1 -1 1 -1 1 1 1 1 1 1 -1 1 -1 1 -1 1 -1 1 -1 -1 -1 -1 -1 1 -1 1 -1 -1 1 -1 1 1 1 1 1 -1 -1 1 -1 -1 -1 1 -1 -1 1 -1 -1 1 -1 1 -1 -1 1 1 1 1 1 -1 1 -1 -1 -1 1 -1 -1 -1 -1 -1 1 1 1 -1 -1 -1 -1 1 1 -1 -1 1 -1 1 1 -1 -1 1 -1 1 -1 -1 -1 1 1 1 -1 -1 1 -1 1 1 1 -1 1 -1 -1 -1 -1 -1 -1 -1 1 -1 1 1 -1 1 -1 -1 1 1 1 -1 1 -1 1 1 -1 -1 1 1 1 -1 -1 1 1 1 1 1 1 1 -1 -1 1 1 -1 -1 1 1 -1 1 -1 1 -1 -1 1 1 -1 1 1 -1 -1 -1 -1 -1 -1 1 -1 -1 1 -1 1 1 -1 1 1 -1 1 1 -1 -1 1 -1 -1 -1 -1 -1 -1 1 1 -1 1 -1 -1 1 -1 1 -1 1 1 1 1 -1 1 -1 1 1 1 -1 1 1 -1 -1 -1 1 -1 -1 1 1 -1 1 -1 -1 -1 -1 1 -1 -1 1 1 1 1 -1 -1 1 -1 1 -1 1 -1 1 1 -1 -1 -1 1 1 -1 1 1 1 1 -1 -1 1 1 1 -1 1 1 1 1 -1 1 1 1 1 1 1 1 1 -1;
|
||||
@@ -0,0 +1,74 @@
|
||||
#
|
||||
|
||||
## Timing Assertions Section
|
||||
create_clock -period 20.000 [get_ports ad9361_rx_clk]
|
||||
|
||||
## Physical Constraints Section
|
||||
|
||||
# AD9361 Interface
|
||||
# port 0
|
||||
set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS25} [get_ports ad9361_rx_clk]
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports ad9361_rx_frame]
|
||||
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[0]}]
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[1]}]
|
||||
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[2]}]
|
||||
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[3]}]
|
||||
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[4]}]
|
||||
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[5]}]
|
||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[6]}]
|
||||
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[7]}]
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[8]}]
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[9]}]
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[10]}]
|
||||
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {ad9361_rx_data[11]}]
|
||||
|
||||
# port 1
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports ad9361_tx_clk]
|
||||
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS25} [get_ports ad9361_tx_frame]
|
||||
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[0]}]
|
||||
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[1]}]
|
||||
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[2]}]
|
||||
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[3]}]
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[4]}]
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[5]}]
|
||||
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[6]}]
|
||||
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[7]}]
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[8]}]
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[9]}]
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[10]}]
|
||||
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports {ad9361_tx_data[11]}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports ad9361_spi_clk]
|
||||
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS25} [get_ports ad9361_spi_csn]
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports ad9361_spi_mosi]
|
||||
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports ad9361_spi_miso]
|
||||
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS25} [get_ports ad9361_reset_b]
|
||||
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad9361_en_agc]
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports ad9361_enable]
|
||||
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad9361_txnrx]
|
||||
|
||||
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS25} [get_ports {ad9361_ctrl_in[0]}]
|
||||
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports {ad9361_ctrl_in[1]}]
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS25} [get_ports {ad9361_ctrl_in[2]}]
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports {ad9361_ctrl_in[3]}]
|
||||
|
||||
## CONTROL LED & GPIO
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports led_red]
|
||||
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports led_yellow]
|
||||
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports led_blue]
|
||||
|
||||
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {rf_gpio[0]}]
|
||||
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports {rf_gpio[1]}]
|
||||
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {rf_gpio[2]}]
|
||||
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {rf_gpio[3]}]
|
||||
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {rf_gpio[4]}]
|
||||
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {rf_gpio[5]}]
|
||||
|
||||
set_property -dict { IOSTANDARD LVCMOS25 PACKAGE_PIN H16 } [get_ports clk_crystal]
|
||||
create_clock -period 25.000 [get_ports clk_crystal]
|
||||
|
||||
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN T10 } [get_ports uart_rx]
|
||||
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN T11 } [get_ports uart_tx]
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
@@ -0,0 +1,3 @@
|
||||
set_property MAX_FANOUT 512 [get_nets *u_Receiver/mag*]
|
||||
# set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid]
|
||||
set_false_path -through [get_nets u_Receiver/rst]
|
||||
@@ -0,0 +1,28 @@
|
||||
# 重建工程
|
||||
# 添加HDL文件
|
||||
add_files -fileset sources_1 ./source/hdl/
|
||||
# 添加XDC文件
|
||||
add_files -fileset constrs_1 ./source/contraint/mm7020.xdc
|
||||
# 添加tb文件
|
||||
add_files -fileset sim_1 ./source/sim/
|
||||
update_compile_order -fileset sources_1
|
||||
# 添加adi的库
|
||||
set_property ip_repo_paths ./source/adi_library [current_fileset]
|
||||
update_ip_catalog
|
||||
|
||||
# 添加IP
|
||||
set ip_folder "./source/ip"
|
||||
set xci_files [glob -nocomplain -type f [file join $ip_folder * *.xci]]
|
||||
# foreach file $xci_files {
|
||||
# puts $file
|
||||
# }
|
||||
add_files $xci_files
|
||||
|
||||
# 添加coe文件
|
||||
set coe_folder "./source/coe"
|
||||
set coe_files [glob -nocomplain -type f [file join $coe_folder *.coe]]
|
||||
add_files -fileset sources_1 $coe_files
|
||||
|
||||
|
||||
# 创建block design
|
||||
source ./source/bd/MM7020_BD.tcl
|
||||
@@ -0,0 +1,451 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/01/18 14:57:46
|
||||
// Design Name:
|
||||
// Module Name: CCSDS_LDPC_ENC_R12
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CCSDS_LDPC_ENC_R12(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input Encoder_SyncIn,
|
||||
input Encoder_Nd,
|
||||
input Encoder_Din,
|
||||
|
||||
output reg Encode_Dout = 1'd0,
|
||||
output reg Encode_Sync_Dout = 1'd0,
|
||||
output reg Encode_Rdy = 1'd0
|
||||
);
|
||||
reg Encoder_Din_d01 = 1'd0; reg Encoder_Din_d02 = 1'd0; reg Encoder_Din_d03 = 1'd0; reg Encoder_Din_d04 = 1'd0; reg Encoder_Din_d05 = 1'd0;
|
||||
reg Encoder_Din_d06 = 1'd0; reg Encoder_Din_d07 = 1'd0; reg Encoder_Din_d08 = 1'd0; reg Encoder_Din_d09 = 1'd0; reg Encoder_Din_d10 = 1'd0;
|
||||
reg Encoder_Din_d11 = 1'd0; reg Encoder_Din_d12 = 1'd0; reg Encoder_Din_d13 = 1'd0; reg Encoder_Din_d14 = 1'd0; reg Encoder_Din_d15 = 1'd0;
|
||||
reg Encoder_Din_d16 = 1'd0; reg Encoder_Din_d17 = 1'd0; reg Encoder_Din_d18 = 1'd0; reg Encoder_Din_d19 = 1'd0; reg Encoder_Din_d20 = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
Encoder_Din_d01 <= 1'd0; Encoder_Din_d02 <= 1'd0; Encoder_Din_d03 <= 1'd0; Encoder_Din_d04 <= 1'd0; Encoder_Din_d05 <= 1'd0;
|
||||
Encoder_Din_d06 <= 1'd0; Encoder_Din_d07 <= 1'd0; Encoder_Din_d08 <= 1'd0; Encoder_Din_d09 <= 1'd0; Encoder_Din_d10 <= 1'd0;
|
||||
Encoder_Din_d11 <= 1'd0; Encoder_Din_d12 <= 1'd0; Encoder_Din_d13 <= 1'd0; Encoder_Din_d14 <= 1'd0; Encoder_Din_d15 <= 1'd0;
|
||||
Encoder_Din_d16 <= 1'd0; Encoder_Din_d17 <= 1'd0; Encoder_Din_d18 <= 1'd0; Encoder_Din_d19 <= 1'd0; Encoder_Din_d20 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
Encoder_Din_d01 <= Encoder_Din;
|
||||
Encoder_Din_d02 <= Encoder_Din_d01; Encoder_Din_d03 <= Encoder_Din_d02; Encoder_Din_d04 <= Encoder_Din_d03; Encoder_Din_d05 <= Encoder_Din_d04;
|
||||
Encoder_Din_d06 <= Encoder_Din_d05; Encoder_Din_d07 <= Encoder_Din_d06; Encoder_Din_d08 <= Encoder_Din_d07; Encoder_Din_d09 <= Encoder_Din_d08;
|
||||
Encoder_Din_d10 <= Encoder_Din_d09; Encoder_Din_d11 <= Encoder_Din_d10; Encoder_Din_d12 <= Encoder_Din_d11; Encoder_Din_d13 <= Encoder_Din_d12;
|
||||
Encoder_Din_d14 <= Encoder_Din_d13; Encoder_Din_d15 <= Encoder_Din_d14; Encoder_Din_d16 <= Encoder_Din_d15; Encoder_Din_d17 <= Encoder_Din_d16;
|
||||
Encoder_Din_d18 <= Encoder_Din_d17; Encoder_Din_d19 <= Encoder_Din_d18; Encoder_Din_d20 <= Encoder_Din_d19;
|
||||
end
|
||||
end
|
||||
|
||||
reg [10:0] cnt_din = 11'd0; //输入1024个时钟
|
||||
reg [10:0] cnt_din_d1 = 11'd0;
|
||||
reg [10:0] cnt_din_d2 = 11'd0;
|
||||
reg Encoder_Nd_d1 = 1'd0;
|
||||
reg Encoder_Nd_d2 = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
cnt_din [10:0] <= 11'd0;
|
||||
cnt_din_d1[10:0] <= 11'd0;
|
||||
cnt_din_d2[10:0] <= 11'd0;
|
||||
Encoder_Nd_d1 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_din_d1[10:0] <= cnt_din[10:0];
|
||||
cnt_din_d2[10:0] <= cnt_din_d1[10:0];
|
||||
Encoder_Nd_d1 <= Encoder_Nd;
|
||||
if(Encoder_SyncIn)begin
|
||||
cnt_din[10:0] <= 11'd1;
|
||||
end
|
||||
else begin
|
||||
if(Encoder_Nd)
|
||||
cnt_din[10:0] <= (cnt_din[10:0] == 11'd1024) ? 11'd0 : cnt_din[10:0] + 11'd1;
|
||||
else
|
||||
cnt_din[10:0] <= cnt_din[10:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [4:0] G_row_rd_clk_num = 5'd0; //完整读取G矩阵的一行需要时钟数
|
||||
reg [10:0] check_clk_num = 11'd0;
|
||||
reg Out_Info_bit = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
G_row_rd_clk_num[4:0] <= 5'd0;
|
||||
check_clk_num[10:0] <= 11'd0;
|
||||
Out_Info_bit <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
G_row_rd_clk_num[4:0] <= 5'd16;
|
||||
check_clk_num[10:0] <= 11'd1024;
|
||||
Out_Info_bit <= Encoder_Din_d20;
|
||||
end
|
||||
end
|
||||
|
||||
//G矩阵读取
|
||||
reg [6:0] G_matrix_addr = 7'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
G_matrix_addr[6:0] <= 7'd0;
|
||||
end
|
||||
else begin
|
||||
if(Encoder_SyncIn)begin
|
||||
G_matrix_addr[6:0] <= 7'd0;
|
||||
end
|
||||
else begin
|
||||
if(Encoder_Nd)begin
|
||||
if(cnt_din[6:0] >= 7'd1 && cnt_din[6:0] <= {2'd0,G_row_rd_clk_num[4:0]})
|
||||
G_matrix_addr[6:0] <= (G_matrix_addr[6:0] == 7'd127) ? 7'd0 : G_matrix_addr[6:0] + 7'd1;
|
||||
else
|
||||
G_matrix_addr[6:0] <= G_matrix_addr[6:0];
|
||||
end
|
||||
else
|
||||
G_matrix_addr[6:0] <= G_matrix_addr[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [63:0] G_matrix_rom_out;
|
||||
G_MATRIX_ROM_R12 G_MATRIX_ROM_R12 (
|
||||
.clka(clk),
|
||||
.addra(G_matrix_addr[6:0]),
|
||||
.douta(G_matrix_rom_out)
|
||||
);
|
||||
reg G_matrix_valid = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
G_matrix_valid <= 1'd0;
|
||||
else begin
|
||||
if(Encoder_Nd_d1)begin
|
||||
G_matrix_valid <= (cnt_din_d1[6:0] >= 7'd1 && cnt_din_d1[6:0] <= {2'd0,G_row_rd_clk_num[4:0]}) ? 1'd1 : 1'd0;
|
||||
end
|
||||
else
|
||||
G_matrix_valid <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [63:0] G_matrix_d01 = 64'd0;
|
||||
reg [63:0] G_matrix_d02 = 64'd0;
|
||||
reg [63:0] G_matrix_d03 = 64'd0;
|
||||
reg [63:0] G_matrix_d04 = 64'd0;
|
||||
reg [63:0] G_matrix_d05 = 64'd0;
|
||||
reg [63:0] G_matrix_d06 = 64'd0;
|
||||
reg [63:0] G_matrix_d07 = 64'd0;
|
||||
reg [63:0] G_matrix_d08 = 64'd0;
|
||||
reg [63:0] G_matrix_d09 = 64'd0;
|
||||
reg [63:0] G_matrix_d10 = 64'd0;
|
||||
reg [63:0] G_matrix_d11 = 64'd0;
|
||||
reg [63:0] G_matrix_d12 = 64'd0;
|
||||
reg [63:0] G_matrix_d13 = 64'd0;
|
||||
reg [63:0] G_matrix_d14 = 64'd0;
|
||||
reg [63:0] G_matrix_d15 = 64'd0;
|
||||
reg [63:0] G_matrix_d16 = 64'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
G_matrix_d01[63:0] <= 64'd0;
|
||||
G_matrix_d02[63:0] <= 64'd0;
|
||||
G_matrix_d03[63:0] <= 64'd0;
|
||||
G_matrix_d04[63:0] <= 64'd0;
|
||||
G_matrix_d05[63:0] <= 64'd0;
|
||||
G_matrix_d06[63:0] <= 64'd0;
|
||||
G_matrix_d07[63:0] <= 64'd0;
|
||||
G_matrix_d08[63:0] <= 64'd0;
|
||||
G_matrix_d09[63:0] <= 64'd0;
|
||||
G_matrix_d10[63:0] <= 64'd0;
|
||||
G_matrix_d11[63:0] <= 64'd0;
|
||||
G_matrix_d12[63:0] <= 64'd0;
|
||||
G_matrix_d13[63:0] <= 64'd0;
|
||||
G_matrix_d14[63:0] <= 64'd0;
|
||||
G_matrix_d15[63:0] <= 64'd0;
|
||||
G_matrix_d16[63:0] <= 64'd0;
|
||||
end
|
||||
else begin
|
||||
if(G_matrix_valid)begin
|
||||
G_matrix_d01[63:0] <= G_matrix_rom_out[63:0];
|
||||
G_matrix_d02[63:0] <= G_matrix_d01[63:0] ;
|
||||
G_matrix_d03[63:0] <= G_matrix_d02[63:0] ;
|
||||
G_matrix_d04[63:0] <= G_matrix_d03[63:0] ;
|
||||
G_matrix_d05[63:0] <= G_matrix_d04[63:0] ;
|
||||
G_matrix_d06[63:0] <= G_matrix_d05[63:0] ;
|
||||
G_matrix_d07[63:0] <= G_matrix_d06[63:0] ;
|
||||
G_matrix_d08[63:0] <= G_matrix_d07[63:0] ;
|
||||
G_matrix_d09[63:0] <= G_matrix_d08[63:0] ;
|
||||
G_matrix_d10[63:0] <= G_matrix_d09[63:0] ;
|
||||
G_matrix_d11[63:0] <= G_matrix_d10[63:0] ;
|
||||
G_matrix_d12[63:0] <= G_matrix_d11[63:0] ;
|
||||
G_matrix_d13[63:0] <= G_matrix_d12[63:0] ;
|
||||
G_matrix_d14[63:0] <= G_matrix_d13[63:0] ;
|
||||
G_matrix_d15[63:0] <= G_matrix_d14[63:0] ;
|
||||
G_matrix_d16[63:0] <= G_matrix_d15[63:0] ;
|
||||
end
|
||||
else begin
|
||||
G_matrix_d01[63:0] <= G_matrix_d01[63:0];
|
||||
G_matrix_d02[63:0] <= G_matrix_d02[63:0];
|
||||
G_matrix_d03[63:0] <= G_matrix_d03[63:0];
|
||||
G_matrix_d04[63:0] <= G_matrix_d04[63:0];
|
||||
G_matrix_d05[63:0] <= G_matrix_d05[63:0];
|
||||
G_matrix_d06[63:0] <= G_matrix_d06[63:0];
|
||||
G_matrix_d07[63:0] <= G_matrix_d07[63:0];
|
||||
G_matrix_d08[63:0] <= G_matrix_d08[63:0];
|
||||
G_matrix_d09[63:0] <= G_matrix_d09[63:0];
|
||||
G_matrix_d10[63:0] <= G_matrix_d10[63:0];
|
||||
G_matrix_d11[63:0] <= G_matrix_d11[63:0];
|
||||
G_matrix_d12[63:0] <= G_matrix_d12[63:0];
|
||||
G_matrix_d13[63:0] <= G_matrix_d13[63:0];
|
||||
G_matrix_d14[63:0] <= G_matrix_d14[63:0];
|
||||
G_matrix_d15[63:0] <= G_matrix_d15[63:0];
|
||||
G_matrix_d16[63:0] <= G_matrix_d16[63:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//矩阵一行有效
|
||||
reg G_matrix_row_valid = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
G_matrix_row_valid <= 1'd0;
|
||||
else begin
|
||||
G_matrix_row_valid <= (cnt_din_d2[6:0] == {2'd0,G_row_rd_clk_num[4:0]} && cnt_din_d2[10:0] > 11'd0) ? 1'd1 : 1'd0;
|
||||
end
|
||||
end
|
||||
//矩阵一行有效的同时计数,1/2与2/3分别计数128 64个时钟以指示编码有效
|
||||
reg [9:0] cnt_encode_valid = 10'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
cnt_encode_valid[9:0] <= 10'd0;
|
||||
else begin
|
||||
if(cnt_din_d2[6:0] == {2'd0,G_row_rd_clk_num[4:0]} && cnt_din_d2[10:0] > 11'd0)
|
||||
cnt_encode_valid[9:0] <= 10'd1;
|
||||
else if(cnt_encode_valid[9:0] >= 10'd1)
|
||||
cnt_encode_valid[9:0] <= (cnt_encode_valid[9:0] == 10'd128) ? 10'd0 : cnt_encode_valid[9:0] + 10'd1;
|
||||
else
|
||||
cnt_encode_valid[9:0] <= cnt_encode_valid[9:0];
|
||||
end
|
||||
end
|
||||
//编码有效
|
||||
reg encode_valid = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
encode_valid <= 1'd0;
|
||||
else begin
|
||||
if(cnt_encode_valid[9:0] != 10'd0)
|
||||
encode_valid <= 1'd1;
|
||||
else
|
||||
encode_valid <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [63:0] G_matrix_d01_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d02_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d03_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d04_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d05_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d06_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d07_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d08_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d09_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d10_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d11_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d12_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d13_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d14_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d15_tem = 64'd0;
|
||||
reg [63:0] G_matrix_d16_tem = 64'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
G_matrix_d01_tem[63:0] <= 64'd0;
|
||||
G_matrix_d02_tem[63:0] <= 64'd0;
|
||||
G_matrix_d03_tem[63:0] <= 64'd0;
|
||||
G_matrix_d04_tem[63:0] <= 64'd0;
|
||||
G_matrix_d05_tem[63:0] <= 64'd0;
|
||||
G_matrix_d06_tem[63:0] <= 64'd0;
|
||||
G_matrix_d07_tem[63:0] <= 64'd0;
|
||||
G_matrix_d08_tem[63:0] <= 64'd0;
|
||||
G_matrix_d09_tem[63:0] <= 64'd0;
|
||||
G_matrix_d10_tem[63:0] <= 64'd0;
|
||||
G_matrix_d11_tem[63:0] <= 64'd0;
|
||||
G_matrix_d12_tem[63:0] <= 64'd0;
|
||||
G_matrix_d13_tem[63:0] <= 64'd0;
|
||||
G_matrix_d14_tem[63:0] <= 64'd0;
|
||||
G_matrix_d15_tem[63:0] <= 64'd0;
|
||||
G_matrix_d16_tem[63:0] <= 64'd0;
|
||||
end
|
||||
else begin
|
||||
if(G_matrix_row_valid)begin
|
||||
G_matrix_d01_tem[63:0] <= G_matrix_d01[63:0];
|
||||
G_matrix_d02_tem[63:0] <= G_matrix_d02[63:0];
|
||||
G_matrix_d03_tem[63:0] <= G_matrix_d03[63:0];
|
||||
G_matrix_d04_tem[63:0] <= G_matrix_d04[63:0];
|
||||
G_matrix_d05_tem[63:0] <= G_matrix_d05[63:0];
|
||||
G_matrix_d06_tem[63:0] <= G_matrix_d06[63:0];
|
||||
G_matrix_d07_tem[63:0] <= G_matrix_d07[63:0];
|
||||
G_matrix_d08_tem[63:0] <= G_matrix_d08[63:0];
|
||||
G_matrix_d09_tem[63:0] <= G_matrix_d09[63:0];
|
||||
G_matrix_d10_tem[63:0] <= G_matrix_d10[63:0];
|
||||
G_matrix_d11_tem[63:0] <= G_matrix_d11[63:0];
|
||||
G_matrix_d12_tem[63:0] <= G_matrix_d12[63:0];
|
||||
G_matrix_d13_tem[63:0] <= G_matrix_d13[63:0];
|
||||
G_matrix_d14_tem[63:0] <= G_matrix_d14[63:0];
|
||||
G_matrix_d15_tem[63:0] <= G_matrix_d15[63:0];
|
||||
G_matrix_d16_tem[63:0] <= G_matrix_d16[63:0];
|
||||
end
|
||||
else begin
|
||||
G_matrix_d01_tem[63:0] <= {G_matrix_d02_tem[0],G_matrix_d01_tem[63:1]};
|
||||
G_matrix_d02_tem[63:0] <= {G_matrix_d01_tem[0],G_matrix_d02_tem[63:1]};
|
||||
G_matrix_d03_tem[63:0] <= {G_matrix_d04_tem[0],G_matrix_d03_tem[63:1]};
|
||||
G_matrix_d04_tem[63:0] <= {G_matrix_d03_tem[0],G_matrix_d04_tem[63:1]};
|
||||
G_matrix_d05_tem[63:0] <= {G_matrix_d06_tem[0],G_matrix_d05_tem[63:1]};
|
||||
G_matrix_d06_tem[63:0] <= {G_matrix_d05_tem[0],G_matrix_d06_tem[63:1]};
|
||||
G_matrix_d07_tem[63:0] <= {G_matrix_d08_tem[0],G_matrix_d07_tem[63:1]};
|
||||
G_matrix_d08_tem[63:0] <= {G_matrix_d07_tem[0],G_matrix_d08_tem[63:1]};
|
||||
G_matrix_d09_tem[63:0] <= {G_matrix_d10_tem[0],G_matrix_d09_tem[63:1]};
|
||||
G_matrix_d10_tem[63:0] <= {G_matrix_d09_tem[0],G_matrix_d10_tem[63:1]};
|
||||
G_matrix_d11_tem[63:0] <= {G_matrix_d12_tem[0],G_matrix_d11_tem[63:1]};
|
||||
G_matrix_d12_tem[63:0] <= {G_matrix_d11_tem[0],G_matrix_d12_tem[63:1]};
|
||||
G_matrix_d13_tem[63:0] <= {G_matrix_d14_tem[0],G_matrix_d13_tem[63:1]};
|
||||
G_matrix_d14_tem[63:0] <= {G_matrix_d13_tem[0],G_matrix_d14_tem[63:1]};
|
||||
G_matrix_d15_tem[63:0] <= {G_matrix_d16_tem[0],G_matrix_d15_tem[63:1]};
|
||||
G_matrix_d16_tem[63:0] <= {G_matrix_d15_tem[0],G_matrix_d16_tem[63:1]};
|
||||
end
|
||||
end
|
||||
end
|
||||
//存储编码结果
|
||||
reg [63:0] en_row_01 = 64'd0;
|
||||
reg [63:0] en_row_02 = 64'd0;
|
||||
reg [63:0] en_row_03 = 64'd0;
|
||||
reg [63:0] en_row_04 = 64'd0;
|
||||
reg [63:0] en_row_05 = 64'd0;
|
||||
reg [63:0] en_row_06 = 64'd0;
|
||||
reg [63:0] en_row_07 = 64'd0;
|
||||
reg [63:0] en_row_08 = 64'd0;
|
||||
reg [63:0] en_row_09 = 64'd0;
|
||||
reg [63:0] en_row_10 = 64'd0;
|
||||
reg [63:0] en_row_11 = 64'd0;
|
||||
reg [63:0] en_row_12 = 64'd0;
|
||||
reg [63:0] en_row_13 = 64'd0;
|
||||
reg [63:0] en_row_14 = 64'd0;
|
||||
reg [63:0] en_row_15 = 64'd0;
|
||||
reg [63:0] en_row_16 = 64'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst || Encoder_SyncIn)begin
|
||||
en_row_01[63:0] <= 64'd0;
|
||||
en_row_02[63:0] <= 64'd0;
|
||||
en_row_03[63:0] <= 64'd0;
|
||||
en_row_04[63:0] <= 64'd0;
|
||||
en_row_05[63:0] <= 64'd0;
|
||||
en_row_06[63:0] <= 64'd0;
|
||||
en_row_07[63:0] <= 64'd0;
|
||||
en_row_08[63:0] <= 64'd0;
|
||||
en_row_09[63:0] <= 64'd0;
|
||||
en_row_10[63:0] <= 64'd0;
|
||||
en_row_11[63:0] <= 64'd0;
|
||||
en_row_12[63:0] <= 64'd0;
|
||||
en_row_13[63:0] <= 64'd0;
|
||||
en_row_14[63:0] <= 64'd0;
|
||||
en_row_15[63:0] <= 64'd0;
|
||||
en_row_16[63:0] <= 64'd0;
|
||||
end
|
||||
else begin
|
||||
if(encode_valid)begin
|
||||
en_row_01[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d01_tem[63:0]) ^ en_row_01[63:0];
|
||||
en_row_02[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d02_tem[63:0]) ^ en_row_02[63:0];
|
||||
en_row_03[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d03_tem[63:0]) ^ en_row_03[63:0];
|
||||
en_row_04[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d04_tem[63:0]) ^ en_row_04[63:0];
|
||||
en_row_05[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d05_tem[63:0]) ^ en_row_05[63:0];
|
||||
en_row_06[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d06_tem[63:0]) ^ en_row_06[63:0];
|
||||
en_row_07[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d07_tem[63:0]) ^ en_row_07[63:0];
|
||||
en_row_08[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d08_tem[63:0]) ^ en_row_08[63:0];
|
||||
en_row_09[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d09_tem[63:0]) ^ en_row_09[63:0];
|
||||
en_row_10[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d10_tem[63:0]) ^ en_row_10[63:0];
|
||||
en_row_11[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d11_tem[63:0]) ^ en_row_11[63:0];
|
||||
en_row_12[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d12_tem[63:0]) ^ en_row_12[63:0];
|
||||
en_row_13[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d13_tem[63:0]) ^ en_row_13[63:0];
|
||||
en_row_14[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d14_tem[63:0]) ^ en_row_14[63:0];
|
||||
en_row_15[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d15_tem[63:0]) ^ en_row_15[63:0];
|
||||
en_row_16[63:0] <= ({64{Encoder_Din_d19}} & G_matrix_d16_tem[63:0]) ^ en_row_16[63:0];
|
||||
end
|
||||
else begin
|
||||
en_row_01[63:0] <= en_row_01[63:0];
|
||||
en_row_02[63:0] <= en_row_02[63:0];
|
||||
en_row_03[63:0] <= en_row_03[63:0];
|
||||
en_row_04[63:0] <= en_row_04[63:0];
|
||||
en_row_05[63:0] <= en_row_05[63:0];
|
||||
en_row_06[63:0] <= en_row_06[63:0];
|
||||
en_row_07[63:0] <= en_row_07[63:0];
|
||||
en_row_08[63:0] <= en_row_08[63:0];
|
||||
en_row_09[63:0] <= en_row_09[63:0];
|
||||
en_row_10[63:0] <= en_row_10[63:0];
|
||||
en_row_11[63:0] <= en_row_11[63:0];
|
||||
en_row_12[63:0] <= en_row_12[63:0];
|
||||
en_row_13[63:0] <= en_row_13[63:0];
|
||||
en_row_14[63:0] <= en_row_14[63:0];
|
||||
en_row_15[63:0] <= en_row_15[63:0];
|
||||
en_row_16[63:0] <= en_row_16[63:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//将译码结果输出
|
||||
wire encode_out;
|
||||
wire encode_sync_out;
|
||||
wire encode_rdy;
|
||||
Out_Process_R12 Out_Process_R12(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
.encode_din(Out_Info_bit),
|
||||
.encode_valid(encode_valid),
|
||||
.check_clk_num(check_clk_num[10:0]),
|
||||
|
||||
.en_row_01(en_row_01[63:0]),
|
||||
.en_row_02(en_row_02[63:0]),
|
||||
.en_row_03(en_row_03[63:0]),
|
||||
.en_row_04(en_row_04[63:0]),
|
||||
.en_row_05(en_row_05[63:0]),
|
||||
.en_row_06(en_row_06[63:0]),
|
||||
.en_row_07(en_row_07[63:0]),
|
||||
.en_row_08(en_row_08[63:0]),
|
||||
.en_row_09(en_row_09[63:0]),
|
||||
.en_row_10(en_row_10[63:0]),
|
||||
.en_row_11(en_row_11[63:0]),
|
||||
.en_row_12(en_row_12[63:0]),
|
||||
.en_row_13(en_row_13[63:0]),
|
||||
.en_row_14(en_row_14[63:0]),
|
||||
.en_row_15(en_row_15[63:0]),
|
||||
.en_row_16(en_row_16[63:0]),
|
||||
|
||||
.encode_out(encode_out),
|
||||
.encode_sync_out(encode_sync_out),
|
||||
.encode_rdy(encode_rdy)
|
||||
);
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
Encode_Dout <= 1'd0;
|
||||
Encode_Rdy <= 1'd0;
|
||||
Encode_Sync_Dout <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
Encode_Dout <= encode_out;
|
||||
Encode_Rdy <= encode_rdy;
|
||||
Encode_Sync_Dout <= encode_sync_out;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,126 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module MagnitudeEstimator #(
|
||||
parameter VEC_WIDTH = 21
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input vec_valid,
|
||||
input [VEC_WIDTH-1:0] I,
|
||||
input [VEC_WIDTH-1:0] Q,
|
||||
(* max_fanout=128 *) output reg [ VEC_WIDTH:0] mag, // width is larger than I & Q
|
||||
(* max_fanout=128 *) output reg mag_valid
|
||||
);
|
||||
|
||||
// input complex vector, calc the magnitude
|
||||
// first calc the abs
|
||||
// compare the I and Q
|
||||
// calc the Mag
|
||||
// Mag ~=Alpha * max(|I|, |Q|) + Beta * min(|I|, |Q|)
|
||||
// * 61/64, 3/8
|
||||
// * mag = max - max/64 - max/32 + min/8 + min/4
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
reg [VEC_WIDTH-1:0] abs_i;
|
||||
reg [VEC_WIDTH-1:0] abs_q;
|
||||
reg [VEC_WIDTH-1:0] max;
|
||||
reg [VEC_WIDTH-1:0] min;
|
||||
|
||||
reg [VEC_WIDTH-1:0] max_component1;
|
||||
reg [VEC_WIDTH-1:0] max_component2;
|
||||
reg [VEC_WIDTH-1:0] max_component3;
|
||||
reg [VEC_WIDTH-1:0] min_component1;
|
||||
reg [VEC_WIDTH-1:0] min_component2;
|
||||
reg [VEC_WIDTH-1:0] min_component3;
|
||||
reg [VEC_WIDTH-1:0] max_res;
|
||||
reg [VEC_WIDTH-1:0] min_res;
|
||||
|
||||
reg vec_valid_d1;
|
||||
reg vec_valid_d2;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
abs_i <= 'd0;
|
||||
abs_q <= 'd0;
|
||||
end
|
||||
else begin
|
||||
if (vec_valid) begin
|
||||
abs_i <= (I[VEC_WIDTH-1] == 1'b1) ? -I : I;
|
||||
abs_q <= (Q[VEC_WIDTH-1] == 1'b1) ? -Q : Q;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
max <= 'd0;
|
||||
min <= 'd0;
|
||||
max_component1 <= 'd0;
|
||||
max_component2 <= 'd0;
|
||||
max_component3 <= 'd0;
|
||||
min_component1 <= 'd0;
|
||||
min_component2 <= 'd0;
|
||||
min_component3 <= 'd0;
|
||||
max_res <= 'd0;
|
||||
min_res <= 'd0;
|
||||
end
|
||||
else begin
|
||||
if (abs_i < abs_q) begin
|
||||
max <= abs_q;
|
||||
min <= abs_i;
|
||||
end
|
||||
else begin
|
||||
max <= abs_i;
|
||||
min <= abs_q;
|
||||
end
|
||||
// TODO: 修改为无符号数
|
||||
max_component1 <= max;
|
||||
max_component2 <= {6'd0, max[VEC_WIDTH-1:6]};
|
||||
max_component3 <= {5'd0, max[VEC_WIDTH-1:5]};
|
||||
min_component1 <= {3'd0, min[VEC_WIDTH-1:3]};
|
||||
min_component2 <= {2'd0, min[VEC_WIDTH-1:2]};
|
||||
// min_component3 <= ;
|
||||
max_res <= max_component1 - max_component2 - max_component3;
|
||||
min_res <= min_component1 + min_component2;
|
||||
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// * mag = max - max/64 - max/32 + min/8 + min/4
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
mag <= 'd0;
|
||||
end
|
||||
else begin
|
||||
mag <= max_res + min_res;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
vec_valid_d1 <= 1'd0;
|
||||
vec_valid_d2 <= 1'd0;
|
||||
mag_valid <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
vec_valid_d1 <= vec_valid;
|
||||
vec_valid_d2 <= vec_valid_d1;
|
||||
mag_valid <= vec_valid_d2;
|
||||
end
|
||||
end
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,212 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/01/18 15:02:10
|
||||
// Design Name:
|
||||
// Module Name: Out_Process_R12
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Out_Process_R12(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input encode_din, //将输入信息比特输出
|
||||
input encode_valid, //下降沿表示完成码字计算
|
||||
input [10:0] check_clk_num, //校验比特个数
|
||||
|
||||
input [63:0] en_row_01,
|
||||
input [63:0] en_row_02,
|
||||
input [63:0] en_row_03,
|
||||
input [63:0] en_row_04,
|
||||
input [63:0] en_row_05,
|
||||
input [63:0] en_row_06,
|
||||
input [63:0] en_row_07,
|
||||
input [63:0] en_row_08,
|
||||
input [63:0] en_row_09,
|
||||
input [63:0] en_row_10,
|
||||
input [63:0] en_row_11,
|
||||
input [63:0] en_row_12,
|
||||
input [63:0] en_row_13,
|
||||
input [63:0] en_row_14,
|
||||
input [63:0] en_row_15,
|
||||
input [63:0] en_row_16,
|
||||
|
||||
output reg encode_out = 1'd0,
|
||||
output reg encode_sync_out = 1'd0,
|
||||
output reg encode_rdy = 1'd0
|
||||
);
|
||||
reg encode_valid_d1 = 1'd0; reg encode_valid_d2 = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
encode_valid_d1 <= 1'd0;
|
||||
encode_valid_d2 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
encode_valid_d1 <= encode_valid;
|
||||
encode_valid_d2 <= encode_valid_d1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [10:0] cycle_out_cnt = 11'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
cycle_out_cnt[10:0] <= 11'd0;
|
||||
else begin
|
||||
if(encode_valid_d1 && !encode_valid)
|
||||
cycle_out_cnt[10:0] <= 11'd1;
|
||||
else begin
|
||||
if(cycle_out_cnt[10:0] >= 11'd1)
|
||||
cycle_out_cnt[10:0] <= (cycle_out_cnt[10:0] == check_clk_num[10:0]) ? 11'd0 : cycle_out_cnt[10:0] + 11'd1;
|
||||
else
|
||||
cycle_out_cnt[10:0] <= 11'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg cycle_out_en = 1'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
cycle_out_en <= 1'd0;
|
||||
else begin
|
||||
if(cycle_out_cnt[10:0] >= 11'd1)
|
||||
cycle_out_en <= 1'd1;
|
||||
else
|
||||
cycle_out_en <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [63:0] en_row_01_tem = 64'd0;
|
||||
reg [63:0] en_row_02_tem = 64'd0;
|
||||
reg [63:0] en_row_03_tem = 64'd0;
|
||||
reg [63:0] en_row_04_tem = 64'd0;
|
||||
reg [63:0] en_row_05_tem = 64'd0;
|
||||
reg [63:0] en_row_06_tem = 64'd0;
|
||||
reg [63:0] en_row_07_tem = 64'd0;
|
||||
reg [63:0] en_row_08_tem = 64'd0;
|
||||
reg [63:0] en_row_09_tem = 64'd0;
|
||||
reg [63:0] en_row_10_tem = 64'd0;
|
||||
reg [63:0] en_row_11_tem = 64'd0;
|
||||
reg [63:0] en_row_12_tem = 64'd0;
|
||||
reg [63:0] en_row_13_tem = 64'd0;
|
||||
reg [63:0] en_row_14_tem = 64'd0;
|
||||
reg [63:0] en_row_15_tem = 64'd0;
|
||||
reg [63:0] en_row_16_tem = 64'd0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
en_row_01_tem[63:0] <= 64'd0;
|
||||
en_row_02_tem[63:0] <= 64'd0;
|
||||
en_row_03_tem[63:0] <= 64'd0;
|
||||
en_row_04_tem[63:0] <= 64'd0;
|
||||
en_row_05_tem[63:0] <= 64'd0;
|
||||
en_row_06_tem[63:0] <= 64'd0;
|
||||
en_row_07_tem[63:0] <= 64'd0;
|
||||
en_row_08_tem[63:0] <= 64'd0;
|
||||
en_row_09_tem[63:0] <= 64'd0;
|
||||
en_row_10_tem[63:0] <= 64'd0;
|
||||
en_row_11_tem[63:0] <= 64'd0;
|
||||
en_row_12_tem[63:0] <= 64'd0;
|
||||
en_row_13_tem[63:0] <= 64'd0;
|
||||
en_row_14_tem[63:0] <= 64'd0;
|
||||
en_row_15_tem[63:0] <= 64'd0;
|
||||
en_row_16_tem[63:0] <= 64'd0;
|
||||
end
|
||||
else begin
|
||||
if(cycle_out_cnt[10:0] == 11'd1)begin
|
||||
en_row_01_tem[63:0] <= en_row_01[63:0];
|
||||
en_row_02_tem[63:0] <= en_row_02[63:0];
|
||||
en_row_03_tem[63:0] <= en_row_03[63:0];
|
||||
en_row_04_tem[63:0] <= en_row_04[63:0];
|
||||
en_row_05_tem[63:0] <= en_row_05[63:0];
|
||||
en_row_06_tem[63:0] <= en_row_06[63:0];
|
||||
en_row_07_tem[63:0] <= en_row_07[63:0];
|
||||
en_row_08_tem[63:0] <= en_row_08[63:0];
|
||||
en_row_09_tem[63:0] <= en_row_09[63:0];
|
||||
en_row_10_tem[63:0] <= en_row_10[63:0];
|
||||
en_row_11_tem[63:0] <= en_row_11[63:0];
|
||||
en_row_12_tem[63:0] <= en_row_12[63:0];
|
||||
en_row_13_tem[63:0] <= en_row_13[63:0];
|
||||
en_row_14_tem[63:0] <= en_row_14[63:0];
|
||||
en_row_15_tem[63:0] <= en_row_15[63:0];
|
||||
en_row_16_tem[63:0] <= en_row_16[63:0];
|
||||
end
|
||||
else if(cycle_out_en)begin
|
||||
en_row_16_tem[63:0] <= {en_row_16_tem[62:0],en_row_15_tem[63]};
|
||||
en_row_15_tem[63:0] <= {en_row_15_tem[62:0],en_row_14_tem[63]};
|
||||
en_row_14_tem[63:0] <= {en_row_14_tem[62:0],en_row_13_tem[63]};
|
||||
en_row_13_tem[63:0] <= {en_row_13_tem[62:0],en_row_12_tem[63]};
|
||||
en_row_12_tem[63:0] <= {en_row_12_tem[62:0],en_row_11_tem[63]};
|
||||
en_row_11_tem[63:0] <= {en_row_11_tem[62:0],en_row_10_tem[63]};
|
||||
en_row_10_tem[63:0] <= {en_row_10_tem[62:0],en_row_09_tem[63]};
|
||||
en_row_09_tem[63:0] <= {en_row_09_tem[62:0],en_row_08_tem[63]};
|
||||
en_row_08_tem[63:0] <= {en_row_08_tem[62:0],en_row_07_tem[63]};
|
||||
en_row_07_tem[63:0] <= {en_row_07_tem[62:0],en_row_06_tem[63]};
|
||||
en_row_06_tem[63:0] <= {en_row_06_tem[62:0],en_row_05_tem[63]};
|
||||
en_row_05_tem[63:0] <= {en_row_05_tem[62:0],en_row_04_tem[63]};
|
||||
en_row_04_tem[63:0] <= {en_row_04_tem[62:0],en_row_03_tem[63]};
|
||||
en_row_03_tem[63:0] <= {en_row_03_tem[62:0],en_row_02_tem[63]};
|
||||
en_row_02_tem[63:0] <= {en_row_02_tem[62:0],en_row_01_tem[63]};
|
||||
en_row_01_tem[63:0] <= {en_row_01_tem[62:0],1'd0};
|
||||
end
|
||||
else begin
|
||||
en_row_01_tem[63:0] <= 64'd0;
|
||||
en_row_02_tem[63:0] <= 64'd0;
|
||||
en_row_03_tem[63:0] <= 64'd0;
|
||||
en_row_04_tem[63:0] <= 64'd0;
|
||||
en_row_05_tem[63:0] <= 64'd0;
|
||||
en_row_06_tem[63:0] <= 64'd0;
|
||||
en_row_07_tem[63:0] <= 64'd0;
|
||||
en_row_08_tem[63:0] <= 64'd0;
|
||||
en_row_09_tem[63:0] <= 64'd0;
|
||||
en_row_10_tem[63:0] <= 64'd0;
|
||||
en_row_11_tem[63:0] <= 64'd0;
|
||||
en_row_12_tem[63:0] <= 64'd0;
|
||||
en_row_13_tem[63:0] <= 64'd0;
|
||||
en_row_14_tem[63:0] <= 64'd0;
|
||||
en_row_15_tem[63:0] <= 64'd0;
|
||||
en_row_16_tem[63:0] <= 64'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
encode_out <= 1'd0;
|
||||
else begin
|
||||
if(cycle_out_en)begin
|
||||
encode_out <= en_row_16_tem[63];
|
||||
end
|
||||
else
|
||||
encode_out <= encode_din;
|
||||
end
|
||||
end
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
encode_rdy <= 1'd0;
|
||||
encode_sync_out <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if(encode_valid_d1 && !encode_valid_d2)
|
||||
encode_sync_out <= 1'd1;
|
||||
else
|
||||
encode_sync_out <= 1'd0;
|
||||
|
||||
encode_rdy <= encode_valid_d2 || cycle_out_en;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
+168
@@ -0,0 +1,168 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// +------------------------------+
|
||||
// | |
|
||||
// | |
|
||||
// +---------+------------> shift_ram(depth=1024) +-------------------+
|
||||
// | | | |
|
||||
// | | | |
|
||||
// | +------------------------------+ |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// | +------------+ |
|
||||
// | + | | - |
|
||||
// | | sliding | |
|
||||
// | | window | |
|
||||
// +---------------------> <----------------------------+
|
||||
// | |
|
||||
// +-----+------+
|
||||
// |
|
||||
// | average_out
|
||||
// |
|
||||
// v
|
||||
|
||||
module PAPR #(
|
||||
parameter MAG_WIDTH = 22,
|
||||
parameter WINDOW_DEPTH = 1023
|
||||
// parameter GATE = 8
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input [MAG_WIDTH-1:0] vec_mag,
|
||||
input mag_valid,
|
||||
output reg frame_sync,
|
||||
output reg frame_sync_pulse
|
||||
);
|
||||
|
||||
localparam SUM_WIDTH = 32;
|
||||
|
||||
reg mag_valid_d1;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d1;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d2;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d3;
|
||||
reg frame_sync_d1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
mag_valid_d1 <= mag_valid;
|
||||
if (rst) begin
|
||||
vec_mag_d1 <= 'd0;
|
||||
vec_mag_d2 <= 'd0;
|
||||
vec_mag_d3 <= 'd0;
|
||||
end
|
||||
else if (mag_valid) begin
|
||||
vec_mag_d1 <= vec_mag;
|
||||
vec_mag_d2 <= vec_mag_d1;
|
||||
vec_mag_d3 <= vec_mag_d2;
|
||||
end
|
||||
else begin
|
||||
vec_mag_d1 <= vec_mag_d1;
|
||||
vec_mag_d2 <= vec_mag_d2;
|
||||
vec_mag_d3 <= vec_mag_d3;
|
||||
end
|
||||
end
|
||||
// accumulate ==> average ==> papr
|
||||
wire [MAG_WIDTH-1:0] vec_mag_1024;
|
||||
reg [ 5:0] cnt;
|
||||
// shift_1024 shift_1024 (
|
||||
// .D (vec_mag), // input wire [21 : 0] D
|
||||
// .CLK(clk), // input wire CLK
|
||||
// .Q (vec_mag_1024) // output wire [21 : 0] Q
|
||||
// );
|
||||
|
||||
shift_reg #(
|
||||
.DATA_WIDTH(MAG_WIDTH),
|
||||
.DEPTH (WINDOW_DEPTH)
|
||||
) u_shift_reg (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.we (mag_valid),
|
||||
.din (vec_mag),
|
||||
.dout(vec_mag_1024)
|
||||
);
|
||||
|
||||
|
||||
reg [SUM_WIDTH-1:0] data_sum;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_sum <= 'd0;
|
||||
end
|
||||
else begin
|
||||
if (mag_valid) begin
|
||||
data_sum <= data_sum + vec_mag - vec_mag_1024;
|
||||
end
|
||||
else begin
|
||||
data_sum <= data_sum;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [MAG_WIDTH-1:0] data_avg;
|
||||
assign data_avg = data_sum[SUM_WIDTH-1:10];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
frame_sync <= 1'd0;
|
||||
end
|
||||
else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
|
||||
// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
|
||||
if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
|
||||
frame_sync <= 1'd1;
|
||||
end
|
||||
else if (cnt == 6'b111111) begin
|
||||
frame_sync <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
frame_sync <= frame_sync;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
frame_sync <= frame_sync;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
frame_sync_d1 <= frame_sync;
|
||||
if (frame_sync && ~frame_sync_d1) begin
|
||||
frame_sync_pulse <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
frame_sync_pulse <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 6'd0;
|
||||
end
|
||||
else if (frame_sync && mag_valid_d1) begin
|
||||
cnt <= cnt + 6'd1;
|
||||
end
|
||||
else if (cnt == 6'b111111) begin
|
||||
cnt <= 6'd0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
// NOTE: comment
|
||||
|
||||
ila_frame_sync u_ila_frame_sync (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(vec_mag), // input wire [21:0] probe0
|
||||
.probe1(mag_valid), // input wire [0:0] probe1
|
||||
.probe2(frame_sync) // input wire [0:0] probe2
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+320
@@ -0,0 +1,320 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module Receiver (
|
||||
input clk,
|
||||
input clk_2x,
|
||||
input clk_4x,
|
||||
input rst,
|
||||
input [ 2:0] speed_mode,
|
||||
input [11:0] ad9361_rx_data_i,
|
||||
input [11:0] ad9361_rx_data_q,
|
||||
output frame_sync_pulse // in domain clk
|
||||
);
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
// reg [23:0] mf_data_d1; // clk_4x
|
||||
// reg [23:0] mf_data_d2; // clk_4x
|
||||
|
||||
// wire rst_4x; // NOTE: HIGH FANOUT to be fixed
|
||||
reg [11:0] mf_data_i;
|
||||
reg [11:0] mf_data_q;
|
||||
|
||||
reg [20:0] dmf_data_i;
|
||||
reg [20:0] dmf_data_q;
|
||||
wire [23:0] dmf_tdata_interp4_i;
|
||||
wire [23:0] dmf_tdata_interp4_q;
|
||||
wire [23:0] dmf_tdata_interp16_i;
|
||||
wire [23:0] dmf_tdata_interp16_q;
|
||||
|
||||
reg dmf_tvalid;
|
||||
wire dmf_tvalid_interp4_i;
|
||||
wire dmf_tvalid_interp4_q;
|
||||
wire dmf_tvalid_interp16_i;
|
||||
wire dmf_tvalid_interp16_q;
|
||||
wire dmf_ready;
|
||||
wire [31:0] mf_data_interp16_i;
|
||||
wire [31:0] mf_data_interp16_q;
|
||||
wire [31:0] mf_data_interp4_i;
|
||||
wire [31:0] mf_data_interp4_q;
|
||||
wire [21:0] mag;
|
||||
wire mag_valid;
|
||||
|
||||
wire frame_sync;
|
||||
|
||||
wire fifo_out_valid;
|
||||
reg [ 2:0] cnt_fifo_out_valid;
|
||||
reg [ 2:0] cnt_fifo_out_valid_sel; // 根据speed mode对应的计数器边界值
|
||||
|
||||
wire [31:0] fifo_out;
|
||||
reg dmf_s_valid;
|
||||
reg [ 8:0] cnt_startup;
|
||||
wire startup;
|
||||
wire startup_4x;
|
||||
wire frame_sync_4x;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign startup = (cnt_startup == 9'd511);
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_startup <= 9'd0;
|
||||
end
|
||||
else if (cnt_startup < 9'd511) begin
|
||||
cnt_startup <= cnt_startup + 8'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// valid signal for dmf
|
||||
always @(posedge clk_4x) begin
|
||||
if (rst) begin
|
||||
dmf_s_valid <= 1'd0;
|
||||
end
|
||||
else if (startup_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin
|
||||
dmf_s_valid <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
dmf_s_valid <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_4x) begin
|
||||
if (rst) begin
|
||||
cnt_fifo_out_valid <= 3'd0;
|
||||
end
|
||||
else if (fifo_out_valid) begin
|
||||
if (cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin
|
||||
cnt_fifo_out_valid <= 3'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_fifo_out_valid <= cnt_fifo_out_valid + 3'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_fifo_out_valid <= cnt_fifo_out_valid;
|
||||
end
|
||||
end
|
||||
|
||||
// speed mode select
|
||||
always @(*) begin
|
||||
case (speed_mode)
|
||||
3'd0: begin // 16
|
||||
mf_data_i = mf_data_interp16_i[31-:12];
|
||||
mf_data_q = mf_data_interp16_q[31-:12];
|
||||
dmf_data_i = dmf_tdata_interp16_i[20:0];
|
||||
dmf_data_q = dmf_tdata_interp16_q[20:0];
|
||||
dmf_tvalid = dmf_tvalid_interp16_i;
|
||||
cnt_fifo_out_valid_sel = 3'd7;
|
||||
end
|
||||
// 3'd1: begin // 8
|
||||
// end
|
||||
3'd2: begin // 4
|
||||
mf_data_i = mf_data_interp4_i[29-:12];
|
||||
mf_data_q = mf_data_interp4_q[29-:12];
|
||||
dmf_data_i = dmf_tdata_interp4_i[20:0];
|
||||
dmf_data_q = dmf_tdata_interp4_q[20:0];
|
||||
dmf_tvalid = dmf_tvalid_interp4_i;
|
||||
cnt_fifo_out_valid_sel = 3'd1;
|
||||
end
|
||||
// 3'd3: begin // 2
|
||||
// end
|
||||
default: begin
|
||||
mf_data_i = mf_data_interp16_i[31-:12];
|
||||
mf_data_q = mf_data_interp16_q[31-:12];
|
||||
dmf_data_i = dmf_tdata_interp16_i[20:0];
|
||||
dmf_data_q = dmf_tdata_interp16_q[20:0];
|
||||
dmf_tvalid = dmf_tvalid_interp16_i;
|
||||
cnt_fifo_out_valid_sel = 3'd7;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
xpm_cdc_sync_rst #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization
|
||||
// registers to 1
|
||||
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) xpm_cdc_sync_rst_inst (
|
||||
.dest_rst(rst_4x), // 1-bit output: src_rst synchronized to the destination clock domain. This output
|
||||
// is registered.
|
||||
.dest_clk(clk_4x), // 1-bit input: Destination clock.
|
||||
.src_rst (rst) // 1-bit input: Source reset signal.
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// match filter
|
||||
// fir_match_interp16 u_fir_match_filter_interp16_i (
|
||||
// .aclk (clk), // input wire aclk
|
||||
// .s_axis_data_tvalid(startup), // input wire s_axis_data_tvalid
|
||||
// .s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
// .s_axis_data_tdata ({4'd0, ad9361_rx_data_i}), // input wire [15 : 0] s_axis_data_tdata
|
||||
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
// .m_axis_data_tdata (mf_data_interp16_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
// );
|
||||
// fir_match_interp16 u_fir_match_filter_interp16_q (
|
||||
// .aclk (clk), // input wire aclk
|
||||
// .s_axis_data_tvalid(startup), // input wire s_axis_data_tvalid
|
||||
// .s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
// .s_axis_data_tdata ({4'd0, ad9361_rx_data_q}), // input wire [15 : 0] s_axis_data_tdata
|
||||
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
// .m_axis_data_tdata (mf_data_interp16_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
// );
|
||||
|
||||
fir_match_interp4 u_fir_match_filter_interp4_i (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(startup), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, ad9361_rx_data_i}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
fir_match_interp4 u_fir_match_filter_interp4_q (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(startup), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, ad9361_rx_data_q}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
// TODO: 削峰
|
||||
fifo_shift u_fifo_shift (
|
||||
// input
|
||||
.s_aclk (clk), // input wire s_aclk
|
||||
.s_aresetn (startup), // input wire s_aresetn
|
||||
.s_axis_tvalid(startup), // input wire s_axis_tvalid
|
||||
.s_axis_tready(), // output wire s_axis_tready
|
||||
.s_axis_tdata ({8'd0, mf_data_q, mf_data_i}), // input wire [31 : 0] s_axis_tdata
|
||||
// output
|
||||
.m_aclk (clk_4x), // input wire m_aclk
|
||||
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
|
||||
.m_axis_tready(1'b1), // input wire m_axis_tready
|
||||
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
|
||||
.wr_rst_busy (),
|
||||
.rd_rst_busy ()
|
||||
);
|
||||
|
||||
// TODO: dmf根据不同的速率挡位来选择不同的内插值的fir滤波器
|
||||
|
||||
// NOTE: 编写关于抽取的滤波器设计相关文档
|
||||
// dmf filter
|
||||
// fir_dmf_interp16 u_fir_dmf_interp16_i (
|
||||
// .aclk (clk_4x), // input wire aclk
|
||||
// .s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
|
||||
// .s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
// .s_axis_data_tdata ({4'd0, fifo_out[11:0]}), // input wire [15 : 0] s_axis_data_tdata
|
||||
// .m_axis_data_tvalid(dmf_tvalid_interp16_i), // output wire m_axis_data_tvalid
|
||||
// .m_axis_data_tdata (dmf_tdata_interp16_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
// );
|
||||
|
||||
// fir_dmf_interp16 u_fir_dmf_interp16_q (
|
||||
// .aclk (clk_4x), // input wire aclk
|
||||
// .s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
|
||||
// .s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
// .s_axis_data_tdata ({4'd0, fifo_out[23:12]}), // input wire [15 : 0] s_axis_data_tdata
|
||||
// .m_axis_data_tvalid(dmf_tvalid_interp16_q), // output wire m_axis_data_tvalid
|
||||
// .m_axis_data_tdata (dmf_tdata_interp16_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
// );
|
||||
|
||||
fir_dmf_interp4 u_fir_dmf_interp4_i (
|
||||
.aclk (clk_4x),
|
||||
.s_axis_data_tvalid(dmf_s_valid),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
|
||||
.m_axis_data_tvalid(dmf_tvalid_interp4_i),
|
||||
.m_axis_data_tdata (dmf_tdata_interp4_i)
|
||||
);
|
||||
|
||||
fir_dmf_interp4 u_fir_dmf_interp4_q (
|
||||
.aclk (clk_4x),
|
||||
.s_axis_data_tvalid(dmf_s_valid),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
|
||||
.m_axis_data_tvalid(dmf_tvalid_interp4_q),
|
||||
.m_axis_data_tdata (dmf_tdata_interp4_q)
|
||||
);
|
||||
|
||||
|
||||
|
||||
MagnitudeEstimator #(
|
||||
.VEC_WIDTH(21)
|
||||
) u_MagnitudeEstimator (
|
||||
.clk (clk_4x),
|
||||
.rst (rst),
|
||||
.vec_valid(dmf_tvalid),
|
||||
.I (dmf_data_i),
|
||||
.Q (dmf_data_q),
|
||||
.mag (mag),
|
||||
.mag_valid(mag_valid)
|
||||
);
|
||||
|
||||
PAPR #(
|
||||
.MAG_WIDTH (22),
|
||||
.WINDOW_DEPTH(1023)
|
||||
) u_PAPR (
|
||||
.clk (clk_4x),
|
||||
.rst (rst),
|
||||
.vec_mag (mag),
|
||||
.mag_valid (mag_valid),
|
||||
.frame_sync (frame_sync_4x),
|
||||
.frame_sync_pulse()
|
||||
);
|
||||
|
||||
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
||||
) xpm_cdc_startup_inst (
|
||||
.dest_out(startup_4x), // 1-bit output: src_in synchronized to the destination clock domain. This output is
|
||||
// registered.
|
||||
.dest_clk(clk_4x), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (startup) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
|
||||
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) xpm_cdc_frame_sync_pulse_inst (
|
||||
.dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
|
||||
// transfer is correctly initiated on src_pulse input. This output is
|
||||
// combinatorial unless REG_OUTPUT is set to 1.
|
||||
.dest_clk (clk), // 1-bit input: Destination clock.
|
||||
.dest_rst (), // 1-bit input: optional; required when RST_USED = 1
|
||||
.src_clk (clk_4x), // 1-bit input: Source clock.
|
||||
.src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
|
||||
// destination clock domain. The minimum gap between each pulse transfer must be
|
||||
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
|
||||
// between the falling edge of a src_pulse to the rising edge of the next
|
||||
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
|
||||
// will generate a pulse the size of one dest_clk period in the destination
|
||||
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
|
||||
// src_rst and/or dest_rst are asserted.
|
||||
.src_rst () // 1-bit input: optional; required when RST_USED = 1
|
||||
);
|
||||
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,551 @@
|
||||
`timescale 1ns / 1ns
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Create Date: 2023/12/18
|
||||
// * Update Date: 2024/03/17
|
||||
|
||||
// NOTE: 接口中的hop_wait和参数GAP_LEN均是为了等待，hop是为了跳频切换，gap是为了满足帧同步延迟,！！！将hop_wait设置为0并不能去掉改状态
|
||||
module Transmitter #(
|
||||
parameter AGC_HEADER_LEN = 2130,
|
||||
parameter FRAME_HEADER_LEN = 512,
|
||||
parameter BLOCK_NUM = 28,
|
||||
parameter PHASE1_LEN = 2112, // (8 cp + 256 sym)* 8 ( total 2048 valid sym)
|
||||
parameter PREFIX_LEN = 8,
|
||||
parameter CHU_SEQ_LEN = 128,
|
||||
parameter GAP_LEN = 160
|
||||
) (
|
||||
// general
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
// control
|
||||
input wire [ 2:0] speed_mode,
|
||||
input wire send_data_ready,
|
||||
input wire send_start,
|
||||
output reg send_over,
|
||||
// data
|
||||
// source data from others
|
||||
output wire clk_data_src,
|
||||
input wire [31:0] tx_data_src_tdata,
|
||||
output reg tx_data_src_tready,
|
||||
input wire tx_data_src_tvalid,
|
||||
|
||||
output reg [ 3:0] hopping_freq,
|
||||
output wire [11:0] ad9361_tx_data_i,
|
||||
output wire [11:0] ad9361_tx_data_q,
|
||||
input wire test,
|
||||
// param from ps
|
||||
input wire [15:0] hop_wait // this is the gap between 2 blocks freq (unit in clk period)
|
||||
);
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
reg [15:0] cnt_agc_send; // agc symbols have been sent
|
||||
reg [15:0] cnt_sym_send; // symbols have been sent
|
||||
reg [15:0] cnt_blocks_send; // blocks have been sent
|
||||
reg [15:0] cnt_wait; // wait cnt max 65535 period, 50M -> 1.3ms
|
||||
reg [15:0] cnt_chu_send;
|
||||
// fsm
|
||||
reg [ 3:0] cs;
|
||||
reg [ 3:0] ns;
|
||||
localparam [3:0] S_IDLE = 4'd0;
|
||||
localparam [3:0] S_SEND_AGC = 4'd1;
|
||||
localparam [3:0] S_SEND_FRAME_HEADER = 4'd2;
|
||||
localparam [3:0] S_SEND_CHU_POS = 4'd8;
|
||||
localparam [3:0] S_SEND_CHU_NEG = 4'd9;
|
||||
localparam [3:0] S_SEND_PHASE1 = 4'd3;
|
||||
localparam [3:0] S_WAIT_HOP = 4'd5;
|
||||
localparam [3:0] S_WAIT_GAP = 4'd6; // wait for freq switch
|
||||
localparam [3:0] S_TEST = 4'd7;
|
||||
|
||||
reg [ 3:0] interp;
|
||||
reg [ 3:0] cnt_interp;
|
||||
reg [ 8:0] mseqs_addr;
|
||||
reg [ 8:0] mseqs_addr_d1;
|
||||
reg [ 8:0] mseqs_addr_d2;
|
||||
reg [ 6:0] chu_seq_addr;
|
||||
wire [31:0] chu_seq;
|
||||
wire mseqs;
|
||||
reg [31:0] bb_wave_out_i; // shape filter result
|
||||
reg [31:0] bb_wave_out_q; // shape filter result
|
||||
wire [31:0] bb_wave_out_i_interp16;
|
||||
wire [31:0] bb_wave_out_q_interp16;
|
||||
wire [31:0] bb_wave_out_i_interp8;
|
||||
wire [31:0] bb_wave_out_q_interp8;
|
||||
wire [31:0] bb_wave_out_i_interp4;
|
||||
wire [31:0] bb_wave_out_q_interp4;
|
||||
wire fir_tvalid_in; // shape filter input valid
|
||||
wire hand_shake; // not used
|
||||
reg [15:0] m_fir_tdata_i;
|
||||
reg [15:0] m_fir_tdata_q;
|
||||
reg [ 3:0] rtz; // return to zero
|
||||
|
||||
reg [12:0] addr_tx_test = 'd0;
|
||||
wire [7:0] data_tx_test;
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign clk_data_src = clk;
|
||||
assign fir_tvalid_in = (cnt_interp == interp);
|
||||
assign hand_shake = tx_data_src_tvalid && tx_data_src_tready; // not used
|
||||
|
||||
assign ad9361_tx_data_i = bb_wave_out_i[31-:12];
|
||||
assign ad9361_tx_data_q = bb_wave_out_q[31-:12];
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// fsm
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cs <= S_IDLE;
|
||||
end
|
||||
else begin
|
||||
cs <= ns;
|
||||
end
|
||||
end
|
||||
// state transition
|
||||
always @(*) begin
|
||||
case (cs)
|
||||
S_IDLE: begin
|
||||
if (send_start) begin
|
||||
ns = S_SEND_AGC;
|
||||
end
|
||||
else if (test) begin
|
||||
ns = S_TEST;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
S_SEND_AGC: begin
|
||||
if (cnt_sym_send == AGC_HEADER_LEN - 1 && fir_tvalid_in) begin
|
||||
ns = S_SEND_FRAME_HEADER;
|
||||
end
|
||||
else begin
|
||||
ns = S_SEND_AGC;
|
||||
end
|
||||
end
|
||||
|
||||
S_SEND_FRAME_HEADER: begin
|
||||
if (cnt_sym_send == FRAME_HEADER_LEN - 1 && fir_tvalid_in) begin
|
||||
`ifdef TX_FRAME_WITH_GAP
|
||||
ns = S_WAIT_GAP;
|
||||
`else
|
||||
ns = S_SEND_CHU_POS;
|
||||
`endif
|
||||
end
|
||||
else begin
|
||||
ns = S_SEND_FRAME_HEADER;
|
||||
end
|
||||
end
|
||||
|
||||
S_WAIT_GAP: begin
|
||||
if (cnt_wait == GAP_LEN - 1) begin
|
||||
ns = S_SEND_CHU_POS;
|
||||
end
|
||||
else begin
|
||||
ns = S_WAIT_GAP;
|
||||
end
|
||||
end
|
||||
|
||||
S_SEND_CHU_POS: begin
|
||||
if (cnt_chu_send == CHU_SEQ_LEN + PREFIX_LEN - 1 && fir_tvalid_in) begin
|
||||
ns = S_SEND_CHU_NEG;
|
||||
end
|
||||
else begin
|
||||
ns = S_SEND_CHU_POS;
|
||||
end
|
||||
end
|
||||
|
||||
S_SEND_CHU_NEG: begin
|
||||
if (cnt_chu_send == CHU_SEQ_LEN + PREFIX_LEN - 1 && fir_tvalid_in) begin
|
||||
ns = S_SEND_PHASE1;
|
||||
end
|
||||
else begin
|
||||
ns = S_SEND_CHU_NEG;
|
||||
end
|
||||
end
|
||||
|
||||
S_SEND_PHASE1: begin
|
||||
if (cnt_sym_send == PHASE1_LEN - 1 && fir_tvalid_in) begin
|
||||
// send block num - 1 and send the final block
|
||||
if (cnt_blocks_send == BLOCK_NUM) begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
else begin
|
||||
`ifdef TX_FRAME_WITH_GAP
|
||||
ns = S_WAIT_HOP;
|
||||
`else
|
||||
ns = S_SEND_CHU_POS;
|
||||
`endif
|
||||
end
|
||||
end
|
||||
else begin
|
||||
ns = S_SEND_PHASE1;
|
||||
end
|
||||
end
|
||||
|
||||
S_WAIT_HOP: begin
|
||||
if (cnt_wait == hop_wait - 1) begin
|
||||
ns = S_SEND_CHU_POS;
|
||||
end
|
||||
else begin
|
||||
ns = S_WAIT_HOP;
|
||||
end
|
||||
end
|
||||
|
||||
S_TEST: begin
|
||||
if (~test) begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
else begin
|
||||
ns = S_TEST;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// speed mode select
|
||||
always @(*) begin
|
||||
case (speed_mode)
|
||||
3'd0: begin
|
||||
interp = 4'd15; // 16
|
||||
bb_wave_out_i = bb_wave_out_i_interp16;
|
||||
bb_wave_out_q = bb_wave_out_q_interp16;
|
||||
end
|
||||
3'd1: begin
|
||||
interp = 4'd7; // 8
|
||||
bb_wave_out_i = bb_wave_out_i_interp8;
|
||||
bb_wave_out_q = bb_wave_out_q_interp8;
|
||||
end
|
||||
3'd2: begin
|
||||
interp = 4'd3; // 4
|
||||
bb_wave_out_i = bb_wave_out_i_interp4;
|
||||
bb_wave_out_q = bb_wave_out_q_interp4;
|
||||
end
|
||||
// 3'd3: begin
|
||||
// interp = 4'd1; // 2
|
||||
// end
|
||||
default: begin
|
||||
interp = 4'd15;
|
||||
bb_wave_out_i = bb_wave_out_i_interp16;
|
||||
bb_wave_out_q = bb_wave_out_q_interp16;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// tx_data_src_tready for handshake
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_data_src_tready <= 1'd0;
|
||||
end
|
||||
// only when the phase 1 state , the transmitter will receive the data from outside(axis protocal)
|
||||
else if (cs == S_SEND_PHASE1) begin
|
||||
if (!tx_data_src_tready && tx_data_src_tvalid) begin // no handshake
|
||||
if (fir_tvalid_in) begin
|
||||
tx_data_src_tready <= 1'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
tx_data_src_tready <= 1'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
tx_data_src_tready <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// interpolation counter
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_interp <= 4'd0;
|
||||
end
|
||||
else if (cs == S_IDLE && rtz == 4'd0) begin
|
||||
cnt_interp <= 4'd0;
|
||||
end
|
||||
else if (cs == S_SEND_AGC || cs == S_SEND_FRAME_HEADER || cs == S_SEND_PHASE1 || cs == S_SEND_CHU_POS || cs == S_SEND_CHU_NEG || cs == S_TEST || rtz > 4'd0) begin
|
||||
if (cnt_interp < interp) begin
|
||||
cnt_interp <= cnt_interp + 4'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_interp <= 4'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_interp <= 4'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// return to zero
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rtz <= 4'd0;
|
||||
end
|
||||
else if (cs == S_SEND_AGC || cs == S_SEND_FRAME_HEADER || cs == S_SEND_PHASE1 || cs == S_SEND_CHU_POS || cs == S_SEND_CHU_NEG || cs == S_TEST) begin
|
||||
if (ns == S_WAIT_HOP || ns == S_WAIT_GAP || ns == S_IDLE) begin
|
||||
rtz <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
rtz <= 4'd0;
|
||||
end
|
||||
end
|
||||
else if (fir_tvalid_in) begin
|
||||
if (rtz == 4'd7) begin
|
||||
rtz <= 4'd0;
|
||||
end
|
||||
else begin
|
||||
rtz <= rtz + 4'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//cnt_sym_send
|
||||
always @(posedge clk) begin
|
||||
if (rst || ns != cs) begin
|
||||
cnt_sym_send <= 16'd0;
|
||||
end
|
||||
else if (cs == S_SEND_AGC || cs == S_SEND_FRAME_HEADER || cs == S_SEND_PHASE1 || cs == S_TEST) begin
|
||||
if (fir_tvalid_in) begin
|
||||
cnt_sym_send <= cnt_sym_send + 16'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_sym_send <= cnt_sym_send;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_sym_send <= 16'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// truncation
|
||||
always @(*) begin
|
||||
if (cs == S_SEND_FRAME_HEADER) begin
|
||||
m_fir_tdata_i = mseqs ? 16'h8001 : 16'h7FFF;
|
||||
m_fir_tdata_q = mseqs ? 16'h8001 : 16'h7FFF;
|
||||
end
|
||||
else if (cs == S_SEND_PHASE1) begin
|
||||
m_fir_tdata_i = tx_data_src_tdata[15-:16];
|
||||
m_fir_tdata_q = tx_data_src_tdata[31-:16];
|
||||
end
|
||||
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC) begin
|
||||
m_fir_tdata_i = chu_seq[15-:16];
|
||||
m_fir_tdata_q = chu_seq[31-:16];
|
||||
end
|
||||
else if (cs == S_SEND_CHU_NEG) begin
|
||||
m_fir_tdata_i = -chu_seq[15-:16];
|
||||
m_fir_tdata_q = -chu_seq[31-:16];
|
||||
end
|
||||
else if (cs == S_TEST) begin
|
||||
m_fir_tdata_i = {data_tx_test[3:0], 12'b0};
|
||||
m_fir_tdata_q = {data_tx_test[7:4], 12'b0};
|
||||
end
|
||||
else begin
|
||||
m_fir_tdata_i = 16'd0;
|
||||
m_fir_tdata_q = 16'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// count the block have been sent
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_blocks_send <= 4'd0;
|
||||
end
|
||||
else if (cs != S_SEND_PHASE1 && ns == S_SEND_PHASE1) begin
|
||||
cnt_blocks_send <= cnt_blocks_send + 4'd1;
|
||||
end
|
||||
else if (cs == S_IDLE) begin
|
||||
cnt_blocks_send <= 4'd0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// S_WAIT_HOP && S_WAIT_GAP
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_wait <= 16'd0;
|
||||
end
|
||||
else if (cs == S_WAIT_HOP) begin
|
||||
if (cnt_wait == hop_wait) begin
|
||||
cnt_wait <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_wait <= cnt_wait + 16'd1;
|
||||
end
|
||||
end
|
||||
else if (cs == S_WAIT_GAP) begin
|
||||
if (cnt_wait == GAP_LEN - 1) begin
|
||||
cnt_wait <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_wait <= cnt_wait + 16'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_wait <= 16'd0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_SEND_PHASE1 && ns == S_IDLE) begin
|
||||
send_over <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
send_over <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// m seq addr control
|
||||
always @(posedge clk) begin
|
||||
mseqs_addr_d1 <= mseqs_addr;
|
||||
mseqs_addr_d2 <= mseqs_addr_d1;
|
||||
if (cs == S_IDLE) begin
|
||||
mseqs_addr <= 1'd0;
|
||||
end
|
||||
else if (cs == S_SEND_FRAME_HEADER || cs == S_TEST) begin
|
||||
if (fir_tvalid_in == 1'b1) begin
|
||||
mseqs_addr <= mseqs_addr + 9'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// chu seq addr control
|
||||
always @(posedge clk) begin
|
||||
if (ns != cs) begin
|
||||
// chu_seq_addr <= 7'h7F - 7'h7; // 8 cp
|
||||
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 8 cp
|
||||
end
|
||||
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC || cs == S_SEND_CHU_NEG) begin
|
||||
if (fir_tvalid_in == 1'b1) begin
|
||||
chu_seq_addr <= chu_seq_addr + 9'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs != ns) begin
|
||||
cnt_chu_send <= 0;
|
||||
end
|
||||
else if (cs == S_SEND_CHU_POS || cs == S_SEND_CHU_NEG) begin
|
||||
if (fir_tvalid_in) begin
|
||||
cnt_chu_send <= cnt_chu_send + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_chu_send <= cnt_chu_send;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_chu_send <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (fir_tvalid_in) begin
|
||||
addr_tx_test <= addr_tx_test + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
bram_m_seqs_512 u_bram_m_seqs_512 (
|
||||
.clka (clk),
|
||||
.addra(mseqs_addr),
|
||||
.douta(mseqs)
|
||||
);
|
||||
|
||||
|
||||
bram_chu_seq u_bram_chu_seq (
|
||||
.clka (clk), // input wire clka
|
||||
.addra(chu_seq_addr), // input wire [6 : 0] addra
|
||||
.douta(chu_seq) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
|
||||
bram_tx_test u_bram_tx_test (
|
||||
.clka (clk), // input wire clka
|
||||
.addra(addr_tx_test), // input wire [17 : 0] addra
|
||||
.douta(data_tx_test) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
|
||||
// fir i & q
|
||||
fir_shape_interp16 u_fir_shape_interp16_i (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(fir_tvalid_in), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (m_fir_tdata_i), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (bb_wave_out_i_interp16) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
|
||||
fir_shape_interp16 u_fir_shape_interp16_q (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_q),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_q_interp16)
|
||||
);
|
||||
|
||||
fir_shape_interp8 u_fir_shape_interp8_i (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_i),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_i_interp8)
|
||||
);
|
||||
|
||||
fir_shape_interp8 u_fir_shape_interp8_q (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_q),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_q_interp8)
|
||||
);
|
||||
|
||||
fir_shape_interp4 u_fir_shape_interp4_i (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_i),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_i_interp4)
|
||||
);
|
||||
|
||||
fir_shape_interp4 u_fir_shape_interp4_q (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_q),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_q_interp4)
|
||||
);
|
||||
|
||||
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
ila_transmitter u_ila_transmitter (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(cnt_sym_send), // input wire [15:0] probe0
|
||||
.probe1(cs), // input wire [3:0] probe1
|
||||
.probe2(ns), // input wire [3:0] probe2
|
||||
.probe3(send_data_ready), // input wire [0:0] probe3
|
||||
.probe4(send_start), // input wire [0:0] probe4
|
||||
.probe5(tx_data_src_tvalid) // input wire [0:0] probe5
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,109 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer: liu yongxin
|
||||
//
|
||||
// Create Date: 08/23/2022 11:58:14 AM
|
||||
// Design Name:
|
||||
// Module Name: ad9361_dp_fdd_1r1t
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: ad9361 degital port config - FDD, 1R1T, Dual Port, DDR
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_dp_fdd_1r1t (
|
||||
// Receive
|
||||
input rx_clk,
|
||||
input [11:0] rx_data,
|
||||
input rx_frame,
|
||||
output [11:0] rx_data_i,
|
||||
output [11:0] rx_data_q,
|
||||
output rx_frame_i,
|
||||
output rx_frame_q,
|
||||
// Transmit
|
||||
input tx_clk,
|
||||
input [11:0] tx_data_i,
|
||||
input [11:0] tx_data_q,
|
||||
output [11:0] tx_data,
|
||||
output tx_frame
|
||||
);
|
||||
|
||||
// rx data
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 12; i = i + 1) begin : rx_data_iddr
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT_Q1 (1'b0),
|
||||
.INIT_Q2 (1'b0),
|
||||
.SRTYPE ("ASYNC")
|
||||
) rx_data_iddr_inst (
|
||||
.CE(1'b1),
|
||||
.R (1'b0),
|
||||
.S (1'b0),
|
||||
.C (rx_clk),
|
||||
.D (rx_data[i]),
|
||||
.Q1(rx_data_q[i]),
|
||||
.Q2(rx_data_i[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
// rx frame
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT_Q1 (1'b0),
|
||||
.INIT_Q2 (1'b0),
|
||||
.SRTYPE ("ASYNC")
|
||||
) i_rx_frame_iddr (
|
||||
.CE(1'b1),
|
||||
.R (1'b0),
|
||||
.S (1'b0),
|
||||
.C (rx_clk),
|
||||
.D (rx_frame),
|
||||
.Q1(rx_frame_q),
|
||||
.Q2(rx_frame_i)
|
||||
);
|
||||
|
||||
// tx data
|
||||
generate
|
||||
for (i = 0; i < 12; i = i + 1) begin : tx_data_oddr
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT (1'b0),
|
||||
.SRTYPE ("ASYNC")
|
||||
) tx_data_oddr_inst (
|
||||
.CE(1'b1),
|
||||
.R (1'b0),
|
||||
.S (1'b0),
|
||||
.C (tx_clk),
|
||||
.D1(tx_data_i[i]),
|
||||
.D2(tx_data_q[i]),
|
||||
.Q (tx_data[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
// tx frame
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT (1'b0),
|
||||
.SRTYPE ("ASYNC")
|
||||
) i_tx_frame_oddr (
|
||||
.CE(1'b1),
|
||||
.R (1'b0),
|
||||
.S (1'b0),
|
||||
.C (tx_clk),
|
||||
.D1(1'b0),
|
||||
.D2(1'b1),
|
||||
.Q (tx_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,155 @@
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Update Date: 2024年7月12日
|
||||
// * NOTE : after test , the pin control pulse effect take palce
|
||||
// * NOTE : after about 50 clocks. so re-measuring the energy
|
||||
// * NOTE : after more than 50 clocks is ok. Here I choose 100 clocks(25 syms)
|
||||
|
||||
|
||||
module ad9361_mgc_pin_ctrl (
|
||||
input clk,
|
||||
input rst,
|
||||
// input start,
|
||||
input [11:0] rx_data_i,
|
||||
input [11:0] rx_data_q,
|
||||
// this port is from zynq to ad9361
|
||||
output wire [ 3:0] ad9361_ctrl_in
|
||||
|
||||
);
|
||||
|
||||
// * CTRL_IN0 causes the gain index to increase for Rx1
|
||||
// * CTRL_IN1 causes the gain index to decrease for Rx1
|
||||
|
||||
localparam PULSE_PERIOD = 5;
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
wire start;
|
||||
reg start_d1;
|
||||
wire start_posedge;
|
||||
wire inc_pulse;
|
||||
wire dec_pulse;
|
||||
wire flag_too_high; // high amplitude
|
||||
wire flag_too_low; // low amplitude
|
||||
wire flag_adjust;
|
||||
reg [3:0] cnt_pulse_width;
|
||||
|
||||
// adjust fsm
|
||||
localparam S_IDLE = 0;
|
||||
localparam S_INC = 1;
|
||||
localparam S_DEC = 2;
|
||||
localparam S_DONE = 3;
|
||||
reg [2:0] cs;
|
||||
reg [2:0] ns;
|
||||
|
||||
// ******** Assingment ********
|
||||
assign ad9361_ctrl_in[0] = inc_pulse;
|
||||
assign ad9361_ctrl_in[1] = dec_pulse;
|
||||
|
||||
assign flag_adjust = flag_too_high | flag_too_low;
|
||||
assign inc_pulse = (cs == S_INC);
|
||||
assign dec_pulse = (cs == S_DEC);
|
||||
|
||||
assign start_posedge = start & ~start_d1;
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// self decrese cnt
|
||||
always @(posedge clk) begin
|
||||
if (flag_adjust) begin
|
||||
cnt_pulse_width = PULSE_PERIOD;
|
||||
end
|
||||
else if (cnt_pulse_width > 0) begin
|
||||
cnt_pulse_width <= cnt_pulse_width - 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
start_d1 <= start;
|
||||
end
|
||||
|
||||
|
||||
// FSM
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cs <= S_IDLE;
|
||||
end
|
||||
else begin
|
||||
cs <= ns;
|
||||
end
|
||||
end
|
||||
|
||||
// fsm for dec and inc
|
||||
always @(*) begin
|
||||
case (cs)
|
||||
S_IDLE: begin
|
||||
if (flag_too_high) begin
|
||||
ns = S_DEC;
|
||||
end
|
||||
else if (flag_too_low) begin
|
||||
ns = S_INC;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_INC: begin
|
||||
if (cnt_pulse_width == 0) begin
|
||||
ns = S_DONE;
|
||||
end
|
||||
end
|
||||
S_DEC: begin
|
||||
if (cnt_pulse_width == 0) begin
|
||||
ns = S_DONE;
|
||||
end
|
||||
end
|
||||
S_DONE: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// measuring the signal power
|
||||
// two cases, amplitute too high or amplitude too low
|
||||
power_measure u_power_measure (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.start (start_posedge),
|
||||
.data_i (rx_data_i),
|
||||
.data_q (rx_data_q),
|
||||
.flag_too_high(flag_too_high),
|
||||
.flag_too_low (flag_too_low)
|
||||
);
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
vio_mgc_control_in u_vio_mgc_control_in (
|
||||
.clk (clk), // input wire clk
|
||||
.probe_out0(start) // output wire [0 : 0] probe_out0
|
||||
);
|
||||
|
||||
ila_ad9361_mgc u_ila_ad9361_mgc (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(start_posedge), // input wire [0:0] probe0
|
||||
.probe1(rx_data_i), // input wire [11:0] probe1
|
||||
.probe2(u_power_measure.cs), // input wire [2:0] probe2
|
||||
.probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
|
||||
.probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
|
||||
.probe5(flag_too_high), // input wire [0:0] probe5
|
||||
.probe6(flag_too_low), // input wire [0:0] probe6
|
||||
.probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
|
||||
.probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,52 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2023/11/14 16:20:11
|
||||
// Design Name:
|
||||
// Module Name: ad9361_spi_interface
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_spi_interface (
|
||||
input ad9361_spi_miso,
|
||||
output ad9361_spi_csn,
|
||||
output ad9361_spi_clk,
|
||||
output ad9361_spi_mosi,
|
||||
// spi interface
|
||||
input spi_sclk,
|
||||
input [1:0] spi_cs,
|
||||
output reg spi_sdi,
|
||||
input spi_sdo,
|
||||
input spi_sdo_t,
|
||||
input spi_three_wire,
|
||||
input spi_active
|
||||
);
|
||||
|
||||
// ad9361 - three-wire spi or four-wire spi
|
||||
assign ad9361_spi_clk = spi_sclk;
|
||||
assign ad9361_spi_csn = spi_cs[1];
|
||||
assign ad9361_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
|
||||
// select sdi signal
|
||||
always @(*) begin
|
||||
if (~ad9361_spi_csn) spi_sdi = spi_three_wire ? ad9361_spi_mosi : ad9361_spi_miso;
|
||||
else spi_sdi = 1'bz;
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,158 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module add_prefix #(
|
||||
//! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
|
||||
parameter WIDTH = 2,
|
||||
parameter DATA_LEN = 256,
|
||||
parameter PREFIX_LEN = 8
|
||||
) (
|
||||
input clk,
|
||||
input start,
|
||||
output reg ready,
|
||||
input [WIDTH-1:0] data_in,
|
||||
output reg data_in_ready,
|
||||
output reg [WIDTH-1:0] data_out,
|
||||
output reg data_out_valid
|
||||
);
|
||||
|
||||
localparam CNT_WIDTH = $clog2(DATA_LEN);
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
wire [ WIDTH-1:0] shift_out;
|
||||
reg [CNT_WIDTH : 0] cnt_in;
|
||||
reg [ CNT_WIDTH:0] cnt_out;
|
||||
|
||||
reg [ 2:0] cs = 0;
|
||||
reg [ 2:0] ns = 0;
|
||||
|
||||
localparam [2:0] S_IDLE = 0;
|
||||
localparam [2:0] S_IN = 1;
|
||||
localparam [2:0] S_OUT = 2;
|
||||
|
||||
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
cs <= ns;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (cs)
|
||||
S_IDLE: begin
|
||||
if (start) begin
|
||||
ns = S_IN;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
S_IN: begin
|
||||
if (cnt_in == DATA_LEN - PREFIX_LEN - 1) begin
|
||||
ns = S_OUT;
|
||||
end
|
||||
else begin
|
||||
ns = S_IN;
|
||||
end
|
||||
end
|
||||
|
||||
S_OUT: begin
|
||||
if (cnt_out == DATA_LEN + PREFIX_LEN - 1) begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
else begin
|
||||
ns = S_OUT;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// module ready to receive new packet
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IDLE && ~start) begin
|
||||
ready <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
ready <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// counts the data in
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IN || cnt_in < DATA_LEN - 1 && cnt_in > 0) begin
|
||||
cnt_in <= cnt_in + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_in <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin
|
||||
data_in_ready <= 1'b1;
|
||||
end
|
||||
else if (cnt_in == DATA_LEN - 1 || cs == S_IDLE) begin
|
||||
data_in_ready <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_OUT) begin
|
||||
cnt_out <= cnt_out + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_out <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_OUT) begin
|
||||
if (cnt_out < PREFIX_LEN) begin
|
||||
data_out <= data_in;
|
||||
end
|
||||
else begin
|
||||
data_out <= shift_out;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
data_out <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_OUT) begin
|
||||
data_out_valid <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
data_out_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
shift256_8 u_shift256_8 (
|
||||
.CLK(clk), // input wire CLK
|
||||
.D (data_in), // input wire [31 : 0] D
|
||||
.Q (shift_out) // output wire [31 : 0] Q
|
||||
);
|
||||
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,341 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
// *******************************************************
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// *******************************************************
|
||||
// * this module get data from the ps ( a axis-fifo in fact)
|
||||
// * and then use the ldpc algorithm to encode the data, which
|
||||
// * is 16 bit parallel, then it dose a width convert to
|
||||
// * 2 bit (i and q) , add a prefix which is 8 sym len. finally,
|
||||
// * send the data with prefix to a fifo (2 bit width, ditributed ram),
|
||||
// * waiting the transmitter to fetch
|
||||
// *
|
||||
// * later update (2024/5/14):
|
||||
// * we find the 16bit parallel cost too much resource, so we change it
|
||||
// * to 1bit serial module,
|
||||
// * 该模块首先将输入的数据32bit数据进行位宽转换为1bit数据，输入到ldpc模块中进行编码
|
||||
// * 然后将ldpc模块通过fifo进行位宽转换成2bit数据（Q，I），然后添加循环前缀（8个符号）
|
||||
// * 送入到fifo_enc_out中，并结束。
|
||||
// *
|
||||
// * Q : 何时开始编码？
|
||||
// * A : 前端有数据下发，且该模块是输出fifo模块中数据不足（<200syms)才进行编码。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
module enc_control #(
|
||||
parameter ENC_IN_LEN = 1024,
|
||||
parameter ENC_OUT_LEN = 2048,
|
||||
parameter INPUT_DATA_WIDTH = 32
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
//from ps axis-fifo
|
||||
input s_axis_fifo_tvalid,
|
||||
output reg s_axis_fifo_tready,
|
||||
input [INPUT_DATA_WIDTH - 1:0] s_axis_fifo_tdata,
|
||||
input [ 31:0] data_src_count,
|
||||
// fifo signal
|
||||
input wire fifo_enc_out_rd_clk,
|
||||
input wire fifo_enc_out_rd_en,
|
||||
output wire [ 31:0] fifo_enc_out_dout_map,
|
||||
output wire fifo_enc_out_empty
|
||||
);
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
localparam CNT_IN_MAX = ENC_IN_LEN / INPUT_DATA_WIDTH;
|
||||
localparam CNT_IN_WIDTH = $clog2(CNT_IN_MAX);
|
||||
localparam CNT_OUT_MAX = ENC_OUT_LEN;
|
||||
localparam CNT_OUT_WIDTH = $clog2(CNT_OUT_MAX); // 多留1bit
|
||||
|
||||
// status
|
||||
localparam [3:0] S_IDLE = 4'd0;
|
||||
localparam [3:0] S_START = 4'd1;
|
||||
localparam [3:0] S_WAIT_LDPC_OUT = 4'd2;
|
||||
localparam [3:0] S_WAIT_ADD_PREFIX_DONE = 4'd3;
|
||||
|
||||
reg [ 3:0] cs;
|
||||
reg [ 3:0] ns;
|
||||
|
||||
// input data width convert
|
||||
reg wc_data_in_valid;
|
||||
wire wc_data_in_ready;
|
||||
wire [ 31:0] wc_data_in;
|
||||
wire wc_data_out_valid;
|
||||
wire wc_data_out;
|
||||
|
||||
// ldpc io signal
|
||||
reg ldpc_in_start;
|
||||
reg ldpc_in_valid;
|
||||
wire ldpc_out_start;
|
||||
wire ldpc_out_valid;
|
||||
wire ldpc_dout;
|
||||
|
||||
// ldpc io cnt
|
||||
reg [ CNT_IN_WIDTH : 0] cnt_in; // 多留1bit
|
||||
reg [CNT_OUT_WIDTH : 0] cnt_out; // 多留1bit
|
||||
|
||||
// map
|
||||
wire [ 1:0] fifo_enc_out_dout;
|
||||
wire [ 15:0] fifo_enc_out_dout_i;
|
||||
wire [ 15:0] fifo_enc_out_dout_q;
|
||||
wire fifo_enc_out_almost_empty;
|
||||
wire fifo_enc_out_prog_empty_1x; // 20 sym
|
||||
wire fifo_enc_out_prog_empty; // 20 sym
|
||||
|
||||
// control the fifo width convert read channel
|
||||
wire fifo_wc_prog_full;
|
||||
reg fifo_wc_prog_full_d1;
|
||||
wire fifo_wc_empty;
|
||||
reg add_prefix_start;
|
||||
|
||||
// signal for add_prefix
|
||||
reg [ 2:0] cnt_add_prefix_in;
|
||||
wire add_prefix_in_ready;
|
||||
wire [ 1:0] data_add_prefix_in;
|
||||
wire data_add_prefix_in_ready;
|
||||
wire [ 1:0] data_add_prefix_out;
|
||||
wire data_add_prefix_out_valid;
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign fifo_enc_out_dout_i = (fifo_enc_out_dout[0] == 1'b0) ? 16'h7FFF : 16'h8001;
|
||||
assign fifo_enc_out_dout_q = (fifo_enc_out_dout[1] == 1'b0) ? 16'h7FFF : 16'h8001;
|
||||
assign fifo_enc_out_dout_map = {fifo_enc_out_dout_q, fifo_enc_out_dout_i};
|
||||
assign wc_data_in = s_axis_fifo_tdata;
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst == 1'b1) begin
|
||||
cs <= S_IDLE;
|
||||
end
|
||||
else begin
|
||||
cs <= ns;
|
||||
end
|
||||
end
|
||||
|
||||
// fsm
|
||||
always @(*) begin
|
||||
// NOTE: S_IDLE --> START (width convert --> encoding module) --> wait output done --> IDLE
|
||||
case (cs)
|
||||
S_IDLE: begin
|
||||
// ! attention
|
||||
// if source is valid which means there are data waiting for encoding
|
||||
// and the pre-stage fifo counts not equal 0
|
||||
// and the width convert fifo is empty
|
||||
// and the finally stage fifo is almost empty
|
||||
// TODO:check the conditions, done 2024年5月27日
|
||||
if (s_axis_fifo_tvalid && data_src_count != 0 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
|
||||
ns = S_START;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
S_START: begin
|
||||
ns = S_WAIT_LDPC_OUT;
|
||||
end
|
||||
|
||||
S_WAIT_LDPC_OUT: begin
|
||||
if (cnt_out == CNT_OUT_MAX) begin
|
||||
ns = S_WAIT_ADD_PREFIX_DONE;
|
||||
end
|
||||
else begin
|
||||
ns = S_WAIT_LDPC_OUT;
|
||||
end
|
||||
end
|
||||
|
||||
S_WAIT_ADD_PREFIX_DONE: begin
|
||||
if (fifo_wc_empty && add_prefix_in_ready) begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
else begin
|
||||
ns = S_WAIT_ADD_PREFIX_DONE;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
wc_data_in_valid <= 0;
|
||||
end
|
||||
else if (ns == S_START || cnt_in < CNT_IN_MAX && cs != S_IDLE) begin
|
||||
wc_data_in_valid <= s_axis_fifo_tvalid;
|
||||
end
|
||||
else begin
|
||||
wc_data_in_valid <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (rst) begin
|
||||
s_axis_fifo_tready = 0;
|
||||
end
|
||||
else begin
|
||||
if (cs != S_IDLE && cnt_in < CNT_IN_MAX) begin
|
||||
s_axis_fifo_tready = wc_data_in_ready;
|
||||
end
|
||||
else begin
|
||||
s_axis_fifo_tready = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
ldpc_in_start = (cs == S_START);
|
||||
ldpc_in_valid = wc_data_out_valid;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IDLE) begin
|
||||
cnt_in <= 0;
|
||||
end
|
||||
else if (wc_data_in_ready && wc_data_in_valid) begin
|
||||
cnt_in <= cnt_in + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ldpc_out_start || cnt_out > 0 && cnt_out <= CNT_OUT_MAX) begin
|
||||
cnt_out <= cnt_out + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_out <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// get the rising edge
|
||||
always @(posedge clk) begin
|
||||
fifo_wc_prog_full_d1 <= fifo_wc_prog_full;
|
||||
end
|
||||
|
||||
// shit code, no modify timing is in a mess
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_add_prefix_in <= 0;
|
||||
end
|
||||
else if (fifo_wc_prog_full & ~fifo_wc_prog_full_d1) begin
|
||||
cnt_add_prefix_in <= cnt_add_prefix_in + 1;
|
||||
end
|
||||
else if (add_prefix_start) begin
|
||||
if (cnt_add_prefix_in < 4) begin
|
||||
cnt_add_prefix_in <= cnt_add_prefix_in + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_add_prefix_in <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
add_prefix_start <= 0;
|
||||
end
|
||||
else if (fifo_wc_prog_full & ~fifo_wc_prog_full_d1 || cnt_add_prefix_in > 0 && add_prefix_in_ready && ~add_prefix_start) begin
|
||||
add_prefix_start <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
add_prefix_start <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
width_convert #(
|
||||
.INPUT_WIDTH (32),
|
||||
.OUTPUT_WIDTH(1)
|
||||
) u_width_convert (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.data_in_valid (wc_data_in_valid),
|
||||
.data_in_ready (wc_data_in_ready),
|
||||
.data_in (wc_data_in),
|
||||
.data_out_valid(wc_data_out_valid),
|
||||
.data_out (wc_data_out)
|
||||
);
|
||||
|
||||
|
||||
// encoding module
|
||||
CCSDS_LDPC_ENC_R12 u_CCSDS_LDPC_ENC_R12 (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.Encoder_SyncIn (ldpc_in_start),
|
||||
.Encoder_Nd (ldpc_in_valid),
|
||||
.Encoder_Din (wc_data_out),
|
||||
.Encode_Dout (ldpc_dout),
|
||||
.Encode_Sync_Dout(ldpc_out_start),
|
||||
.Encode_Rdy (ldpc_out_valid)
|
||||
);
|
||||
|
||||
fifo_width_convert_1_2 u_fifo_width_convert_1_2 (
|
||||
.clk (clk), // input wire clk
|
||||
.srst (rst), // input wire srst
|
||||
.din (ldpc_dout), // input wire [0 : 0] din
|
||||
.wr_en (ldpc_out_valid), // input wire wr_en
|
||||
.rd_en (data_add_prefix_in_ready), // input wire rd_en
|
||||
.dout (data_add_prefix_in), // output wire [1 : 0] dout
|
||||
.full (), // output wire full
|
||||
.empty (fifo_wc_empty), // output wire empty
|
||||
.prog_full(fifo_wc_prog_full)
|
||||
);
|
||||
|
||||
|
||||
add_prefix #(
|
||||
.WIDTH (2), // ! if this parameter is changed, make sure the shift IP inside is also changed
|
||||
.DATA_LEN (256),
|
||||
.PREFIX_LEN(8)
|
||||
) u_add_prefix (
|
||||
.clk (clk),
|
||||
.start (add_prefix_start),
|
||||
.ready (add_prefix_in_ready),
|
||||
.data_in (data_add_prefix_in),
|
||||
.data_in_ready (data_add_prefix_in_ready),
|
||||
.data_out (data_add_prefix_out),
|
||||
.data_out_valid(data_add_prefix_out_valid)
|
||||
);
|
||||
|
||||
fifo_enc_out u_fifo_enc_out (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk (clk), // input wire wr_clk
|
||||
.rd_clk (fifo_enc_out_rd_clk), // input wire rd_clk
|
||||
.din (data_add_prefix_out), // input wire [1 : 0] din
|
||||
.wr_en (data_add_prefix_out_valid), // input wire wr_en
|
||||
.rd_en (fifo_enc_out_rd_en), // input wire rd_en
|
||||
.dout (fifo_enc_out_dout), // output wire [1 : 0] dout
|
||||
.full (), // output wire full
|
||||
.empty (fifo_enc_out_empty), // output wire empty
|
||||
.almost_empty(fifo_enc_out_almost_empty), // output wire almost_empty
|
||||
.prog_empty (fifo_enc_out_prog_empty_1x) // output wire prog_empty
|
||||
);
|
||||
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
||||
) xpm_cdc_single_inst (
|
||||
.dest_out(fifo_enc_out_prog_empty), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk(clk), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (fifo_enc_out_rd_clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (fifo_enc_out_prog_empty_1x) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,58 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
|
||||
module frame_sync #(
|
||||
parameter [511:0] M_SEQ =512'b11111111100001111011100001011001101101111010000111001100001001000101011101011110010010111001110000001110111010011110101001010000001010101011111010110100000110111011011010110000010111011111000111100110100110101110001101000101111111010010110001010011000110000000110011001010110010011111101101001001001101111110010110101000010100010011101100101111011000011010101001110010000110001000010000000010001000110010001110101011011000111000100101010001101100111110011110001011011100101001000001001100111010001111101111000000,
|
||||
parameter [511:0] M_SEQ_REVERSE =512'b00000011110111110001011100110010000010010100111011010001111001111100110110001010100100011100011011010101110001001100010001000000001000010001100001001110010101011000011011110100110111001000101000010101101001111110110010010010110111111001001101010011001100000001100011001010001101001011111110100010110001110101100101100111100011111011101000001101011011011101100000101101011111010101010000001010010101111001011101110000001110011101001001111010111010100010010000110011100001011110110110011010000111011110000111111111
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input [11:0] data_i,
|
||||
input [11:0] data_q,
|
||||
output [17:0] dmf_i,
|
||||
output [17:0] dmf_q
|
||||
);
|
||||
|
||||
reg [ 9:0] data_i_reg[511:0];
|
||||
wire [17:0] sum_i [511:0];
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 512; i = i + 1) begin : adder_gen_block
|
||||
if (i == 0) begin
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_i_reg[i] <= 10'd0;
|
||||
end
|
||||
else begin
|
||||
data_i_reg[i] <= data_i[11-:10];
|
||||
end
|
||||
end
|
||||
adder_iq u_adder_i (
|
||||
.A (18'd0),
|
||||
.B (data_i_reg[i]),
|
||||
.CLK(clk),
|
||||
.ADD(~M_SEQ_REVERSE[i]),
|
||||
.S (sum_i[i])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_i_reg[i] <= 10'd0;
|
||||
end
|
||||
else begin
|
||||
data_i_reg[i] <= data_i_reg[i-1];
|
||||
end
|
||||
end
|
||||
adder_iq u_adder_i (
|
||||
.A (sum_i[i-1]),
|
||||
.B (data_i_reg[i]),
|
||||
.CLK(clk),
|
||||
.ADD(~M_SEQ_REVERSE[i]),
|
||||
.S (sum_i[i])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,377 @@
|
||||
`timescale 1ns / 100ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Beijing Institute of Technology
|
||||
// Engineer: FanHao
|
||||
//
|
||||
// Create Date: 02/08/2023 04:40:51 PM
|
||||
// Design Name:
|
||||
// Module Name: axi_lite
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions: 2022.2
|
||||
// Description: An axi-lite wrap for register configuration
|
||||
//
|
||||
// Dependencies: up_axi
|
||||
//
|
||||
// Revision:
|
||||
// [0.0-01] - Initial Version: Add asynchronized clock support.
|
||||
// [0.0-00] - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module phy_control #(
|
||||
parameter ASYNC_CLK = 1,
|
||||
// parameter REG_SPACE_ADDR_WIDTH = 5,
|
||||
parameter AXI_ADDRESS_WIDTH = 5
|
||||
) (
|
||||
/********************************************************************************/
|
||||
/************************** Slave AXI-LITE interface ****************************/
|
||||
/********************************************************************************/
|
||||
//--- DO NOT MODIFY FOLLOWING CONTANT
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ACLK, PHASE 0.000" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ACLK CLK" *)
|
||||
input s_axi_aclk, (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW" *) (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ARESETN RST" *)
|
||||
input s_axi_aresetn, (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, CLK_DOMAIN ACLK, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input s_axi_awvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input [AXI_ADDRESS_WIDTH-1:0] s_axi_awaddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output s_axi_awready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input [ 2:0] s_axi_awprot, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input s_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input [ 31:0] s_axi_wdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input [ 3:0] s_axi_wstrb, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output s_axi_wready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output s_axi_bvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output [ 1:0] s_axi_bresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input s_axi_bready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input s_axi_arvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input [AXI_ADDRESS_WIDTH-1:0] s_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output s_axi_arready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input [ 2:0] s_axi_arprot, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output s_axi_rvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input s_axi_rready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output [ 1:0] s_axi_rresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output [ 31:0] s_axi_rdata,
|
||||
//--- DO NOT MODIFY CONTANT ABOVE
|
||||
/********************************************************************************/
|
||||
/******************************** User Interface ********************************/
|
||||
/********************************************************************************/
|
||||
//--- ADD YOUR OWN PORTS START
|
||||
// main clock
|
||||
|
||||
input clk, // can be floating if ASYNC_CLK == 0
|
||||
// resetn (should synchronised with "clk")
|
||||
input rstn, // can be floating if ASYNC_CLK == 0
|
||||
|
||||
output wire phy_rst,
|
||||
output wire phy_tx_test_flag
|
||||
//--- ADD YOUR OWN PORTS END
|
||||
);
|
||||
|
||||
// MODULE_VERSION[31:24] Major Version
|
||||
// MODULE_VERSION[23:16] Minor Version
|
||||
// MODULE_VERSION[15: 0] Revision
|
||||
localparam MODULE_VERSION = 'h000001;
|
||||
|
||||
/********************************************************************************/
|
||||
/******************************** Interface Logic *******************************/
|
||||
/********************************************************************************/
|
||||
//--- DO NOT MODIFY FOLLOWING CONTANT
|
||||
// Module internal signals
|
||||
wire local_clk;
|
||||
wire local_rstn;
|
||||
|
||||
wire up_rreq_s;
|
||||
reg [ 31:0] up_rdata_ff = 'd0;
|
||||
reg up_rack_ff = 1'b0;
|
||||
wire up_wreq_s;
|
||||
wire [ 31:0] up_wdata_s;
|
||||
reg up_wack_ff = 1'b0;
|
||||
wire [(AXI_ADDRESS_WIDTH-3):0] up_waddr_s;
|
||||
wire [(AXI_ADDRESS_WIDTH-3):0] up_raddr_s;
|
||||
|
||||
// up_axi interface signals
|
||||
wire up_rack;
|
||||
wire up_rreq;
|
||||
wire [ 31:0] up_rdata;
|
||||
wire up_wack;
|
||||
wire up_wreq;
|
||||
wire [ 31:0] up_wdata;
|
||||
wire [(AXI_ADDRESS_WIDTH-3):0] up_waddr;
|
||||
wire [(AXI_ADDRESS_WIDTH-3):0] up_raddr;
|
||||
|
||||
// following signals indicate corresponding rep/ack were received.
|
||||
wire up_rreq_rcv;
|
||||
wire up_wreq_rcv;
|
||||
wire up_rack_rcv;
|
||||
wire up_wack_rcv;
|
||||
|
||||
generate
|
||||
if (ASYNC_CLK) begin
|
||||
assign local_clk = clk;
|
||||
assign local_rstn = rstn;
|
||||
|
||||
// read channel synchronisation
|
||||
reg up_rreq_send = 1'b0;
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (s_axi_aresetn == 1'b0) begin
|
||||
up_rreq_send <= 1'b0;
|
||||
end
|
||||
else if (up_rreq) begin
|
||||
up_rreq_send <= 1'b1;
|
||||
end
|
||||
else if (up_rreq_rcv) begin
|
||||
up_rreq_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
xpm_cdc_handshake #(
|
||||
.DEST_EXT_HSK(0),
|
||||
.DEST_SYNC_FF(2),
|
||||
.INIT_SYNC_FF(1),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.SRC_SYNC_FF(2),
|
||||
.WIDTH((AXI_ADDRESS_WIDTH - 2)) // raddr
|
||||
) i_rd_req_xpm_cdc (
|
||||
.dest_clk(local_clk),
|
||||
.dest_req(up_rreq_s),
|
||||
.dest_out({up_raddr_s[(AXI_ADDRESS_WIDTH-3):0]}),
|
||||
.src_clk (s_axi_aclk),
|
||||
.src_send(up_rreq_send),
|
||||
.src_rcv (up_rreq_rcv),
|
||||
.src_in ({up_raddr[(AXI_ADDRESS_WIDTH-3):0]})
|
||||
);
|
||||
reg up_rack_send = 1'b0;
|
||||
always @(posedge local_clk) begin
|
||||
if (local_rstn == 1'b0) begin
|
||||
up_rack_send <= 1'b0;
|
||||
end
|
||||
else if (up_rack_ff) begin
|
||||
up_rack_send <= 1'b1;
|
||||
end
|
||||
else if (up_rack_rcv) begin
|
||||
up_rack_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
xpm_cdc_handshake #(
|
||||
.DEST_EXT_HSK(0),
|
||||
.DEST_SYNC_FF(2),
|
||||
.INIT_SYNC_FF(1),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.SRC_SYNC_FF(2),
|
||||
.WIDTH(32) //rdata
|
||||
) i_rd_rsp_xpm_cdc (
|
||||
.dest_clk(s_axi_aclk),
|
||||
.dest_req(up_rack),
|
||||
.dest_out({up_rdata[31:0]}),
|
||||
.src_clk (local_clk),
|
||||
.src_send(up_rack_send),
|
||||
.src_rcv (up_rack_rcv),
|
||||
.src_in ({up_rdata_ff[31:0]})
|
||||
);
|
||||
|
||||
// write channel synchronisation
|
||||
reg up_wreq_send = 1'b0;
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (s_axi_aresetn == 1'b0) begin
|
||||
up_wreq_send <= 1'b0;
|
||||
end
|
||||
else if (up_wreq) begin
|
||||
up_wreq_send <= 1'b1;
|
||||
end
|
||||
else if (up_wreq_rcv) begin
|
||||
up_wreq_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
xpm_cdc_handshake #(
|
||||
.DEST_EXT_HSK(0),
|
||||
.DEST_SYNC_FF(2),
|
||||
.INIT_SYNC_FF(1),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.SRC_SYNC_FF(2),
|
||||
.WIDTH((AXI_ADDRESS_WIDTH - 2) + 32) //waddr + wdata
|
||||
) i_wr_req_ctrl_xpm_cdc (
|
||||
.dest_clk(local_clk),
|
||||
.dest_req(up_wreq_s),
|
||||
.dest_out({up_waddr_s[(AXI_ADDRESS_WIDTH-3):0], up_wdata_s[31:0]}),
|
||||
.src_clk (s_axi_aclk),
|
||||
.src_send(up_wreq_send),
|
||||
.src_rcv (up_wreq_rcv),
|
||||
.src_in ({up_waddr[(AXI_ADDRESS_WIDTH-3):0], up_wdata[31:0]})
|
||||
);
|
||||
reg up_wack_send = 1'b0;
|
||||
always @(posedge local_clk) begin
|
||||
if (local_rstn == 1'b0) begin
|
||||
up_wack_send <= 1'b0;
|
||||
end
|
||||
else if (up_wack_ff) begin
|
||||
up_wack_send <= 1'b1;
|
||||
end
|
||||
else if (up_wack_rcv) begin
|
||||
up_wack_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
xpm_cdc_handshake #(
|
||||
.DEST_EXT_HSK(0),
|
||||
.DEST_SYNC_FF(2),
|
||||
.INIT_SYNC_FF(1),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.SRC_SYNC_FF(2),
|
||||
.WIDTH(1) // wack
|
||||
) i_wr_rsp_data_xpm_cdc (
|
||||
.dest_clk(s_axi_aclk),
|
||||
.dest_req(up_wack),
|
||||
.src_clk (local_clk),
|
||||
.src_send(up_wack_send),
|
||||
.src_rcv (up_wack_rcv),
|
||||
.src_in (1)
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign local_clk = s_axi_aclk;
|
||||
assign local_rstn = s_axi_aresetn;
|
||||
assign up_rack = up_rack_ff;
|
||||
assign up_rreq_s = up_rreq;
|
||||
assign up_rdata = up_rdata_ff;
|
||||
assign up_wack = up_wack_ff;
|
||||
assign up_wreq_s = up_wreq;
|
||||
assign up_wdata_s[31:0] = up_wdata[31:0];
|
||||
assign up_waddr_s[(AXI_ADDRESS_WIDTH-3):0] = up_waddr[(AXI_ADDRESS_WIDTH-3):0];
|
||||
assign up_raddr_s = up_raddr[(AXI_ADDRESS_WIDTH-3):0];
|
||||
assign up_rreq_rcv = up_rreq_s;
|
||||
assign up_wreq_rcv = up_wreq_s;
|
||||
assign up_rack_rcv = up_rack_ff;
|
||||
assign up_wack_rcv = up_wack_ff;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// up-axi interface wrapper
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH(AXI_ADDRESS_WIDTH)
|
||||
) i_up_axi (
|
||||
.up_rstn (s_axi_aresetn),
|
||||
.up_clk (s_axi_aclk),
|
||||
.up_axi_awvalid(s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready(s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready(s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack)
|
||||
);
|
||||
|
||||
always @(posedge local_clk) begin
|
||||
if (local_rstn == 1'b0) begin
|
||||
up_rack_ff <= 'd0;
|
||||
end
|
||||
else begin
|
||||
up_rack_ff <= up_rreq_s;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge local_clk) begin
|
||||
if (local_rstn == 1'b0) begin
|
||||
up_wack_ff <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
up_wack_ff <= up_wreq_s;
|
||||
end
|
||||
end
|
||||
//--- DO NOT MODIFY CONTANT ABOVE
|
||||
|
||||
/********************************************************************************/
|
||||
/********************************** User Logic **********************************/
|
||||
/********************************************************************************/
|
||||
// BASIC RULES:
|
||||
// 1. AIX Write operation alwayse has the highet priority.
|
||||
// 2. Every userside operation must use "local_clk" as driving clock
|
||||
// 3. Every regoster must have a perfectely defined access type
|
||||
// you can use the following acronyms to define the register's access type
|
||||
// NOTE: different access types can be combined.
|
||||
// RO Read-only
|
||||
// CLRONRD Readable, clears value on read
|
||||
// CLRONWR Readable, Readable, clears value on write
|
||||
// RAZ Read as zero
|
||||
// RO Read only
|
||||
// RUD Read undefined
|
||||
// RW Normal read/write
|
||||
// RWSO Read/write, set only
|
||||
// WAZ Write as zero
|
||||
// WO Write-only
|
||||
// WTC Readable, write a one to clear
|
||||
// RWSO Read/write, set only
|
||||
// RUD Read undefined
|
||||
// RAZ Read as zero
|
||||
// Z Access (read or write) as zero
|
||||
//--- ADD YOUR OWN LOGIC START
|
||||
//--- EXAMPLE CODE START
|
||||
|
||||
// Register address definitions
|
||||
|
||||
// NOTE: 物理层寄存器定义，控制寄存器，状态寄存器
|
||||
|
||||
localparam integer PHY_CR = 'h00000000 >> 2; // RW
|
||||
localparam integer PHY_SR = 'h00000004 >> 2; // RW
|
||||
|
||||
// Register definitions
|
||||
reg [31:0] phy_cr_reg = 32'h0;
|
||||
reg [31:0] phy_sr_reg = 32'h0;
|
||||
|
||||
// Register Reading
|
||||
always @(posedge local_clk) begin
|
||||
case (up_raddr_s)
|
||||
PHY_CR: up_rdata_ff <= phy_cr_reg;
|
||||
PHY_SR: up_rdata_ff <= phy_sr_reg;
|
||||
default: up_rdata_ff <= 'h00;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Main Logic
|
||||
always @(posedge local_clk) begin
|
||||
if (local_rstn == 1'b0) begin
|
||||
phy_cr_reg <= 32'h0;
|
||||
phy_sr_reg <= 32'h0;
|
||||
end
|
||||
else begin
|
||||
// AXI write operation alwayse has the higest priority.
|
||||
if (up_wreq_s == 1'b1) begin
|
||||
case (up_waddr_s)
|
||||
PHY_CR: phy_cr_reg <= up_wdata_s;
|
||||
PHY_SR: phy_sr_reg <= up_wdata_s;
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
// self logic
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// control reg definition
|
||||
assign phy_rst = ~phy_cr_reg[0];
|
||||
assign phy_tx_test_flag = phy_cr_reg[1];
|
||||
|
||||
|
||||
|
||||
|
||||
//--- ADD YOUR OWN LOGIC END
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,302 @@
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Update Date: 2024/7/16
|
||||
// * NOTE : this file use the sign bit number to estimate the
|
||||
// * NOTE : signal power, the drawback of this module is that
|
||||
// * NOTE : little amplitude over the threhold will be treated
|
||||
// * NOTE : as overflow, thus indicating a flag_too_high pulse
|
||||
// * NOTE :
|
||||
// * NOTE : as improvemnt, we can use a number as the threshold
|
||||
// * NOTE : such as 1800 ( under the 12bit input ).
|
||||
// * NOTE :
|
||||
|
||||
module power_measure (
|
||||
input clk,
|
||||
input rst,
|
||||
input start,
|
||||
// data input
|
||||
input wire [11:0] data_i,
|
||||
input wire [11:0] data_q,
|
||||
output reg flag_too_high,
|
||||
output reg flag_too_low
|
||||
);
|
||||
|
||||
localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数
|
||||
localparam CNT_MEASURING_MAX = 512; // * 观察64个周期
|
||||
localparam CNT_ADJUST_TIMES_MAX = 25;
|
||||
localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// * NOTE: during measuring, the sign bit numbers changes .
|
||||
// * NOTE: as the signal amplitude(power) changes.
|
||||
// * NOTE: thus, measuring the sign bit numbers can indicate
|
||||
// * NOTE: the power of the signal.
|
||||
// * NOTE:
|
||||
// * NOTE: the sign bit number min, represents the minimum of
|
||||
// * NOTE: the sign bit number, meaning the highest signal power.
|
||||
// * NOTE: if sign_bit_num_min_* is too small (1 or 2), we should
|
||||
// * NOTE: decrease the input signal power.
|
||||
// * NOTE:
|
||||
// * NOTE: reversely, the sign_bit_num_max_* means the maximum of
|
||||
// * NOTE: the amplitude, if signal power is too small, it will be
|
||||
// * NOTE: small, indicating increasing the input signal power.
|
||||
// * NOTE:
|
||||
// * NOTE: for a modulated signal, the power can not be indicated by
|
||||
// * NOTE: max sign bit number, so we should only control the min sign
|
||||
// * NOTE: bit numer.
|
||||
|
||||
reg [ 3:0] sign_bit_num_i;
|
||||
reg [ 3:0] sign_bit_num_min_i;
|
||||
reg [ 3:0] sign_bit_num_q;
|
||||
reg [ 3:0] sign_bit_num_min_q;
|
||||
|
||||
// startup
|
||||
reg [ 7:0] cnt_startup; // set rx gain to max each time start posedge comes
|
||||
reg [ 3:0] cnt_amp_too_high; // for short cuirt
|
||||
|
||||
// abs
|
||||
reg [11:0] data_i_abs;
|
||||
reg [11:0] data_q_abs;
|
||||
|
||||
// measuring the signal power
|
||||
reg [15:0] cnt_measuring;
|
||||
// for waiting ad9361 adjust done
|
||||
reg [15:0] cnt_wait_9361;
|
||||
// the times fsm have adjust already
|
||||
reg [ 7:0] cnt_adjust_times;
|
||||
|
||||
// fsm var
|
||||
localparam S_MEASURE_IDLE = 0;
|
||||
localparam S_MEASURE_ING = 1;
|
||||
localparam S_MEASURE_DONE = 2;
|
||||
localparam S_MEASURE_ADJ = 3;
|
||||
localparam S_MEASURE_STARTUP = 4;
|
||||
|
||||
reg [2:0] cs = S_MEASURE_IDLE;
|
||||
reg [2:0] ns = S_MEASURE_IDLE;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst || start) begin
|
||||
cnt_startup <= 0;
|
||||
end
|
||||
else if (cs == S_MEASURE_STARTUP && cnt_startup < 255) begin
|
||||
cnt_startup <= cnt_startup + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cs <= S_MEASURE_IDLE;
|
||||
end
|
||||
else begin
|
||||
cs <= ns;
|
||||
end
|
||||
end
|
||||
|
||||
// fsm
|
||||
always @(*) begin
|
||||
case (cs)
|
||||
|
||||
S_MEASURE_IDLE: begin
|
||||
if (start) begin
|
||||
ns = S_MEASURE_STARTUP;
|
||||
end
|
||||
else begin
|
||||
ns = S_MEASURE_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
S_MEASURE_STARTUP: begin
|
||||
if (cnt_startup == 255) begin
|
||||
ns = S_MEASURE_ING;
|
||||
end
|
||||
else begin
|
||||
ns = S_MEASURE_STARTUP;
|
||||
end
|
||||
end
|
||||
|
||||
S_MEASURE_ING: begin
|
||||
if (cnt_measuring == CNT_MEASURING_MAX - 1 || cnt_amp_too_high == CNT_AMP_TOO_HIGH_THRESHOLD - 1) begin
|
||||
ns = S_MEASURE_DONE;
|
||||
end
|
||||
else begin
|
||||
ns = S_MEASURE_ING;
|
||||
end
|
||||
end
|
||||
|
||||
S_MEASURE_DONE: begin
|
||||
ns = S_MEASURE_ADJ;
|
||||
end
|
||||
|
||||
S_MEASURE_ADJ: begin
|
||||
// mgc adjust done
|
||||
if (cnt_adjust_times == CNT_ADJUST_TIMES_MAX - 1) begin
|
||||
ns = S_MEASURE_IDLE;
|
||||
end
|
||||
// wait ad9361 feedback
|
||||
else if (cnt_wait_9361 == CNT_WAIT_9361_MAX - 1) begin
|
||||
ns = S_MEASURE_ING;
|
||||
end
|
||||
else begin
|
||||
ns = S_MEASURE_ADJ;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
ns = S_MEASURE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_MEASURE_ING) begin
|
||||
cnt_measuring <= cnt_measuring + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_measuring <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_MEASURE_ADJ) begin
|
||||
cnt_wait_9361 <= cnt_wait_9361 + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_wait_9361 <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_MEASURE_DONE) begin
|
||||
cnt_adjust_times <= cnt_adjust_times + 1;
|
||||
end
|
||||
else if (cs == S_MEASURE_IDLE) begin
|
||||
cnt_adjust_times <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_MEASURE_ING && (sign_bit_num_i == 1 || sign_bit_num_q == 1)) begin
|
||||
cnt_amp_too_high <= cnt_amp_too_high + 1;
|
||||
end
|
||||
else if (cs == S_MEASURE_ADJ || cs == S_MEASURE_IDLE) begin
|
||||
cnt_amp_too_high <= 0;
|
||||
end
|
||||
else begin
|
||||
cnt_amp_too_high <= cnt_amp_too_high;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// get the abs value
|
||||
always @(posedge clk) begin
|
||||
// i
|
||||
if (data_i[11]) begin
|
||||
data_i_abs <= -data_i;
|
||||
end
|
||||
else begin
|
||||
data_i_abs <= data_i;
|
||||
end
|
||||
// q
|
||||
if (data_q[11]) begin
|
||||
data_q_abs <= -data_q;
|
||||
end
|
||||
else begin
|
||||
data_q_abs <= data_q;
|
||||
end
|
||||
end
|
||||
|
||||
// get the sign number bit number of the temporary 12 bit number
|
||||
always @(*) begin
|
||||
casez (data_i_abs)
|
||||
12'b1000_0000_0000: sign_bit_num_i <= 8'd1;
|
||||
12'b01??_????_????: sign_bit_num_i <= 8'd1;
|
||||
12'b001?_????_????: sign_bit_num_i <= 8'd2;
|
||||
12'b0001_????_????: sign_bit_num_i <= 8'd3;
|
||||
12'b0000_1???_????: sign_bit_num_i <= 8'd4;
|
||||
12'b0000_01??_????: sign_bit_num_i <= 8'd5;
|
||||
12'b0000_001?_????: sign_bit_num_i <= 8'd6;
|
||||
12'b0000_0001_????: sign_bit_num_i <= 8'd7;
|
||||
12'b0000_0000_1???: sign_bit_num_i <= 8'd8;
|
||||
12'b0000_0000_01??: sign_bit_num_i <= 8'd9;
|
||||
12'b0000_0000_001?: sign_bit_num_i <= 8'd10;
|
||||
12'b0000_0000_0001: sign_bit_num_i <= 8'd11;
|
||||
default: begin
|
||||
sign_bit_num_i <= 8'd12;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// get the sign number bit number of the temporary 12 bit number
|
||||
always @(*) begin
|
||||
casez (data_q_abs)
|
||||
12'b1000_0000_0000: sign_bit_num_q <= 8'd1;
|
||||
12'b01??_????_????: sign_bit_num_q <= 8'd1;
|
||||
12'b001?_????_????: sign_bit_num_q <= 8'd2;
|
||||
12'b0001_????_????: sign_bit_num_q <= 8'd3;
|
||||
12'b0000_1???_????: sign_bit_num_q <= 8'd4;
|
||||
12'b0000_01??_????: sign_bit_num_q <= 8'd5;
|
||||
12'b0000_001?_????: sign_bit_num_q <= 8'd6;
|
||||
12'b0000_0001_????: sign_bit_num_q <= 8'd7;
|
||||
12'b0000_0000_1???: sign_bit_num_q <= 8'd8;
|
||||
12'b0000_0000_01??: sign_bit_num_q <= 8'd9;
|
||||
12'b0000_0000_001?: sign_bit_num_q <= 8'd10;
|
||||
12'b0000_0000_0001: sign_bit_num_q <= 8'd11;
|
||||
default: begin
|
||||
sign_bit_num_q <= 8'd12;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_MEASURE_IDLE || cs == S_MEASURE_ADJ) begin
|
||||
sign_bit_num_min_i <= 8'd11;
|
||||
sign_bit_num_min_q <= 8'd11;
|
||||
end
|
||||
else if (cs == S_MEASURE_ING) begin
|
||||
if (sign_bit_num_min_i > sign_bit_num_i) begin
|
||||
sign_bit_num_min_i <= sign_bit_num_i;
|
||||
end
|
||||
if (sign_bit_num_min_q > sign_bit_num_q) begin
|
||||
sign_bit_num_min_q <= sign_bit_num_q;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// * flag_too_* generate logic, the core of the module
|
||||
always @(posedge clk) begin
|
||||
if (cnt_startup[2:0] == 3'b101 && cnt_startup <= 200) begin
|
||||
flag_too_high <= 0;
|
||||
flag_too_low <= 1;
|
||||
end
|
||||
else if (cs == S_MEASURE_DONE) begin
|
||||
// * 若符号位太多，则信号太小，需要增加信号功率
|
||||
if (sign_bit_num_min_i >= 3 || sign_bit_num_min_q >= 3) begin
|
||||
flag_too_low <= 1;
|
||||
end
|
||||
// * 若符号位太少，则信号太大，需要降低信号功率
|
||||
else if (sign_bit_num_min_i <= 1 || sign_bit_num_min_q <= 1 || cnt_amp_too_high >= CNT_AMP_TOO_HIGH_THRESHOLD - 1) begin
|
||||
flag_too_high <= 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
flag_too_high <= 0;
|
||||
flag_too_low <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,93 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/10/04 13:29:02
|
||||
// Design Name:
|
||||
// Module Name: shift_reg
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module shift_reg #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter DEPTH = 4
|
||||
) (
|
||||
input clk,
|
||||
(* max_fanout = 256 *) input rst,
|
||||
input we,
|
||||
input [DATA_WIDTH-1:0] din,
|
||||
output [DATA_WIDTH-1:0] dout
|
||||
);
|
||||
// generate
|
||||
// if (DEPTH > 1) begin
|
||||
// reg [DEPTH-1:0] shift_register[DATA_WIDTH-1:0];
|
||||
// genvar shift_bit_cnt;
|
||||
// for (shift_bit_cnt = 0; shift_bit_cnt < DATA_WIDTH; shift_bit_cnt = shift_bit_cnt + 1) begin : shift_each_bit
|
||||
// always @(posedge clk) begin
|
||||
// if (we) shift_register[shift_bit_cnt] <= {din[shift_bit_cnt], shift_register[shift_bit_cnt][DEPTH-1:1]};
|
||||
// else shift_register[shift_bit_cnt] <= shift_bit_cnt[shift_bit_cnt];
|
||||
// end
|
||||
// end
|
||||
// genvar output_bit_cnt;
|
||||
// for (output_bit_cnt = 0; output_bit_cnt < DATA_WIDTH; output_bit_cnt = output_bit_cnt + 1) begin : output_each_bit
|
||||
// assign dout[output_bit_cnt] = shift_register[output_bit_cnt][0];
|
||||
// end
|
||||
// end
|
||||
// else // just a reg
|
||||
// begin
|
||||
// reg [DATA_WIDTH-1:0] shift_register;
|
||||
// always @(posedge clk) begin
|
||||
// if (we) shift_register <= din;
|
||||
// else shift_register <= shift_register;
|
||||
// end
|
||||
// assign dout = shift_register;
|
||||
// end
|
||||
// endgenerate
|
||||
|
||||
|
||||
generate
|
||||
if (DEPTH > 1) begin
|
||||
reg [DATA_WIDTH-1:0] shift_register[DEPTH-1:0];
|
||||
genvar shift_reg_cnt;
|
||||
for (shift_reg_cnt = 0; shift_reg_cnt < DEPTH; shift_reg_cnt = shift_reg_cnt + 1) begin : shift_each_reg
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
shift_register[shift_reg_cnt][DATA_WIDTH-1:0] <= 'd0;
|
||||
end
|
||||
else if (we) begin
|
||||
if (shift_reg_cnt == 0) begin
|
||||
shift_register[shift_reg_cnt] <= din;
|
||||
end
|
||||
else begin
|
||||
shift_register[shift_reg_cnt] <= shift_register[shift_reg_cnt-1];
|
||||
end
|
||||
end
|
||||
else shift_register[shift_reg_cnt] <= shift_register[shift_reg_cnt];
|
||||
end
|
||||
end
|
||||
assign dout = shift_register[DEPTH-1];
|
||||
end
|
||||
else // just a reg
|
||||
begin
|
||||
reg [DATA_WIDTH-1:0] shift_register;
|
||||
always @(posedge clk) begin
|
||||
if (we) shift_register <= din;
|
||||
else shift_register <= shift_register;
|
||||
end
|
||||
assign dout = shift_register;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,358 @@
|
||||
`timescale 10ns / 10ns
|
||||
// * Micro7020
|
||||
|
||||
module system_top (
|
||||
// rx data
|
||||
input ad9361_rx_clk, // ad9361 receive data clock output
|
||||
input ad9361_rx_frame, // ad9361 receive data frame output signal, indicates I & Q
|
||||
input [11:0] ad9361_rx_data, // ad9361 receive data
|
||||
// tx data
|
||||
output ad9361_tx_clk, // ad9361 feedback clock
|
||||
output ad9361_tx_frame, // ad9361 transmit data frame input signal, indicates I & Q
|
||||
output [11:0] ad9361_tx_data, // ad9361 transmit data
|
||||
// spi interface
|
||||
input ad9361_spi_miso,
|
||||
output ad9361_spi_csn,
|
||||
output ad9361_spi_clk,
|
||||
output ad9361_spi_mosi,
|
||||
// control signal
|
||||
output ad9361_reset_b, // asynchronous reset, active low
|
||||
output ad9361_en_agc, // enable AGC, active high
|
||||
output ad9361_enable, // enable ad9361, active high
|
||||
output ad9361_txnrx, // logic low selects the RX, logic high selects the TX
|
||||
output wire [ 3:0] ad9361_ctrl_in, // ad9361 control in pins, for fastlock control
|
||||
// fixed-io
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
// clock signal
|
||||
input clk_crystal,
|
||||
// ddr
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
// uart
|
||||
input uart_rx,
|
||||
output uart_tx,
|
||||
// RF interface control signals
|
||||
output wire [ 5:0] rf_gpio,
|
||||
output wire led_red,
|
||||
output wire led_yellow,
|
||||
output wire led_blue
|
||||
);
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// power on clock domain
|
||||
wire clk_poweron;
|
||||
(*max_fanout = 256 *)
|
||||
wire rst_sys;
|
||||
wire poweron_locked;
|
||||
|
||||
// ad9361 clock domain
|
||||
wire locked;
|
||||
wire clk_1x;
|
||||
wire clk_2x;
|
||||
wire clk_4x;
|
||||
|
||||
// emio
|
||||
wire [31:0] gpio_i;
|
||||
wire [31:0] gpio_o;
|
||||
wire [31:0] gpio_t;
|
||||
|
||||
// enc signal
|
||||
wire enc_fifo_rd_en;
|
||||
wire [31:0] enc_fifo_dout_map;
|
||||
wire enc_fifo_empty;
|
||||
|
||||
// tx bus
|
||||
wire clk_tx_data_src;
|
||||
wire [31:0] tx_data_src_count;
|
||||
wire [31:0] tx_data_src_tdata;
|
||||
wire tx_data_src_tready;
|
||||
wire tx_data_src_tvalid;
|
||||
// tx signal
|
||||
wire tx_test_flag;
|
||||
|
||||
// baseband signal
|
||||
wire [11:0] ad9361_rx_data_i;
|
||||
wire [11:0] ad9361_rx_data_q;
|
||||
wire ad9361_rx_frame_i;
|
||||
wire ad9361_rx_frame_q;
|
||||
wire [11:0] ad9361_tx_data_i;
|
||||
wire [11:0] ad9361_tx_data_q;
|
||||
wire [ 2:0] speed_mode;
|
||||
|
||||
// phy control signal
|
||||
wire phy_rst_vio;
|
||||
wire phy_rst_ps;
|
||||
wire phy_rst;
|
||||
wire phy_tx_test_flag_vio;
|
||||
wire phy_tx_test_flag;
|
||||
|
||||
// tx signal
|
||||
wire frame_sync_pulse;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign ad9361_tx_clk = clk_1x;
|
||||
assign rst_sys = ~poweron_locked;
|
||||
// ad9361 control
|
||||
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
|
||||
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
|
||||
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
|
||||
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
|
||||
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
clk_wiz_poweron u_clk_wiz_poweron (
|
||||
// Clock out ports
|
||||
.clk_poweron(clk_poweron), // output clk_poweron
|
||||
// Status and control signals
|
||||
.locked (poweron_locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_crystal(clk_crystal) // input clk_crystal
|
||||
);
|
||||
|
||||
// clock domain - ad9361 rx & tx
|
||||
clk_wiz_baseband u_clk_wiz_baseband (
|
||||
// Clock out ports
|
||||
.clk_1x (clk_1x), // output clk_1x
|
||||
.clk_2x (clk_2x), // output clk_2x
|
||||
.clk_4x (clk_4x), // output clk_4x
|
||||
// Status and control signals
|
||||
.locked (locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_src(ad9361_rx_clk) // input clk_src
|
||||
);
|
||||
|
||||
MM7020_BD_wrapper u_MM7020_BD_wrapper (
|
||||
.ad9361_spi_clk (ad9361_spi_clk),
|
||||
.ad9361_spi_csn (ad9361_spi_csn),
|
||||
.ad9361_spi_miso (ad9361_spi_miso),
|
||||
.ad9361_spi_mosi (ad9361_spi_mosi),
|
||||
.clk_ps (clk_poweron),
|
||||
.rst_ps (rst_sys),
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
// fixed io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
// gpio ps
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
// intr pl to ps
|
||||
.pl2ps_intr2 (intr_2ps),
|
||||
.pl2ps_intr3 (pl2ps_intr3),
|
||||
// tx fifo
|
||||
.tx_data_src_count (tx_data_src_count),
|
||||
.tx_data_src_tdata (tx_data_src_tdata),
|
||||
.tx_data_src_tready(tx_data_src_tready),
|
||||
.tx_data_src_tvalid(tx_data_src_tvalid),
|
||||
//phy control signal
|
||||
.phy_rst (phy_rst_ps),
|
||||
.phy_tx_test_flag (phy_tx_test_flag),
|
||||
// uart
|
||||
.uart_rx (uart_rx),
|
||||
.uart_tx (uart_tx)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
// ---- PHY layer logic start
|
||||
|
||||
// enc_control u_enc_control (
|
||||
// .clk (clk_poweron),
|
||||
// .rst (rst_sys | phy_rst_ps),
|
||||
// .s_axis_fifo_tvalid (tx_data_src_tvalid),
|
||||
// .s_axis_fifo_tready (tx_data_src_tready),
|
||||
// .s_axis_fifo_tdata (tx_data_src_tdata),
|
||||
// .data_src_count (tx_data_src_count),
|
||||
// .fifo_enc_out_rd_clk (clk_1x),
|
||||
// .fifo_enc_out_rd_en (enc_fifo_rd_en),
|
||||
// .fifo_enc_out_dout_map(enc_fifo_dout_map),
|
||||
// .fifo_enc_out_empty (enc_fifo_empty)
|
||||
// );
|
||||
|
||||
|
||||
// tdma #(
|
||||
// .SLOT_LEN (1250000), // 50MHz--> 25ms
|
||||
// .TIC_TO_PS_LEN (1200000),
|
||||
// .TIC_FRAME_SYNC(42272)
|
||||
// ) u_tdma (
|
||||
// .clk (clk_1x),
|
||||
// .rst (rst_sys),
|
||||
// .flag_is_master (1'b0),
|
||||
// .flag_frame_sync(frame_sync_pulse),
|
||||
// .intr_2ps (intr_2ps),
|
||||
// .tx_start (tx_start)
|
||||
// );
|
||||
|
||||
|
||||
// Transmitter u_Transmitter (
|
||||
// .clk (clk_1x),
|
||||
// .rst (rst_sys | phy_rst | phy_rst_vio),
|
||||
// .speed_mode (speed_mode),
|
||||
// .send_data_ready (send_data_ready),
|
||||
// .send_start (send_start),
|
||||
// .send_over (send_over),
|
||||
// .clk_data_src (clk_data_src),
|
||||
// .tx_data_src_tdata (enc_fifo_dout_map),
|
||||
// .tx_data_src_tready(enc_fifo_rd_en),
|
||||
// .tx_data_src_tvalid(~enc_fifo_empty),
|
||||
// .hopping_freq (),
|
||||
// .ad9361_tx_data_i (ad9361_tx_data_i),
|
||||
// .ad9361_tx_data_q (ad9361_tx_data_q),
|
||||
// .test (tx_test_flag | phy_tx_test_flag_vio),
|
||||
// .hop_wait (100)
|
||||
// );
|
||||
|
||||
// Receiver u_Receiver (
|
||||
// .clk (clk_1x),
|
||||
// .clk_2x (clk_2x),
|
||||
// .clk_4x (clk_4x),
|
||||
// .rst (rst_sys | phy_rst | phy_rst_vio),
|
||||
// .speed_mode (speed_mode),
|
||||
// .ad9361_rx_data_i(ad9361_rx_data_i),
|
||||
// .ad9361_rx_data_q(ad9361_rx_data_q),
|
||||
// .frame_sync_pulse(frame_sync_pulse)
|
||||
// );
|
||||
|
||||
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys | phy_rst),
|
||||
.rx_data_i (ad9361_rx_data_i),
|
||||
.rx_data_q (ad9361_rx_data_q),
|
||||
.ad9361_ctrl_in(ad9361_ctrl_in)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ---- PHY layer logic end
|
||||
|
||||
|
||||
// ad9361 digital port - 1R1T, Dual Port, DDR
|
||||
ad9361_dp_fdd_1r1t ad9361_dp_fdd_1r1t_inst (
|
||||
// Receive
|
||||
.rx_clk (ad9361_rx_clk),
|
||||
.rx_data (ad9361_rx_data),
|
||||
.rx_frame (ad9361_rx_frame),
|
||||
.rx_data_i (ad9361_rx_data_i),
|
||||
.rx_data_q (ad9361_rx_data_q),
|
||||
.rx_frame_i(ad9361_rx_frame_i),
|
||||
.rx_frame_q(ad9361_rx_frame_q),
|
||||
// Transmit
|
||||
.tx_clk (ad9361_tx_clk),
|
||||
.tx_data_i (ad9361_tx_data_i),
|
||||
.tx_data_q (ad9361_tx_data_q),
|
||||
.tx_data (ad9361_tx_data),
|
||||
.tx_frame (ad9361_tx_frame)
|
||||
);
|
||||
|
||||
// ******** CDC ********
|
||||
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
||||
) xpm_cdc_single_tx_test_flag_ps_inst (
|
||||
.dest_out(tx_test_flag), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk(clk_1x), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (clk_poweron), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (phy_tx_test_flag) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
xpm_cdc_sync_rst #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) xpm_cdc_sync_rst_phy_rst_inst (
|
||||
.dest_rst(phy_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk(clk_1x), // 1-bit input: Destination clock.
|
||||
.src_rst (phy_rst_ps) // 1-bit input: Source reset signal.
|
||||
);
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
ila_ad9361_rx u_ila_ad9361_rx (
|
||||
.clk (ad9361_rx_clk),
|
||||
.probe0(ad9361_rx_data_i),
|
||||
.probe1(ad9361_rx_data_q),
|
||||
.probe2(u_ad9361_mgc_pin_ctrl.flag_adjust)
|
||||
);
|
||||
|
||||
ila_ad9361_tx u_ila_ad9361_tx (
|
||||
.clk (ad9361_tx_clk), // input wire clk
|
||||
.probe0(ad9361_tx_data_i), // input wire [11:0] probe0
|
||||
.probe1(ad9361_tx_data_q) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
|
||||
vio_phy_control u_vio_phy_control (
|
||||
.clk (clk_1x), // input wire clk
|
||||
.probe_out0(phy_rst_vio), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(phy_tx_test_flag_vio), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(send_start) // output wire [0 : 0] probe_out2
|
||||
);
|
||||
|
||||
|
||||
vio_gpio u_vio_gpio (
|
||||
.clk (clk_poweron),
|
||||
.probe_out0(rf_gpio),
|
||||
.probe_out1(led_red),
|
||||
.probe_out2(led_yellow),
|
||||
.probe_out3(led_blue)
|
||||
);
|
||||
|
||||
vio_tx_speed_mode u_vio_tx_speed_mode (
|
||||
.clk (clk_1x),
|
||||
.probe_out0(speed_mode)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+120
@@ -0,0 +1,120 @@
|
||||
`timescale 1ns / 1ps
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Create Date: 2024/04/08
|
||||
// * Update Date: 2024/05/17
|
||||
|
||||
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
|
||||
// ! WHEN U INSTANTIATE THIS MODULE
|
||||
module tdma #(
|
||||
parameter SLOT_LEN = 1250000,
|
||||
parameter TIC_TO_PS_LEN = 1200000,
|
||||
parameter TIC_FRAME_SYNC = 42272
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input flag_is_master,
|
||||
input flag_frame_sync,
|
||||
output intr_2ps,
|
||||
// output tic_hop,
|
||||
output tx_start
|
||||
);
|
||||
|
||||
// TODO: 需要检查综合后电路是否会被优化
|
||||
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
|
||||
// ******** Wire & Reg ********
|
||||
reg flag_is_tx_slot;
|
||||
// ******** Assingment ********
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
generate
|
||||
if (SLOT_LEN <= 65535) begin // slot len is small
|
||||
reg [15:0] cnt;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
if (!flag_is_master && flag_frame_sync) begin
|
||||
// slave update cnt
|
||||
cnt <= TIC_FRAME_SYNC;
|
||||
end
|
||||
else if (cnt >= SLOT_LEN - 1) begin
|
||||
cnt <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 16'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign tx_start = flag_is_tx_slot & (cnt == 16'd10); // just a num for avoiding the zero,(cnt is also 0 in rst state)
|
||||
assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if (!flag_is_master && flag_frame_sync) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if (cnt == 16'd1) begin
|
||||
flag_is_tx_slot <= ~flag_is_tx_slot;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
reg [15:0] cnt_l;
|
||||
reg [ 7:0] cnt_h;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_l <= 16'd0;
|
||||
cnt_h <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (!flag_is_master && flag_frame_sync) begin
|
||||
// slave update cnt
|
||||
{cnt_h, cnt_l} <= TIC_FRAME_SYNC;
|
||||
end
|
||||
else begin
|
||||
// master
|
||||
if ({cnt_h, cnt_l} >= SLOT_LEN) begin
|
||||
cnt_h <= 8'd0;
|
||||
cnt_l <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
{cnt_h, cnt_l} <= {cnt_h, cnt_l} + 24'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
assign tx_start = flag_is_tx_slot & ({cnt_h, cnt_l} == 16'd10);
|
||||
assign intr_2ps = ~flag_is_tx_slot & ({cnt_h, cnt_l} == TIC_TO_PS_LEN);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if (!flag_is_master && flag_frame_sync) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if ({cnt_h, cnt_l} == 16'd1) begin
|
||||
flag_is_tx_slot <= ~flag_is_tx_slot;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
endmodule
|
||||
+274
@@ -0,0 +1,274 @@
|
||||
`timescale 1ns / 100ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Beijing Institute of Technology
|
||||
// Engineer: FanHao
|
||||
//
|
||||
// Create Date: 02/08/2023 04:40:51 PM
|
||||
// Design Name:
|
||||
// Module Name: up_axi
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions: 2022.2
|
||||
// Description: An simple axi-lite interface
|
||||
//
|
||||
// Dependencies: none.
|
||||
//
|
||||
// Revision:
|
||||
// 0.0.01 - Initial Version: Add Read/Write error response
|
||||
// 0.0.00 - File Created
|
||||
//
|
||||
// Additional Comments:
|
||||
// Forked from Analog Devices HDL References Designe
|
||||
// (https://github.com/analogdevicesinc/hdl/)
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module up_axi #(
|
||||
parameter AXI_ADDRESS_WIDTH = 16
|
||||
) (
|
||||
|
||||
// reset and clocks
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
|
||||
// axi4 interface
|
||||
input up_axi_awvalid,
|
||||
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
|
||||
output up_axi_awready,
|
||||
input up_axi_wvalid,
|
||||
input [ 31:0] up_axi_wdata,
|
||||
input [ 3:0] up_axi_wstrb,
|
||||
output up_axi_wready,
|
||||
output up_axi_bvalid,
|
||||
output [ 1:0] up_axi_bresp,
|
||||
input up_axi_bready,
|
||||
input up_axi_arvalid,
|
||||
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
|
||||
output up_axi_arready,
|
||||
output up_axi_rvalid,
|
||||
output [ 1:0] up_axi_rresp,
|
||||
output [ 31:0] up_axi_rdata,
|
||||
input up_axi_rready,
|
||||
|
||||
// pcore interface
|
||||
|
||||
output up_wreq,
|
||||
output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
|
||||
output [ 31:0] up_wdata,
|
||||
input up_wack,
|
||||
output up_rreq,
|
||||
output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
|
||||
input [ 31:0] up_rdata,
|
||||
input up_rack
|
||||
);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_axi_awready_int = 'd0;
|
||||
reg up_axi_wready_int = 'd0;
|
||||
reg up_axi_bvalid_int = 'd0;
|
||||
reg [ 1:0] up_axi_bresp_int = 'd0;
|
||||
reg [ 1:0] up_bresp_d;
|
||||
reg up_wack_d = 'd0;
|
||||
reg up_wsel = 'd0;
|
||||
reg up_wreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
|
||||
reg [ 31:0] up_wdata_int = 'd0;
|
||||
reg [ 5:0] up_wcount = 'd0;
|
||||
reg up_axi_arready_int = 'd0;
|
||||
reg up_axi_rvalid_int = 'd0;
|
||||
reg [ 1:0] up_axi_rresp_int = 'd0;
|
||||
reg [ 31:0] up_axi_rdata_int = 'd0;
|
||||
reg up_rack_d = 'd0;
|
||||
reg [ 31:0] up_rdata_d = 'd0;
|
||||
reg [ 1:0] up_rresp_d = 'd0;
|
||||
reg up_rsel = 'd0;
|
||||
reg up_rreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
|
||||
reg [ 5:0] up_rcount = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wack_s;
|
||||
wire up_rack_s;
|
||||
wire [ 31:0] up_rdata_s;
|
||||
wire [ 1:0] up_rresp_s;
|
||||
wire [ 1:0] up_bresp_s;
|
||||
|
||||
// write channel interface
|
||||
assign up_axi_awready = up_axi_awready_int;
|
||||
assign up_axi_wready = up_axi_wready_int;
|
||||
assign up_axi_bvalid = up_axi_bvalid_int;
|
||||
assign up_axi_bresp = up_axi_bresp_int;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_awready_int <= 'd0;
|
||||
up_axi_wready_int <= 'd0;
|
||||
up_axi_bvalid_int <= 'd0;
|
||||
up_axi_bresp_int <= 'd0;
|
||||
end
|
||||
else begin
|
||||
|
||||
if (up_axi_awready_int == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b0;
|
||||
end
|
||||
else if (up_wack_s == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b1;
|
||||
end
|
||||
|
||||
if (up_axi_wready_int == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b0;
|
||||
end
|
||||
else if (up_wack_s == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b1;
|
||||
end
|
||||
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_axi_bvalid_int <= 1'b0;
|
||||
up_axi_bresp_int <= 'd0;
|
||||
end
|
||||
else if (up_wack_d == 1'b1) begin
|
||||
up_axi_bvalid_int <= 1'b1;
|
||||
up_axi_bresp_int <= (up_bresp_d) ? up_bresp_d : up_axi_bresp_int;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
assign up_wreq = up_wreq_int;
|
||||
assign up_waddr = up_waddr_int;
|
||||
assign up_wdata = up_wdata_int;
|
||||
assign up_wack_s = (up_wcount == 6'h3f) ? 1'b1 : (up_wcount[5] & up_wack);
|
||||
assign up_bresp_s = (up_wcount == 6'h3f) ? 2'b10 : 2'b00; // SLVERR : OKAY
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_wack_d <= 'd0;
|
||||
up_wsel <= 'd0;
|
||||
up_wreq_int <= 'd0;
|
||||
up_waddr_int <= 'd0;
|
||||
up_wdata_int <= 'd0;
|
||||
up_wcount <= 'd0;
|
||||
up_bresp_d <= 'd0;
|
||||
end
|
||||
else begin
|
||||
up_wack_d <= up_wack_s;
|
||||
up_bresp_d <= up_bresp_s;
|
||||
if (up_wsel == 1'b1) begin
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_wsel <= 1'b0;
|
||||
end
|
||||
up_wreq_int <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
up_wsel <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
up_wdata_int <= up_axi_wdata;
|
||||
end
|
||||
|
||||
if (up_wack_s == 1'b1) begin
|
||||
up_wcount <= 6'h00;
|
||||
end
|
||||
else if (up_wcount[5] == 1'b1) begin
|
||||
up_wcount <= up_wcount + 1'b1;
|
||||
end
|
||||
else if (up_wreq_int == 1'b1) begin
|
||||
up_wcount <= 6'h20;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// read channel interface
|
||||
assign up_axi_arready = up_axi_arready_int;
|
||||
assign up_axi_rvalid = up_axi_rvalid_int;
|
||||
assign up_axi_rdata = up_axi_rdata_int;
|
||||
assign up_axi_rresp = up_axi_rresp_int;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_arready_int <= 'd0;
|
||||
up_axi_rvalid_int <= 'd0;
|
||||
up_axi_rdata_int <= 'd0;
|
||||
up_axi_rresp_int <= 'd0;
|
||||
end
|
||||
else begin
|
||||
if (up_axi_arready_int == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b0;
|
||||
end
|
||||
else if (up_rack_s == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_axi_rvalid_int <= 1'b0;
|
||||
up_axi_rdata_int <= 'd0;
|
||||
up_axi_rresp_int <= 'd0;
|
||||
end
|
||||
else if (up_rack_d == 1'b1) begin
|
||||
up_axi_rvalid_int <= 1'b1;
|
||||
up_axi_rdata_int <= up_rdata_d;
|
||||
up_axi_rresp_int <= (up_rresp_d) ? up_rresp_d : up_axi_rresp_int;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_rreq = up_rreq_int;
|
||||
assign up_raddr = up_raddr_int;
|
||||
assign up_rack_s = (up_rcount == 6'h3f) ? 1'b1 : (up_rcount[5] & up_rack);
|
||||
assign up_rdata_s = (up_rcount == 6'h3f) ? {2{16'hdead}} : up_rdata;
|
||||
assign up_rresp_s = (up_rcount == 6'h3f) ? 2'b10 : 2'b00; // SLVERR : OKAY
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rack_d <= 'd0;
|
||||
up_rdata_d <= 'd0;
|
||||
up_rsel <= 'd0;
|
||||
up_rreq_int <= 'd0;
|
||||
up_raddr_int <= 'd0;
|
||||
up_rcount <= 'd0;
|
||||
end
|
||||
else begin
|
||||
up_rack_d <= up_rack_s;
|
||||
up_rdata_d <= up_rdata_s;
|
||||
up_rresp_d <= up_rresp_s;
|
||||
if (up_rsel == 1'b1) begin
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_rsel <= 1'b0;
|
||||
end
|
||||
up_rreq_int <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
up_rsel <= up_axi_arvalid;
|
||||
up_rreq_int <= up_axi_arvalid;
|
||||
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
end
|
||||
if (up_rack_s == 1'b1) begin
|
||||
up_rcount <= 6'h00;
|
||||
end
|
||||
else if (up_rcount[5] == 1'b1) begin
|
||||
up_rcount <= up_rcount + 1'b1;
|
||||
end
|
||||
else if (up_rreq_int == 1'b1) begin
|
||||
up_rcount <= 6'h20;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,90 @@
|
||||
`timescale 1ns / 1ps
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Update Date:
|
||||
// * NOTE : this is the first version convert from wider bitwidth to narrower bitwidth
|
||||
|
||||
module width_convert #(
|
||||
parameter INPUT_WIDTH = 16,
|
||||
parameter OUTPUT_WIDTH = 2
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input data_in_valid,
|
||||
input wire data_in_ready,
|
||||
input wire [INPUT_WIDTH - 1 : 0] data_in,
|
||||
output reg data_out_valid,
|
||||
output reg [OUTPUT_WIDTH -1 : 0] data_out
|
||||
|
||||
);
|
||||
|
||||
localparam CNT_MAX = INPUT_WIDTH / OUTPUT_WIDTH;
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
reg [ INPUT_WIDTH-1:0] data_in_latch;
|
||||
reg [$clog2(CNT_MAX) - 1 : 0] cnt;
|
||||
reg flag_working;
|
||||
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign data_in_ready = (~flag_working & ~rst) | (cnt == CNT_MAX - 1);
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_in_latch <= 'd0;
|
||||
end
|
||||
else begin
|
||||
if (data_in_valid && data_in_ready) begin
|
||||
data_in_latch <= data_in;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_working <= 0;
|
||||
end
|
||||
else if (data_in_valid) begin
|
||||
flag_working <= 1;
|
||||
end
|
||||
else if (cnt == CNT_MAX - 1) begin
|
||||
flag_working <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 0;
|
||||
end
|
||||
else if (flag_working) begin
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
data_out = data_in_latch[cnt*OUTPUT_WIDTH+OUTPUT_WIDTH-1-:OUTPUT_WIDTH];
|
||||
data_out_valid = flag_working;
|
||||
end
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+198
@@ -0,0 +1,198 @@
|
||||
`timescale 10ns / 10ns
|
||||
module TB_sys ();
|
||||
|
||||
|
||||
reg clk;
|
||||
reg req;
|
||||
always #1 clk <= ~clk;
|
||||
|
||||
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// power on clock domain
|
||||
wire clk_poweron;
|
||||
(*max_fanout = 256 *)
|
||||
wire rst_sys;
|
||||
wire poweron_locked;
|
||||
|
||||
// ad9361 clock domain
|
||||
wire locked;
|
||||
wire clk_1x;
|
||||
wire clk_2x;
|
||||
wire clk_4x;
|
||||
|
||||
// emio
|
||||
wire [31:0] gpio_i;
|
||||
wire [31:0] gpio_o;
|
||||
wire [31:0] gpio_t;
|
||||
|
||||
// enc signal
|
||||
wire enc_fifo_rd_en;
|
||||
wire [31:0] enc_fifo_dout_map;
|
||||
wire enc_fifo_empty;
|
||||
|
||||
// tx bus
|
||||
wire clk_tx_data_src;
|
||||
wire [31:0] tx_data_src_count;
|
||||
wire [15:0] tx_data_src_tdata;
|
||||
wire tx_data_src_tready;
|
||||
wire tx_data_src_tvalid;
|
||||
|
||||
// baseband signal
|
||||
wire [11:0] ad9361_rx_data_i;
|
||||
wire [11:0] ad9361_rx_data_q;
|
||||
wire ad9361_rx_frame_i;
|
||||
wire ad9361_rx_frame_q;
|
||||
wire [11:0] ad9361_tx_data_i;
|
||||
wire [11:0] ad9361_tx_data_q;
|
||||
|
||||
// test
|
||||
wire flag_transmitter_test;
|
||||
|
||||
|
||||
reg pl2ps_intr2;
|
||||
reg [31:0] cnt;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign ad9361_tx_clk = clk_1x;
|
||||
assign rst_sys = ~poweron_locked;
|
||||
// ad9361 control
|
||||
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
|
||||
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
|
||||
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
|
||||
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
|
||||
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst_sys) begin
|
||||
pl2ps_intr2 <= 0;
|
||||
cnt <= 0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 1;
|
||||
if (cnt == 1000 || cnt == 1500 || cnt == 2000) begin
|
||||
pl2ps_intr2 <= 1;
|
||||
end
|
||||
else begin
|
||||
pl2ps_intr2 <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
clk_wiz_poweron u_clk_wiz_poweron (
|
||||
// Clock out ports
|
||||
.clk_poweron(clk_poweron), // output clk_poweron
|
||||
// Status and control signals
|
||||
.locked (poweron_locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_crystal(clk_crystal) // input clk_crystal
|
||||
);
|
||||
|
||||
// clock domain - ad9361 rx & tx
|
||||
clk_wiz_baseband u_clk_wiz_baseband (
|
||||
// Clock out ports
|
||||
.clk_1x (clk_1x), // output clk_1x
|
||||
.clk_2x (clk_2x), // output clk_2x
|
||||
.clk_4x (clk_4x), // output clk_4x
|
||||
// Status and control signals
|
||||
.locked (locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_src(ad9361_rx_clk) // input clk_src
|
||||
);
|
||||
|
||||
MM7020_BD_wrapper u_MM7020_BD_wrapper (
|
||||
.ad9361_spi_clk (ad9361_spi_clk),
|
||||
.ad9361_spi_csn (ad9361_spi_csn),
|
||||
.ad9361_spi_miso (ad9361_spi_miso),
|
||||
.ad9361_spi_mosi (ad9361_spi_mosi),
|
||||
.clk_ps (clk_poweron),
|
||||
.rst_ps (rst_sys),
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
// fixed io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
// gpio ps
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
// intr pl to ps
|
||||
.pl2ps_intr2 (pl2ps_intr2),
|
||||
.pl2ps_intr3 (pl2ps_intr3),
|
||||
// tx fifo
|
||||
.tx_data_src_count (tx_data_src_count),
|
||||
.tx_data_src_tdata (tx_data_src_tdata),
|
||||
.tx_data_src_tready(tx_data_src_tready),
|
||||
.tx_data_src_tvalid(tx_data_src_tvalid),
|
||||
// uart
|
||||
.uart_rx (uart_rx),
|
||||
.uart_tx (uart_tx)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
// ---- PHY layer logic start
|
||||
|
||||
// enc_control u_enc_control (
|
||||
// .clk (clk_poweron),
|
||||
// .rst (rst_sys),
|
||||
// .s_axis_fifo_tvalid(tx_data_src_tvalid),
|
||||
// .s_axis_fifo_tready(tx_data_src_tready),
|
||||
// .s_axis_fifo_tdata (tx_data_src_tdata),
|
||||
// .data_src_count (tx_data_src_count),
|
||||
// .fifo_rd_clk (clk_1x),
|
||||
// .fifo_rd_en (enc_fifo_rd_en),
|
||||
// .fifo_dout_map (enc_fifo_dout_map),
|
||||
// .fifo_empty (enc_fifo_empty)
|
||||
// );
|
||||
|
||||
// Transmitter u_Transmitter (
|
||||
// .clk (clk_1x),
|
||||
// .rst (rst_sys),
|
||||
// .speed_mode (0),
|
||||
// .send_data_ready (send_data_ready),
|
||||
// .send_start (send_start),
|
||||
// .send_over (send_over),
|
||||
// .clk_data_src (clk_data_src),
|
||||
// .tx_data_src_tdata (enc_fifo_dout_map),
|
||||
// .tx_data_src_tready(enc_fifo_rd_en),
|
||||
// .tx_data_src_tvalid(~enc_fifo_empty),
|
||||
// .hopping_freq (),
|
||||
// .ad9361_tx_data_i (ad9361_tx_data_i),
|
||||
// .ad9361_tx_data_q (ad9361_tx_data_q),
|
||||
// .test (flag_transmitter_test),
|
||||
// .hop_wait (2000)
|
||||
// );
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,77 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/04/15 20:17:12
|
||||
// Design Name:
|
||||
// Module Name: tb_Receiver
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_Receiver ();
|
||||
reg clk;
|
||||
reg clk_2x;
|
||||
reg clk_4x;
|
||||
reg rst;
|
||||
localparam CLK_PERIOD = 20_0;
|
||||
always #(10) clk = ~clk;
|
||||
always #(5) clk_2x = ~clk_2x;
|
||||
always #(2.5) clk_4x = ~clk_4x;
|
||||
|
||||
// * start
|
||||
reg [11:0] ad9361_rx_data_i;
|
||||
reg [11:0] ad9361_rx_data_q;
|
||||
reg flag;
|
||||
reg [11:0] mem_i [10000:0];
|
||||
reg [11:0] mem_q [10000:0];
|
||||
|
||||
initial begin
|
||||
clk <= 1'b0;
|
||||
clk_2x <= 1'b0;
|
||||
clk_4x <= 1'b0;
|
||||
$readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_i_testbench.txt", mem_i);
|
||||
$readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_q_testbench.txt", mem_q);
|
||||
rst <= 1'b0;
|
||||
flag <= 0;
|
||||
#(CLK_PERIOD * 50) rst <= 1;
|
||||
#(CLK_PERIOD * 10) rst <= 0;
|
||||
#(CLK_PERIOD * 100) flag <= 1;
|
||||
|
||||
end
|
||||
|
||||
Receiver u_Receiver (
|
||||
.clk (clk),
|
||||
.clk_2x (clk_2x),
|
||||
.clk_4x (clk_4x),
|
||||
.rst (rst),
|
||||
.speed_mode (3'd0),
|
||||
.ad9361_rx_data_i(ad9361_rx_data_i),
|
||||
.ad9361_rx_data_q(ad9361_rx_data_q)
|
||||
);
|
||||
|
||||
reg [15:0] index = 16'd0;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
index <= 'd0;
|
||||
ad9361_rx_data_i <= 'd0;
|
||||
ad9361_rx_data_q <= 'd0;
|
||||
end
|
||||
else if (flag) begin
|
||||
ad9361_rx_data_i <= mem_i[index];
|
||||
ad9361_rx_data_q <= mem_q[index];
|
||||
index <= index + 16'd1;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,53 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module tb_Transmitter ();
|
||||
|
||||
|
||||
|
||||
reg clk = 1;
|
||||
reg clk_tx = 1;
|
||||
|
||||
reg rst = 1;
|
||||
|
||||
always #1 clk <= ~clk;
|
||||
always #2 clk_tx <= ~clk_tx;
|
||||
reg intr = 0;
|
||||
reg test=0;
|
||||
|
||||
initial begin
|
||||
#100 rst <= 0;
|
||||
#1000 test <=1;
|
||||
#1000 test <=0;
|
||||
#1000 test <=1;
|
||||
#1000 test <=1;
|
||||
end
|
||||
|
||||
Transmitter #(
|
||||
.AGC_HEADER_LEN(200),
|
||||
.FRAME_HEADER_LEN(512),
|
||||
.BLOCK_NUM(3),
|
||||
.PHASE1_LEN(2112),
|
||||
.PREFIX_LEN(8),
|
||||
.CHU_SEQ_LEN(128),
|
||||
.GAP_LEN(128)
|
||||
) u_Transmitter (
|
||||
.clk (clk_tx),
|
||||
.rst (rst),
|
||||
.speed_mode (0),
|
||||
.send_data_ready (),
|
||||
.send_start (),
|
||||
.send_over (),
|
||||
.clk_data_src (),
|
||||
.tx_data_src_tdata (),
|
||||
.tx_data_src_tready(),
|
||||
.tx_data_src_tvalid(),
|
||||
.hopping_freq (),
|
||||
.ad9361_tx_data_i (),
|
||||
.ad9361_tx_data_q (),
|
||||
.test (test),
|
||||
.hop_wait (2000)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,55 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module tb_add_prefix ();
|
||||
|
||||
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
|
||||
|
||||
always #1 clk <= ~clk;
|
||||
|
||||
reg start;
|
||||
wire ready;
|
||||
reg [31:0] data_in = 0;
|
||||
wire [31:0] data_out;
|
||||
wire data_out_valid;
|
||||
|
||||
initial begin
|
||||
#20 rst <= 1'b1;
|
||||
#20 rst <= 0;
|
||||
start <= 1'b0;
|
||||
#100 start <= 1'b1;
|
||||
#2 start <= 1'b0;
|
||||
end
|
||||
|
||||
add_prefix #(
|
||||
.WIDTH (32),
|
||||
.DATA_LEN (256),
|
||||
.PREFIX_LEN(8)
|
||||
) u_add_prefix (
|
||||
.clk (clk),
|
||||
.start (start),
|
||||
.ready (ready),
|
||||
.data_in (data_in),
|
||||
.data_in_ready (data_in_ready),
|
||||
.data_out (data_out),
|
||||
.data_out_valid(data_out_valid)
|
||||
);
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst == 1'b1) begin
|
||||
data_in <= 0;
|
||||
end
|
||||
else if (start || data_in > 0) begin
|
||||
data_in <= data_in + 32'd1;
|
||||
end
|
||||
else begin
|
||||
data_in <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,110 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
|
||||
module tb_enc_control ();
|
||||
|
||||
|
||||
reg clk = 1;
|
||||
reg rst = 1;
|
||||
|
||||
always #1 clk <= ~clk;
|
||||
|
||||
reg intr = 0;
|
||||
|
||||
|
||||
reg s_axis_fifo_tvalid = 1'b0;
|
||||
wire s_axis_fifo_tready;
|
||||
reg [31:0] s_axis_fifo_tdata;
|
||||
reg [31:0] data_src_count;
|
||||
wire enc_dout_intr;
|
||||
wire enc_dout_valid;
|
||||
wire [15:0] enc_dout;
|
||||
|
||||
reg fifo_enc_out_rd_en;
|
||||
wire [31:0] fifo_enc_out_dout_map;
|
||||
wire fifo_enc_out_empty;
|
||||
reg [ 1:0] cnt_div = 0;
|
||||
wire clk_div;
|
||||
|
||||
assign enc_dout_valid = ~fifo_enc_out_empty;
|
||||
assign clk_div = cnt_div[1];
|
||||
|
||||
|
||||
initial begin
|
||||
#100 rst <= 1'b0;
|
||||
end
|
||||
|
||||
reg [31:0] cnt_start;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_start <= 0;
|
||||
s_axis_fifo_tvalid <= 0;
|
||||
end
|
||||
else if (cnt_start < 70) begin
|
||||
cnt_start <= cnt_start + 1;
|
||||
s_axis_fifo_tvalid <= 0;
|
||||
end
|
||||
else if (cnt_start < 1500) begin
|
||||
cnt_start <= cnt_start + 1;
|
||||
s_axis_fifo_tvalid <= 1;
|
||||
end
|
||||
else if (cnt_start < 25000) begin
|
||||
cnt_start <= cnt_start + 1;
|
||||
s_axis_fifo_tvalid <= 0;
|
||||
end
|
||||
else if (cnt_start < 50000) begin
|
||||
cnt_start <= cnt_start + 1;
|
||||
s_axis_fifo_tvalid <= 1;
|
||||
end
|
||||
else begin
|
||||
s_axis_fifo_tvalid <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_src_count <= 0;
|
||||
s_axis_fifo_tdata <= $random();
|
||||
end
|
||||
else begin
|
||||
if (s_axis_fifo_tready) begin
|
||||
s_axis_fifo_tdata <= $random();
|
||||
end
|
||||
data_src_count <= 1000;
|
||||
end
|
||||
end
|
||||
|
||||
enc_control u_enc_control (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.s_axis_fifo_tvalid (s_axis_fifo_tvalid),
|
||||
.s_axis_fifo_tready (s_axis_fifo_tready),
|
||||
.s_axis_fifo_tdata (s_axis_fifo_tdata),
|
||||
.data_src_count (data_src_count),
|
||||
.fifo_enc_out_rd_clk (clk_div),
|
||||
.fifo_enc_out_rd_en (fifo_enc_out_rd_en),
|
||||
.fifo_enc_out_dout_map(fifo_enc_out_dout_map),
|
||||
.fifo_enc_out_empty (fifo_enc_out_empty)
|
||||
);
|
||||
|
||||
reg [1:0] cnt_rd;
|
||||
always @(posedge clk_div) begin
|
||||
if (rst) begin
|
||||
cnt_rd <= 0;
|
||||
end
|
||||
else begin
|
||||
if (enc_dout_valid) cnt_rd <= cnt_rd + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_div) begin
|
||||
if (cnt_rd == 2'b11) fifo_enc_out_rd_en <= 1;
|
||||
else fifo_enc_out_rd_en <= 0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
cnt_div <= cnt_div + 1;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,26 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/03/10 18:06:49
|
||||
// Design Name:
|
||||
// Module Name: tb_led
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_led(
|
||||
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,81 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/04/26 17:05:11
|
||||
// Design Name:
|
||||
// Module Name: tb_tdma
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_tdma ();
|
||||
|
||||
|
||||
|
||||
reg clk = 1;
|
||||
reg clk_tx = 1;
|
||||
reg rst = 1;
|
||||
always #1 clk <= ~clk;
|
||||
initial begin
|
||||
#1000 rst <= 1'b0;
|
||||
end
|
||||
|
||||
wire flag_frame_sync_m;
|
||||
reg flag_frame_sync_s = 0;
|
||||
wire intr_2ps_m;
|
||||
wire intr_2ps_s;
|
||||
wire tic_hop_m;
|
||||
wire tic_hop_s;
|
||||
wire tx_start_m;
|
||||
wire tx_start_s;
|
||||
|
||||
assign flag_frame_sync_m = 1'b0;
|
||||
|
||||
tdma #(
|
||||
.SLOT_LEN (1250000),
|
||||
.TIC_TO_PS_LEN (1200000),
|
||||
.TIC_FRAME_SYNC(42272)
|
||||
) u_tdma_master (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.flag_is_master (1'b1),
|
||||
.flag_frame_sync(flag_frame_sync_m),
|
||||
.intr_2ps (intr_2ps_m),
|
||||
// .tic_hop (tic_hop_m),
|
||||
.tx_start (tx_start_m)
|
||||
);
|
||||
|
||||
|
||||
tdma #(
|
||||
.SLOT_LEN (20000),
|
||||
.TIC_TO_PS_LEN (18000),
|
||||
.TIC_FRAME_SYNC(2000)
|
||||
) u_tdma_slave (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.flag_is_master (1'b0),
|
||||
.flag_frame_sync(flag_frame_sync_s),
|
||||
.intr_2ps (intr_2ps_s),
|
||||
// .tic_hop (tic_hop_s),
|
||||
.tx_start (tx_start_s)
|
||||
);
|
||||
|
||||
|
||||
initial begin
|
||||
#12000 flag_frame_sync_s <= 1'b1;
|
||||
#3 flag_frame_sync_s <= 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,193 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module tb_tx_with_enc ();
|
||||
|
||||
reg clk_crystal = 0; // 25MHz
|
||||
reg ad9361_rx_clk = 0; // 50MHz
|
||||
always #2 clk_crystal <= ~clk_crystal;
|
||||
always #1 ad9361_rx_clk <= ~ad9361_rx_clk;
|
||||
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// power on clock domain
|
||||
wire clk_poweron;
|
||||
(*max_fanout = 256 *)
|
||||
wire rst_sys;
|
||||
wire poweron_locked;
|
||||
|
||||
// ad9361 clock domain
|
||||
wire locked;
|
||||
wire clk_1x;
|
||||
wire clk_2x;
|
||||
wire clk_4x;
|
||||
|
||||
// emio
|
||||
wire [31:0] gpio_i;
|
||||
wire [31:0] gpio_o;
|
||||
wire [31:0] gpio_t;
|
||||
|
||||
// enc signal
|
||||
wire enc_fifo_rd_en;
|
||||
wire [31:0] enc_fifo_dout_map;
|
||||
wire enc_fifo_empty;
|
||||
|
||||
// tx bus
|
||||
wire clk_tx_data_src;
|
||||
wire [31:0] tx_data_src_count;
|
||||
wire [31:0] tx_data_src_tdata;
|
||||
wire tx_data_src_tready;
|
||||
wire tx_data_src_tvalid;
|
||||
|
||||
// baseband signal
|
||||
wire [11:0] ad9361_rx_data_i;
|
||||
wire [11:0] ad9361_rx_data_q;
|
||||
wire ad9361_rx_frame_i;
|
||||
wire ad9361_rx_frame_q;
|
||||
wire [11:0] ad9361_tx_data_i;
|
||||
wire [11:0] ad9361_tx_data_q;
|
||||
|
||||
// test
|
||||
wire tx_test_flag_ps;
|
||||
wire tx_test_flag;
|
||||
wire frame_sync_pulse;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign ad9361_tx_clk = clk_1x;
|
||||
assign rst_sys = ~poweron_locked;
|
||||
// ad9361 control
|
||||
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
|
||||
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
|
||||
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
|
||||
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
|
||||
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
clk_wiz_poweron u_clk_wiz_poweron (
|
||||
// Clock out ports
|
||||
.clk_poweron(clk_poweron), // output clk_poweron
|
||||
// Status and control signals
|
||||
.locked (poweron_locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_crystal(clk_crystal) // input clk_crystal
|
||||
);
|
||||
|
||||
// clock domain - ad9361 rx & tx
|
||||
clk_wiz_baseband u_clk_wiz_baseband (
|
||||
// Clock out ports
|
||||
.clk_1x (clk_1x), // output clk_1x
|
||||
.clk_2x (clk_2x), // output clk_2x
|
||||
.clk_4x (clk_4x), // output clk_4x
|
||||
// Status and control signals
|
||||
.locked (locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_src(ad9361_rx_clk) // input clk_src
|
||||
);
|
||||
|
||||
MM7020_BD_wrapper u_MM7020_BD_wrapper (
|
||||
.ad9361_spi_clk (ad9361_spi_clk),
|
||||
.ad9361_spi_csn (ad9361_spi_csn),
|
||||
.ad9361_spi_miso (ad9361_spi_miso),
|
||||
.ad9361_spi_mosi (ad9361_spi_mosi),
|
||||
.clk_ps (clk_poweron),
|
||||
.rst_ps (rst_sys),
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
// fixed io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
// gpio ps
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
// intr pl to ps
|
||||
.pl2ps_intr2 (intr_2ps),
|
||||
.pl2ps_intr3 (pl2ps_intr3),
|
||||
// tx fifo
|
||||
.tx_data_src_count (tx_data_src_count),
|
||||
.tx_data_src_tdata (tx_data_src_tdata),
|
||||
.tx_data_src_tready(tx_data_src_tready),
|
||||
.tx_data_src_tvalid(tx_data_src_tvalid),
|
||||
//tx flag
|
||||
.tx_test_flag (tx_test_flag_ps),
|
||||
// uart
|
||||
.uart_rx (uart_rx),
|
||||
.uart_tx (uart_tx)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
// ---- PHY layer logic start
|
||||
|
||||
enc_control u_enc_control (
|
||||
.clk (clk_poweron),
|
||||
.rst (rst_sys),
|
||||
.s_axis_fifo_tvalid (tx_data_src_tvalid),
|
||||
.s_axis_fifo_tready (tx_data_src_tready),
|
||||
.s_axis_fifo_tdata (tx_data_src_tdata),
|
||||
.data_src_count (tx_data_src_count),
|
||||
.fifo_enc_out_rd_clk (clk_1x),
|
||||
.fifo_enc_out_rd_en (enc_fifo_rd_en),
|
||||
.fifo_enc_out_dout_map(enc_fifo_dout_map),
|
||||
.fifo_enc_out_empty (enc_fifo_empty)
|
||||
);
|
||||
|
||||
|
||||
tdma #(
|
||||
.SLOT_LEN (1250000), // 50MHz--> 25ms
|
||||
.TIC_TO_PS_LEN (1200000),
|
||||
.TIC_FRAME_SYNC(42272)
|
||||
) u_tdma (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys),
|
||||
.flag_is_master (1'b0),
|
||||
.flag_frame_sync(frame_sync_pulse),
|
||||
.intr_2ps (intr_2ps),
|
||||
.tx_start (tx_start)
|
||||
);
|
||||
|
||||
|
||||
Transmitter u_Transmitter (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys),
|
||||
.speed_mode (0),
|
||||
.send_data_ready (send_data_ready),
|
||||
.send_start (tx_start),
|
||||
.send_over (send_over),
|
||||
.clk_data_src (clk_data_src),
|
||||
.tx_data_src_tdata (enc_fifo_dout_map),
|
||||
.tx_data_src_tready(enc_fifo_rd_en),
|
||||
.tx_data_src_tvalid(~enc_fifo_empty),
|
||||
.hopping_freq (),
|
||||
.ad9361_tx_data_i (ad9361_tx_data_i),
|
||||
.ad9361_tx_data_q (ad9361_tx_data_q),
|
||||
.test (tx_test_flag),
|
||||
.hop_wait (2000)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,90 @@
|
||||
`timescale 1ns / 1ps
|
||||
module tb_width_convert ();
|
||||
|
||||
|
||||
reg clk = 1;
|
||||
reg rst = 1;
|
||||
always #(2) clk <= ~clk;
|
||||
|
||||
initial begin
|
||||
#10 rst <= 1'b0;
|
||||
end
|
||||
|
||||
reg [31:0] data_in;
|
||||
reg data_in_valid;
|
||||
wire data_in_ready;
|
||||
wire data_out_valid;
|
||||
wire [ 0:0] data_out;
|
||||
|
||||
width_convert #(
|
||||
.INPUT_WIDTH (32),
|
||||
.OUTPUT_WIDTH(1)
|
||||
) u_width_convert (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.data_in_valid (data_in_valid),
|
||||
.data_in_ready (data_in_ready),
|
||||
.data_in (data_in),
|
||||
.data_out_valid(data_out_valid),
|
||||
.data_out (data_out)
|
||||
);
|
||||
|
||||
reg [5:0] cnt_startup;
|
||||
reg [3:0] cnt_data_in;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_startup <= 0;
|
||||
end
|
||||
else if (cnt_startup < 6'b111111) begin
|
||||
cnt_startup <= cnt_startup + 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [5:0] cnt_in;
|
||||
localparam CNT_IN_MAX = 32;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_in <= 0;
|
||||
end
|
||||
else if (cnt_in == CNT_IN_MAX) begin
|
||||
cnt_in <= 0;
|
||||
end
|
||||
else begin
|
||||
cnt_in <= cnt_in + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_in <= $random();
|
||||
cnt_data_in <= 0;
|
||||
end
|
||||
else if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX && cnt_data_in < 5) begin
|
||||
data_in <= $random();
|
||||
cnt_data_in <= cnt_data_in + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
// if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX) begin
|
||||
// data_in_valid <= 1;
|
||||
// end
|
||||
// else begin
|
||||
// data_in_valid <= 0;
|
||||
// end
|
||||
if (rst) begin
|
||||
data_in_valid <= 0;
|
||||
end
|
||||
else if (cnt_startup == 6'b111_111 && cnt_data_in < 5) begin
|
||||
data_in_valid <= 1;
|
||||
end
|
||||
else begin
|
||||
data_in_valid <= 0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user