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feat(tdma): update tdma logic

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This commit is contained in:
ZoroGH
2024-10-09 20:13:52 +08:00
parent 5e8d69a0b0
commit ae78b3092d
10 changed files with 699 additions and 459 deletions
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hdl/PAPR.v
+103 -58
View File
@@ -36,19 +36,32 @@ module PAPR #(
);
localparam SUM_WIDTH = 32;
localparam CNT_START = 16; // 32*4 / 8 * mag_valid signal is active high per 8 clk
localparam CNT_END = 44; // 88*4 / 8
localparam PULSE_PERIOD = 32;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg [MAG_WIDTH-1:0] vec_mag_reserved;
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 7:0] cnt;
wire [MAG_WIDTH-1:0] data_avg;
reg [SUM_WIDTH-1:0] data_sum;
assign data_avg = data_sum[SUM_WIDTH-1:10];
reg mag_valid_d1;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg frame_sync_d1;
always @(posedge clk) begin
mag_valid_d1 <= mag_valid;
if (rst) begin
vec_mag_d1 <= 'd0;
vec_mag_d2 <= 'd0;
vec_mag_d3 <= 'd0;
vec_mag_d1 <= 0;
vec_mag_d2 <= 0;
vec_mag_d3 <= 0;
end
else if (mag_valid) begin
vec_mag_d1 <= vec_mag;
@@ -61,9 +74,7 @@ module PAPR #(
vec_mag_d3 <= vec_mag_d3;
end
end
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 5:0] cnt;
shift_reg #(
.DATA_WIDTH(MAG_WIDTH),
@@ -77,10 +88,9 @@ module PAPR #(
);
reg [SUM_WIDTH-1:0] data_sum;
always @(posedge clk) begin
if (rst) begin
data_sum <= 'd0;
data_sum <= 0;
end
else begin
if (mag_valid) begin
@@ -92,59 +102,94 @@ module PAPR #(
end
end
wire [MAG_WIDTH-1:0] data_avg;
assign data_avg = data_sum[SUM_WIDTH-1:10];
// FSM
reg [2:0] cs = 0;
reg [2:0] ns = 0;
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
0: begin
if (mag_valid && vec_mag_1024 != 'd0 && data_avg != 'd0 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
ns = 1;
end
end
1: begin
if (cnt == CNT_START - 1) begin
ns = 2;
end
end
2: begin
if (vec_mag_reserved < {vec_mag[MAG_WIDTH-3:0], 2'b0}) begin
ns = 0;
end
else if (cnt == CNT_END - 1) begin
ns = 3;
end
end
3: begin
// generate pulse
ns = 4;
end
4: begin
if (cnt == PULSE_PERIOD - 1) begin
ns = 0;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
frame_sync <= 1'd0;
if (cs == 0 && ns == 1) begin
vec_mag_reserved <= vec_mag_d2;
end
else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
frame_sync <= 1'd1;
end
else if (cnt == 6'b111111) begin
frame_sync <= 1'd0;
end
else begin
frame_sync <= frame_sync;
else if (cs == 0) begin
vec_mag_reserved <= 0;
end
end
always @(posedge clk) begin
if (cs == 1 || cs == 2) begin
if (mag_valid) begin
cnt <= cnt + 1;
end
end
else if (cs == 4) begin
cnt <= cnt + 1;
end
else if (cs == 0) begin
cnt <= 0;
end
end
always @(posedge clk) begin
frame_sync_pulse <= (cs == 3);
if (cs == 4) begin
frame_sync <= 1;
end
else begin
frame_sync <= frame_sync;
frame_sync <= 0;
end
end
always @(posedge clk) begin
frame_sync_d1 <= frame_sync;
if (frame_sync && ~frame_sync_d1) begin
frame_sync_pulse <= 1'd1;
end
else begin
frame_sync_pulse <= 1'd0;
end
end
always @(posedge clk) begin
if (rst) begin
cnt <= 6'd0;
end
else if (frame_sync && mag_valid_d1) begin
cnt <= cnt + 6'd1;
end
else if (cnt == 6'b111111) begin
cnt <= 6'd0;
end
end
ila_frame_sync u_ila_frame_sync (
.clk (clk), // input wire clk
.probe0(vec_mag), // input wire [21:0] probe0
.probe1(data_avg), // input wire [21:0] probe0
.probe2(frame_sync) // input wire [0:0] probe2
);
// ila_frame_sync u_ila_frame_sync (
// .clk (clk), // input wire clk
// .probe0(vec_mag), // input wire [21:0] probe0
// .probe1(data_avg), // input wire [21:0] probe0
// .probe2(cs), // input wire [2:0] probe2
// .probe3(cnt), // input wire [7:0] probe2
// .probe4(frame_sync), // input wire [0:0] probe2
// .probe5(vec_mag_reserved) // input wire [21:0] probe2
// );
hdl/RecvTop.v
+63 -30
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@@ -46,7 +46,9 @@ module RecvTop (
output wire [31:0] rx_data_src_fifo_tdata,
output wire rx_data_src_fifo_tlast,
input wire rx_data_src_fifo_tready,
output wire rx_data_src_fifo_tvalid
output wire rx_data_src_fifo_tvalid,
// ber
output reg err_flag_pos
);
wire rst_TimeSync;
@@ -274,7 +276,7 @@ module RecvTop (
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -302,7 +304,7 @@ module RecvTop (
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
if (frame_sync_pulse && ~flag_frame_sync) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
@@ -314,6 +316,8 @@ module RecvTop (
end
end
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
always @(posedge clk) begin
if (rst) begin
flag_frame_sync <= 0;
@@ -354,6 +358,19 @@ module RecvTop (
end
end
wire [9:0] dagc_data_in_i;
wire [9:0] dagc_data_in_q;
shift_register_64 u_shift_register_64_i (
.D (mf_data_interp4_i[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_i) // output wire [9 : 0] Q
);
shift_register_64 u_shift_register_64_q (
.D (mf_data_interp4_q[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_q) // output wire [9 : 0] Q
);
DAGC_v2 DAGC_v2 (
.clk (clk),
@@ -362,10 +379,10 @@ module RecvTop (
.framesync_d0 (flag_frame_sync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(mf_data_interp4_i[29-:10]), // input,
.matchfilterout_q(mf_data_interp4_q[29-:10]), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
.matchfilterout_i(dagc_data_in_i), // input,
.matchfilterout_q(dagc_data_in_q), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
// debug
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
@@ -502,7 +519,7 @@ module RecvTop (
extract_mac_frame u_extract_mac_frame (
.clk (clk_2x),
.rst (rst2 || rst_frame_sync || ~flag_frame_sync),
.rst (rst2 || rst_frame_sync),
.ldpc_dec_out_start (LDPC_SyncOut),
.ldpc_dec_out_valid (LDPC_Rdy),
.ldpc_dec_out_data (LDPC_Dout),
@@ -512,6 +529,22 @@ module RecvTop (
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
);
reg err_flag;
reg err_flag_d1;
// reg err_flag_pos;
always @(posedge clk) begin
if (rst2 || rst_frame_sync) begin
err_flag <= 0;
end
else if (total_frames == 105 && bad_frames > 0) begin
err_flag <= 1;
end
err_flag_d1 <= err_flag;
err_flag_pos <= err_flag & ~err_flag_d1;
end
@@ -562,28 +595,28 @@ module RecvTop (
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (dagc_data_in_i), // width: 12
.probe3 (dagc_data_in_q), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
);
hdl/descrambler.v
-161
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@@ -1,161 +0,0 @@
// * Engineer:
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
// * *************************************************** *
// * Update Date:
// * NOTE :
module scrambler #(
parameter ILA_ON = 0
) (
input clk,
input rst_n,
// s_axis_stream
input [31:0] s_axis_tdata,
input s_axis_tvalid,
output reg s_axis_tready,
input s_axis_tlast,
input [31:0] s_axis_rd_data_count,
// m_axis_stream
output reg [31:0] m_axis_tdata,
output reg m_axis_tvalid,
input m_axis_tready,
output reg m_axis_tlast
);
// ******** Wire & Reg ********
wire rst;
reg [ 2:0] addr_scramble = 0;
reg [ 2:0] addr_scramble_d1 = 0;
reg [ 2:0] addr_scramble_d2 = 0;
wire [31:0] data_scramble_mask;
reg [ 3:0] cnt_in;
reg [31:0] s_axis_tdata_d1;
reg [31:0] s_axis_tdata_d2;
reg s_axis_tready_d1;
reg s_axis_tlast_d1;
// fsm
reg [ 1:0] cs = 0;
reg [ 1:0] ns = 0;
localparam S_IDLE = 0;
localparam S_WORKING = 1;
// ******** Assingment ********
assign rst = ~rst_n;
// ******** Logic Block ********
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 16) begin
ns = S_WORKING;
end
end
S_WORKING: begin
if (addr_scramble_d2 == 3'h7) begin
ns = S_IDLE;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
addr_scramble <= 0;
end
else begin
addr_scramble <= addr_scramble + 1;
end
addr_scramble_d1 <= addr_scramble;
addr_scramble_d2 <= addr_scramble_d1;
end
always @(posedge clk) begin
if (cs == S_WORKING) begin
m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
end
else begin
m_axis_tdata <= 0;
end
end
always @(posedge clk) begin
if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
s_axis_tready <= 1;
end
else begin
s_axis_tready <= 0;
end
end
always @(posedge clk) begin
s_axis_tdata_d1 <= s_axis_tdata;
s_axis_tready_d1 <= s_axis_tready;
m_axis_tvalid <= s_axis_tready_d1;
s_axis_tlast_d1 <= s_axis_tlast;
m_axis_tlast <= s_axis_tlast_d1;
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
cnt_in <= 0;
end
else if (cs == S_WORKING && cnt_in < 4'd8) begin
cnt_in <= cnt_in + 1;
end
end
// ******** Inst ********
bram_scramble u_bram_scramble (
.clka (clk), // input wire clka
.addra(addr_scramble), // input wire [2 : 0] addra
.douta(data_scramble_mask) // output wire [31 : 0] douta
);
// ******** Debug ********
generate
if (ILA_ON)
ila_scrambler u_ila_scrambler (
.clk (clk), // input wire clk
.probe0(s_axis_tvalid), // input wire [0:0] probe0
.probe1(s_axis_tready), // input wire [0:0] probe1
.probe2(s_axis_tdata), // input wire [31:0] probe2
.probe3(s_axis_tlast), // input wire [0:0] probe3
.probe4(m_axis_tvalid), // input wire [0:0] probe4
.probe5(m_axis_tready), // input wire [0:0] probe5
.probe6(m_axis_tdata), // input wire [31:0] probe6
.probe7(m_axis_tlast), // input wire [0:0] probe7
.probe8(data_scramble_mask) // input wire [31:0] probe8
);
endgenerate
endmodule
hdl/net_city.v
+9 -9
View File
@@ -12,8 +12,8 @@ module net_city (
output reg [07:0] recv_id = 8'd0,
// rx signal
input frame_sync,
input recv_net_data_nd,
input [63:0] recv_net_data,
// input recv_net_data_nd,
// input [63:0] recv_net_data,
// net parameter
input [31:0] frame_sync_time,
input [07:0] id_num,
@@ -215,13 +215,13 @@ module net_city (
// if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
recv_id <= recv_net_data[63:56];
recv_video_id01 <= recv_net_data[55:48];
recv_video_id02 <= recv_net_data[47:40];
recv_video_id03 <= recv_net_data[39:32];
recv_connect_node <= recv_net_data[31:24];
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// recv_id <= recv_net_data[63:56];
// recv_video_id01 <= recv_net_data[55:48];
// recv_video_id02 <= recv_net_data[47:40];
// recv_video_id03 <= recv_net_data[39:32];
// recv_connect_node <= recv_net_data[31:24];
// end
// else begin
// state_net <= 8'd200;
hdl/phy_control.v
+24 -9
View File
@@ -71,7 +71,10 @@ module phy_control #(
// tdma parameters
output wire tdma_flag_is_master,
output wire [31:0] tdma_slot_len,
output wire [31:0] tdma_tic_2_ps
output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id
//--- ADD YOUR OWN PORTS END
);
@@ -339,12 +342,16 @@ module phy_control #(
localparam integer PHY_SR = 'h00000004 >> 2; // RW
localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
// Register definitions
reg [31:0] phy_cr_reg = 32'h0;
reg [31:0] phy_sr_reg = 32'h0;
reg [31:0] tdma_slot_len_reg = 32'h0;
reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0;
// Register Reading
always @(posedge local_clk) begin
@@ -369,25 +376,33 @@ module phy_control #(
PHY_SR: phy_sr_reg <= up_wdata_s;
TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
endcase
end
else begin
// self logic
if (tdma_recv_id_reg[8] == 1) begin
tdma_recv_id_reg[8] <= 0;
end
end
end
end
// control reg definition
assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_tx_iq_reverse = phy_cr_reg[2];
assign phy_rx_iq_reverse = phy_cr_reg[3];
assign tdma_flag_is_master = phy_cr_reg[4];
assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_tx_iq_reverse = phy_cr_reg[2];
assign phy_rx_iq_reverse = phy_cr_reg[3];
assign tdma_flag_is_master = phy_cr_reg[4];
// tdma
assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_id_cfg = tdma_id_cfg_reg;
// received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
vio_phy_param u_vio_phy_param (
.clk (local_clk),
hdl/system_top.v
+136 -96
View File
@@ -122,6 +122,9 @@ module system_top (
wire tdma_flag_is_master;
wire [31:0] tdma_slot_len;
wire [31:0] tdma_tic_2_ps;
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
// tx signal
wire frame_sync_pulse;
@@ -134,6 +137,15 @@ module system_top (
wire tx_start_vio;
reg tx_start_vio_d1;
wire tx_start_vio_pos;
// rx
wire rx_err_flag_pos;
wire rf_io3_d1_12db;
wire rf_io4_d2_6db;
wire rf_io0_d3_18db;
wire rf_io1_d4_12db;
wire rf_io2_trx; // 1 for tx on, 0 for rx
// vio
wire rst_manual;
@@ -157,6 +169,13 @@ module system_top (
assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// gpio rf control
assign rf_io0_d3_18db = rf_gpio[0];
assign rf_io1_d4_12db = rf_gpio[1];
assign rf_io2_trx = rf_gpio[2];
assign rf_io3_d1_12db = rf_gpio[3];
assign rf_io4_d2_6db = rf_gpio[4];
// ******** Logic Block ********
@@ -184,78 +203,89 @@ module system_top (
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl_tx_intr (intr_2ps | intr_2ps_vio_pos),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_2x),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
// phy control signal
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.clk_rx_data_src_fifo (clk_2x),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
// phy clock and rst to ps
.clk_phy (clk_1x),
.rst_phy_n (~rst_sys),
// phy control signal , under clk_1x domain
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_frame_sync (frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]),
.local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// tdma u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (tdma_flag_is_master),
// .flag_frame_sync(frame_sync_pulse),
// .tdma_slot_len (tdma_slot_len[23:0]),
// .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
@@ -305,7 +335,7 @@ module system_top (
.rst (rst_sys | phy_rst),
.speed_mode (2),
.send_data_ready (send_data_ready),
.send_start (tx_start | tx_start_vio_pos),
.send_start (tx_start),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
@@ -322,7 +352,7 @@ module system_top (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst | rx_rst_vio),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
@@ -340,7 +370,8 @@ module system_top (
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.err_flag_pos (rx_err_flag_pos)
);
@@ -369,41 +400,50 @@ module system_top (
.tx_frame (ad9361_tx_frame)
);
// ******** CDC ********
// // ******** CDC ********
// ******** Debug ********
// // ******** Debug ********
// ila_ad9361_rx u_ila_ad9361_rx (
// .clk (ad9361_rx_clk),
// .probe0(ad9361_rx_data_i),
// .probe1(ad9361_rx_data_q),
// .probe2(u_RecvTop.flag_mgc_done)
// // ila_ad9361_rx u_ila_ad9361_rx (
// // .clk (ad9361_rx_clk),
// // .probe0(ad9361_rx_data_i),
// // .probe1(ad9361_rx_data_q),
// // .probe2(u_RecvTop.flag_mgc_done)
// // );
// // ila_ad9361_tx u_ila_ad9361_tx (
// // .clk (ad9361_tx_clk), // input wire clk
// // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// // );
// // assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// // always @(posedge clk_1x) begin
// // tx_start_vio_d1 <= tx_start_vio;
// // end
// // assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// // always @(posedge clk_1x) begin
// // intr_2ps_vio_d1 <= intr_2ps_vio;
// // end
// vio_system_top u_vio_system_top (
// .clk (clk_1x),
// .probe_out0(node_id),
// .probe_out1(max_slot_num),
// .probe_out2(rst_manual)
// );
// ila_ad9361_tx u_ila_ad9361_tx (
// .clk (ad9361_tx_clk), // input wire clk
// .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// );
assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
always @(posedge clk_1x) begin
tx_start_vio_d1 <= tx_start_vio;
end
assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
always @(posedge clk_1x) begin
intr_2ps_vio_d1 <= intr_2ps_vio;
end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(rx_rst_vio),
.probe_out1(tx_start_vio),
.probe_out2(intr_2ps_vio)
vio_rf u_vio_rf (
.clk (clk_poweron),
.probe_out0(rf_io2_trx),
.probe_out1(rf_io3_d1_12db),
.probe_out2(rf_io4_d2_6db),
.probe_out3(rf_io0_d3_18db),
.probe_out4(rf_io1_d4_12db)
);
endmodule
hdl/tdma.v
+126 -30
View File
@@ -14,52 +14,144 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter TIC_FRAME_SYNC = 42344
parameter TIC_FRAME_SYNC = 44432
) (
input clk,
input rst,
input flag_is_master,
// PHY parameter
input flag_frame_sync,
// general parameter, update only once
input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num,
input wire [ 7:0] local_id, // ID number for this device
// update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
input wire [ 7:0] recevied_cur_slot_id,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ********
reg flag_is_tx_slot;
reg [23:0] cnt;
reg flag_next_slot_is_tx_slot;
reg [23:0] cnt_tdma_slot_len;
reg [ 7:0] cur_slot_id;
wire flag_end_of_one_slot; // the last period of the slot
wire [23:0] tdma_tic_frame_sync_vio;
// fsm
localparam S_IDLE = 0;
localparam S_RX = 1;
localparam S_TX = 2;
reg [1:0] cs = 0;
reg [1:0] ns = 0;
// ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10);
assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1);
assign flag_end_of_one_slot = (cnt_tdma_slot_len == tdma_slot_len - 1);
assign tx_start = (cs == S_TX) & (cnt_tdma_slot_len == 16'd10);
assign intr_2ps = flag_next_slot_is_tx_slot & (cnt_tdma_slot_len == tdma_tic_2_ps - 1);
// ******** Logic Block ********
// fsm
always @(posedge clk) begin
if (rst) begin
cs <= S_IDLE;
end
else begin
cs <= ns;
end
end
// conditional transition
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
// if this device is master node, ps should first send one packet to the fifo
if (local_id == 1) begin
ns = S_TX;
end
else if (recevied_cur_slot_id_valid) begin
ns = S_RX;
end
end
S_RX: begin
if (flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_TX;
end
end
S_TX: begin
if (~flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_RX;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
cnt_tdma_slot_len <= 0;
end
else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_tic_frame_sync_vio;
end
else begin
if (!flag_is_master && flag_frame_sync) begin
// slave update cnt
cnt <= TIC_FRAME_SYNC;
// if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
// cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
// end
// else begin
// cnt_tdma_slot_len <= 0;
// end
if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0;
end
else begin
// master
if (cnt < tdma_slot_len - 1) begin
cnt <= cnt + 1;
cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
end
end
end
always @(*) begin
if (cs == S_TX || cnt_tdma_slot_len <= 10) begin
rx_rst <= 1;
end
else begin
rx_rst <= 0;
end
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
if (ns == S_TX) begin // indicating master node
cur_slot_id <= 1;
end
else if (recevied_cur_slot_id_valid) begin // from ps update, first sync, indicating slave
cur_slot_id <= recevied_cur_slot_id;
end
else begin
cur_slot_id <= 0;
end
end
else begin
if (recevied_cur_slot_id_valid) begin // from ps update
cur_slot_id <= recevied_cur_slot_id;
end
else if (flag_end_of_one_slot) begin // at the changing moment
if (cur_slot_id == tdma_slot_num) begin
cur_slot_id <= 1;
end
else begin
cnt <= 0;
cur_slot_id <= cur_slot_id + 1;
end
end
end
@@ -67,11 +159,11 @@ module tdma #(
always @(posedge clk) begin
if (flag_is_master) begin
rx_rst <= 1;
if (local_id == 1) begin
flag_next_slot_is_tx_slot <= (cur_slot_id == tdma_slot_num);
end
else begin
rx_rst <= flag_is_master | (cnt <= 16'd4);
flag_next_slot_is_tx_slot <= (cur_slot_id + 1 == local_id);
end
end
@@ -80,20 +172,24 @@ module tdma #(
// ******** Debug ********
vio_tdma u_vio_tdma (
.clk (clk),
.probe_in0(tdma_slot_len),
.probe_in1(tdma_tic_2_ps),
.probe_in2(flag_is_master)
.clk (clk),
.probe_in0 (tdma_slot_len),
.probe_in1 (tdma_tic_2_ps),
.probe_in2 (tdma_slot_num),
.probe_in3 (local_id),
.probe_out0(tdma_tic_frame_sync_vio)
);
ila_mac_layer u_ila_mac_layer (
.clk (clk),
.probe0(cnt), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(flag_is_master), // width: 1
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync) // width: 1
.probe0(cnt_tdma_slot_len), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(cur_slot_id), // width: 8
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync), // width: 1
.probe6(recevied_cur_slot_id), // width: 8
.probe7(recevied_cur_slot_id_valid) // width: 1
);