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feat(tdma): update tdma logic

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ZoroGH
2024-10-09 20:13:52 +08:00
parent 5e8d69a0b0
commit ae78b3092d
10 changed files with 699 additions and 459 deletions
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hdl/RecvTop.v
+63 -30
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@@ -46,7 +46,9 @@ module RecvTop (
output wire [31:0] rx_data_src_fifo_tdata,
output wire rx_data_src_fifo_tlast,
input wire rx_data_src_fifo_tready,
output wire rx_data_src_fifo_tvalid
output wire rx_data_src_fifo_tvalid,
// ber
output reg err_flag_pos
);
wire rst_TimeSync;
@@ -274,7 +276,7 @@ module RecvTop (
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -302,7 +304,7 @@ module RecvTop (
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
if (frame_sync_pulse && ~flag_frame_sync) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
@@ -314,6 +316,8 @@ module RecvTop (
end
end
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
always @(posedge clk) begin
if (rst) begin
flag_frame_sync <= 0;
@@ -354,6 +358,19 @@ module RecvTop (
end
end
wire [9:0] dagc_data_in_i;
wire [9:0] dagc_data_in_q;
shift_register_64 u_shift_register_64_i (
.D (mf_data_interp4_i[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_i) // output wire [9 : 0] Q
);
shift_register_64 u_shift_register_64_q (
.D (mf_data_interp4_q[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_q) // output wire [9 : 0] Q
);
DAGC_v2 DAGC_v2 (
.clk (clk),
@@ -362,10 +379,10 @@ module RecvTop (
.framesync_d0 (flag_frame_sync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(mf_data_interp4_i[29-:10]), // input,
.matchfilterout_q(mf_data_interp4_q[29-:10]), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
.matchfilterout_i(dagc_data_in_i), // input,
.matchfilterout_q(dagc_data_in_q), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
// debug
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
@@ -502,7 +519,7 @@ module RecvTop (
extract_mac_frame u_extract_mac_frame (
.clk (clk_2x),
.rst (rst2 || rst_frame_sync || ~flag_frame_sync),
.rst (rst2 || rst_frame_sync),
.ldpc_dec_out_start (LDPC_SyncOut),
.ldpc_dec_out_valid (LDPC_Rdy),
.ldpc_dec_out_data (LDPC_Dout),
@@ -512,6 +529,22 @@ module RecvTop (
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
);
reg err_flag;
reg err_flag_d1;
// reg err_flag_pos;
always @(posedge clk) begin
if (rst2 || rst_frame_sync) begin
err_flag <= 0;
end
else if (total_frames == 105 && bad_frames > 0) begin
err_flag <= 1;
end
err_flag_d1 <= err_flag;
err_flag_pos <= err_flag & ~err_flag_d1;
end
@@ -562,28 +595,28 @@ module RecvTop (
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (dagc_data_in_i), // width: 12
.probe3 (dagc_data_in_q), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
);