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feat(tdma): update tdma logic

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ZoroGH
2024-10-09 20:13:52 +08:00
parent 5e8d69a0b0
commit ae78b3092d
10 changed files with 699 additions and 459 deletions
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hdl/net_city.v
+9 -9
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@@ -12,8 +12,8 @@ module net_city (
output reg [07:0] recv_id = 8'd0,
// rx signal
input frame_sync,
input recv_net_data_nd,
input [63:0] recv_net_data,
// input recv_net_data_nd,
// input [63:0] recv_net_data,
// net parameter
input [31:0] frame_sync_time,
input [07:0] id_num,
@@ -215,13 +215,13 @@ module net_city (
// if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
recv_id <= recv_net_data[63:56];
recv_video_id01 <= recv_net_data[55:48];
recv_video_id02 <= recv_net_data[47:40];
recv_video_id03 <= recv_net_data[39:32];
recv_connect_node <= recv_net_data[31:24];
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// recv_id <= recv_net_data[63:56];
// recv_video_id01 <= recv_net_data[55:48];
// recv_video_id02 <= recv_net_data[47:40];
// recv_video_id03 <= recv_net_data[39:32];
// recv_connect_node <= recv_net_data[31:24];
// end
// else begin
// state_net <= 8'd200;