ZoroGH/MM7020
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases 3 Wiki Activity

feat(tdma): update tdma logic

Browse Source
This commit is contained in:
ZoroGH
2024-10-09 20:13:52 +08:00
parent 5e8d69a0b0
commit ae78b3092d
10 changed files with 699 additions and 459 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hdl/system_top.v
+136 -96
View File
@@ -122,6 +122,9 @@ module system_top (
wire tdma_flag_is_master;
wire [31:0] tdma_slot_len;
wire [31:0] tdma_tic_2_ps;
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
// tx signal
wire frame_sync_pulse;
@@ -134,6 +137,15 @@ module system_top (
wire tx_start_vio;
reg tx_start_vio_d1;
wire tx_start_vio_pos;
// rx
wire rx_err_flag_pos;
wire rf_io3_d1_12db;
wire rf_io4_d2_6db;
wire rf_io0_d3_18db;
wire rf_io1_d4_12db;
wire rf_io2_trx; // 1 for tx on, 0 for rx
// vio
wire rst_manual;
@@ -157,6 +169,13 @@ module system_top (
assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// gpio rf control
assign rf_io0_d3_18db = rf_gpio[0];
assign rf_io1_d4_12db = rf_gpio[1];
assign rf_io2_trx = rf_gpio[2];
assign rf_io3_d1_12db = rf_gpio[3];
assign rf_io4_d2_6db = rf_gpio[4];
// ******** Logic Block ********
@@ -184,78 +203,89 @@ module system_top (
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl_tx_intr (intr_2ps | intr_2ps_vio_pos),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_2x),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
// phy control signal
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.clk_rx_data_src_fifo (clk_2x),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
// phy clock and rst to ps
.clk_phy (clk_1x),
.rst_phy_n (~rst_sys),
// phy control signal , under clk_1x domain
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_frame_sync (frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]),
.local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// tdma u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (tdma_flag_is_master),
// .flag_frame_sync(frame_sync_pulse),
// .tdma_slot_len (tdma_slot_len[23:0]),
// .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
@@ -305,7 +335,7 @@ module system_top (
.rst (rst_sys | phy_rst),
.speed_mode (2),
.send_data_ready (send_data_ready),
.send_start (tx_start | tx_start_vio_pos),
.send_start (tx_start),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
@@ -322,7 +352,7 @@ module system_top (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst | rx_rst_vio),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
@@ -340,7 +370,8 @@ module system_top (
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.err_flag_pos (rx_err_flag_pos)
);
@@ -369,41 +400,50 @@ module system_top (
.tx_frame (ad9361_tx_frame)
);
// ******** CDC ********
// // ******** CDC ********
// ******** Debug ********
// // ******** Debug ********
// ila_ad9361_rx u_ila_ad9361_rx (
// .clk (ad9361_rx_clk),
// .probe0(ad9361_rx_data_i),
// .probe1(ad9361_rx_data_q),
// .probe2(u_RecvTop.flag_mgc_done)
// // ila_ad9361_rx u_ila_ad9361_rx (
// // .clk (ad9361_rx_clk),
// // .probe0(ad9361_rx_data_i),
// // .probe1(ad9361_rx_data_q),
// // .probe2(u_RecvTop.flag_mgc_done)
// // );
// // ila_ad9361_tx u_ila_ad9361_tx (
// // .clk (ad9361_tx_clk), // input wire clk
// // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// // );
// // assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// // always @(posedge clk_1x) begin
// // tx_start_vio_d1 <= tx_start_vio;
// // end
// // assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// // always @(posedge clk_1x) begin
// // intr_2ps_vio_d1 <= intr_2ps_vio;
// // end
// vio_system_top u_vio_system_top (
// .clk (clk_1x),
// .probe_out0(node_id),
// .probe_out1(max_slot_num),
// .probe_out2(rst_manual)
// );
// ila_ad9361_tx u_ila_ad9361_tx (
// .clk (ad9361_tx_clk), // input wire clk
// .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// );
assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
always @(posedge clk_1x) begin
tx_start_vio_d1 <= tx_start_vio;
end
assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
always @(posedge clk_1x) begin
intr_2ps_vio_d1 <= intr_2ps_vio;
end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(rx_rst_vio),
.probe_out1(tx_start_vio),
.probe_out2(intr_2ps_vio)
vio_rf u_vio_rf (
.clk (clk_poweron),
.probe_out0(rf_io2_trx),
.probe_out1(rf_io3_d1_12db),
.probe_out2(rf_io4_d2_6db),
.probe_out3(rf_io0_d3_18db),
.probe_out4(rf_io1_d4_12db)
);
endmodule