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feat(tdma): update tdma logic

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ZoroGH
2024-10-09 20:13:52 +08:00
parent 5e8d69a0b0
commit ae78b3092d
10 changed files with 699 additions and 459 deletions
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hdl/tdma.v
+126 -30
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@@ -14,52 +14,144 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter TIC_FRAME_SYNC = 42344
parameter TIC_FRAME_SYNC = 44432
) (
input clk,
input rst,
input flag_is_master,
// PHY parameter
input flag_frame_sync,
// general parameter, update only once
input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num,
input wire [ 7:0] local_id, // ID number for this device
// update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
input wire [ 7:0] recevied_cur_slot_id,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ********
reg flag_is_tx_slot;
reg [23:0] cnt;
reg flag_next_slot_is_tx_slot;
reg [23:0] cnt_tdma_slot_len;
reg [ 7:0] cur_slot_id;
wire flag_end_of_one_slot; // the last period of the slot
wire [23:0] tdma_tic_frame_sync_vio;
// fsm
localparam S_IDLE = 0;
localparam S_RX = 1;
localparam S_TX = 2;
reg [1:0] cs = 0;
reg [1:0] ns = 0;
// ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10);
assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1);
assign flag_end_of_one_slot = (cnt_tdma_slot_len == tdma_slot_len - 1);
assign tx_start = (cs == S_TX) & (cnt_tdma_slot_len == 16'd10);
assign intr_2ps = flag_next_slot_is_tx_slot & (cnt_tdma_slot_len == tdma_tic_2_ps - 1);
// ******** Logic Block ********
// fsm
always @(posedge clk) begin
if (rst) begin
cs <= S_IDLE;
end
else begin
cs <= ns;
end
end
// conditional transition
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
// if this device is master node, ps should first send one packet to the fifo
if (local_id == 1) begin
ns = S_TX;
end
else if (recevied_cur_slot_id_valid) begin
ns = S_RX;
end
end
S_RX: begin
if (flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_TX;
end
end
S_TX: begin
if (~flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_RX;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
cnt_tdma_slot_len <= 0;
end
else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_tic_frame_sync_vio;
end
else begin
if (!flag_is_master && flag_frame_sync) begin
// slave update cnt
cnt <= TIC_FRAME_SYNC;
// if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
// cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
// end
// else begin
// cnt_tdma_slot_len <= 0;
// end
if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0;
end
else begin
// master
if (cnt < tdma_slot_len - 1) begin
cnt <= cnt + 1;
cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
end
end
end
always @(*) begin
if (cs == S_TX || cnt_tdma_slot_len <= 10) begin
rx_rst <= 1;
end
else begin
rx_rst <= 0;
end
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
if (ns == S_TX) begin // indicating master node
cur_slot_id <= 1;
end
else if (recevied_cur_slot_id_valid) begin // from ps update, first sync, indicating slave
cur_slot_id <= recevied_cur_slot_id;
end
else begin
cur_slot_id <= 0;
end
end
else begin
if (recevied_cur_slot_id_valid) begin // from ps update
cur_slot_id <= recevied_cur_slot_id;
end
else if (flag_end_of_one_slot) begin // at the changing moment
if (cur_slot_id == tdma_slot_num) begin
cur_slot_id <= 1;
end
else begin
cnt <= 0;
cur_slot_id <= cur_slot_id + 1;
end
end
end
@@ -67,11 +159,11 @@ module tdma #(
always @(posedge clk) begin
if (flag_is_master) begin
rx_rst <= 1;
if (local_id == 1) begin
flag_next_slot_is_tx_slot <= (cur_slot_id == tdma_slot_num);
end
else begin
rx_rst <= flag_is_master | (cnt <= 16'd4);
flag_next_slot_is_tx_slot <= (cur_slot_id + 1 == local_id);
end
end
@@ -80,20 +172,24 @@ module tdma #(
// ******** Debug ********
vio_tdma u_vio_tdma (
.clk (clk),
.probe_in0(tdma_slot_len),
.probe_in1(tdma_tic_2_ps),
.probe_in2(flag_is_master)
.clk (clk),
.probe_in0 (tdma_slot_len),
.probe_in1 (tdma_tic_2_ps),
.probe_in2 (tdma_slot_num),
.probe_in3 (local_id),
.probe_out0(tdma_tic_frame_sync_vio)
);
ila_mac_layer u_ila_mac_layer (
.clk (clk),
.probe0(cnt), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(flag_is_master), // width: 1
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync) // width: 1
.probe0(cnt_tdma_slot_len), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(cur_slot_id), // width: 8
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync), // width: 1
.probe6(recevied_cur_slot_id), // width: 8
.probe7(recevied_cur_slot_id_valid) // width: 1
);