ZoroGH/MM7020
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases 3 Wiki Activity

feat(tdma): update tdma logic

Browse Source
This commit is contained in:
ZoroGH
2024-10-09 20:13:52 +08:00
parent 5e8d69a0b0
commit ae78b3092d
10 changed files with 699 additions and 459 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sim/tb_tdma.v
+67 -12
View File
@@ -29,18 +29,73 @@ module tb_tdma ();
#10 rst <= 1'b0;
end
tdma #(
.SLOT_LEN (625000), // 50MHz--> 15ms
.TIC_TO_PS_LEN (575000),
.TIC_FRAME_SYNC(42344)
) u_tdma (
.clk (clk),
.rst (rst),
.flag_is_master (1),
.flag_frame_sync(0),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
reg [7:0] local_id = 0;
initial begin
#20 local_id <= 1;
end
reg flag_frame_sync = 0;
reg recevied_cur_slot_id_valid = 0;
reg [7:0] recevied_cur_slot_id = 0;
tdma u_tdma_master (
.clk (clk),
.rst (rst),
.flag_frame_sync (flag_frame_sync),
.tdma_slot_len (24'd7500),
.tdma_tic_2_ps (24'd6000),
.tdma_slot_num (8'd4),
.local_id (local_id),
.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid),
.recevied_cur_slot_id (recevied_cur_slot_id),
.intr_2ps (),
.tx_start (),
.rx_rst ()
);
reg flag_frame_sync_slave = 0;
reg recevied_cur_slot_id_valid_slave = 0;
reg [7:0] recevied_cur_slot_id_slave = 7;
reg [7:0] local_id_slave = 10;
reg [7:0] cnt = 0;
always @(posedge clk) begin
if (cnt < 8'hFF) begin
cnt <= cnt + 1;
end
end
always @(posedge clk) begin
if (cnt == 8'hF3) begin
flag_frame_sync_slave <= 1;
end
else begin
flag_frame_sync_slave <= 0;
end
if (cnt == 8'hFE) begin
recevied_cur_slot_id_valid_slave <= 1;
end
else begin
recevied_cur_slot_id_valid_slave <= 0;
end
end
tdma u_tdma_slave (
.clk (clk),
.rst (rst),
.flag_frame_sync (flag_frame_sync_slave),
.tdma_slot_len (24'd7500),
.tdma_tic_2_ps (24'd6000),
.tdma_slot_num (8'd10),
.local_id (local_id_slave),
.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid_slave),
.recevied_cur_slot_id (recevied_cur_slot_id_slave),
.intr_2ps (),
.tx_start (),
.rx_rst ()
);
endmodule