merge(sys): merge tdma update

hdl/phy_control.v

@@ -74,7 +74,8 @@ module phy_control #(
     output wire [31:0] tdma_tic_2_ps,
     output wire [31:0] tdma_id_cfg,
     output wire        tdma_recv_cur_slot_id_valid,
-    output wire [ 7:0] tdma_recv_cur_slot_id
+    output wire [ 7:0] tdma_recv_cur_slot_id,
+    output wire [31:0] tdma_frame_sync_tic
 
     //--- ADD YOUR OWN PORTS END
 );
@@ -344,6 +345,7 @@ module phy_control #(
     localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
     localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
     localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
+    localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
 
     // Register definitions
     reg [31:0] phy_cr_reg = 32'h0;
@@ -352,6 +354,7 @@ module phy_control #(
     reg [31:0] tdma_tic_2_ps_reg = 32'h0;
     reg [31:0] tdma_id_cfg_reg = 32'h0;  // 2B zero pad, 1B slot num, 1B local id
     reg [31:0] tdma_recv_id_reg = 32'h0;
+    reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
 
     // Register Reading
     always @(posedge local_clk) begin
@@ -378,6 +381,7 @@ module phy_control #(
                     TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
                     TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
                     TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
+                    TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
                 endcase
             end
             else begin
@@ -403,6 +407,8 @@ module phy_control #(
     // received mac frame 
     assign tdma_recv_cur_slot_id       = tdma_recv_id_reg[7:0];
     assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
+    // frame sync tic
+    assign tdma_frame_sync_tic         = tdma_frame_sync_tic_reg;
 
     vio_phy_param u_vio_phy_param (
         .clk      (local_clk),