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merge(sys): merge tdma update

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ZoroGH
2024-10-12 11:02:35 +08:00
parent ae78b3092d
commit fea952e06a
4 changed files with 48 additions and 84 deletions
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hdl/system_top.v
+22 -67
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@@ -125,6 +125,8 @@ module system_top (
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
wire [31:0] tdma_frame_sync_tic;
// tx signal
wire frame_sync_pulse;
@@ -170,11 +172,12 @@ module system_top (
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// gpio rf control
assign rf_io0_d3_18db = rf_gpio[0];
assign rf_io1_d4_12db = rf_gpio[1];
assign rf_io2_trx = rf_gpio[2];
assign rf_io3_d1_12db = rf_gpio[3];
assign rf_io4_d2_6db = rf_gpio[4];
assign rf_gpio[0] = rf_io0_d3_18db;
assign rf_gpio[1] = rf_io1_d4_12db;
assign rf_gpio[2] = rf_io2_trx;
assign rf_gpio[3] = rf_io3_d1_12db;
assign rf_gpio[4] = rf_io4_d2_6db;
assign rf_gpio[5] = 0;
// ******** Logic Block ********
@@ -266,6 +269,7 @@ module system_top (
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
.tdma_frame_sync_tic (tdma_frame_sync_tic),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
@@ -278,6 +282,7 @@ module system_top (
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]),
.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
.local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
@@ -288,32 +293,6 @@ module system_top (
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start
enc_control u_enc_control (
@@ -374,11 +353,6 @@ module system_top (
.err_flag_pos (rx_err_flag_pos)
);
// ---- PHY layer logic end
@@ -400,41 +374,22 @@ module system_top (
.tx_frame (ad9361_tx_frame)
);
// // ******** CDC ********
// ******** CDC ********
// // ******** Debug ********
// ******** Debug ********
// // ila_ad9361_rx u_ila_ad9361_rx (
// // .clk (ad9361_rx_clk),
// // .probe0(ad9361_rx_data_i),
// // .probe1(ad9361_rx_data_q),
// // .probe2(u_RecvTop.flag_mgc_done)
// // );
// ila_ad9361_rx u_ila_ad9361_rx (
// .clk (ad9361_rx_clk),
// .probe0(ad9361_rx_data_i),
// .probe1(ad9361_rx_data_q),
// .probe2(u_RecvTop.flag_mgc_done)
// );
// // ila_ad9361_tx u_ila_ad9361_tx (
// // .clk (ad9361_tx_clk), // input wire clk
// // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// // );
// // assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// // always @(posedge clk_1x) begin
// // tx_start_vio_d1 <= tx_start_vio;
// // end
// // assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// // always @(posedge clk_1x) begin
// // intr_2ps_vio_d1 <= intr_2ps_vio;
// // end
// vio_system_top u_vio_system_top (
// .clk (clk_1x),
// .probe_out0(node_id),
// .probe_out1(max_slot_num),
// .probe_out2(rst_manual)
// ila_ad9361_tx u_ila_ad9361_tx (
// .clk (ad9361_tx_clk), // input wire clk
// .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// );
vio_rf u_vio_rf (