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merge(sys): merge tdma update

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ZoroGH
2024-10-12 11:02:35 +08:00
parent ae78b3092d
commit fea952e06a
4 changed files with 48 additions and 84 deletions
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hdl/tdma.v
+9 -16
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@@ -13,9 +13,7 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter TIC_FRAME_SYNC = 44432
) (
module tdma (
input clk,
input rst,
// PHY parameter
@@ -24,6 +22,7 @@ module tdma #(
input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num,
input wire [23:0] tdma_frame_sync_tic,
input wire [ 7:0] local_id, // ID number for this device
// update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
@@ -102,15 +101,9 @@ module tdma #(
cnt_tdma_slot_len <= 0;
end
else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_tic_frame_sync_vio;
cnt_tdma_slot_len <= tdma_frame_sync_tic;
end
else begin
// if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
// cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
// end
// else begin
// cnt_tdma_slot_len <= 0;
// end
if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0;
end
@@ -172,12 +165,12 @@ module tdma #(
// ******** Debug ********
vio_tdma u_vio_tdma (
.clk (clk),
.probe_in0 (tdma_slot_len),
.probe_in1 (tdma_tic_2_ps),
.probe_in2 (tdma_slot_num),
.probe_in3 (local_id),
.probe_out0(tdma_tic_frame_sync_vio)
.clk (clk),
.probe_in0(tdma_slot_len),
.probe_in1(tdma_tic_2_ps),
.probe_in2(tdma_slot_num),
.probe_in3(local_id),
.probe_in4(tdma_frame_sync_tic)
);
ila_mac_layer u_ila_mac_layer (