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merge(sys): merge tdma update

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ZoroGH
2024-10-12 11:02:35 +08:00
parent ae78b3092d
commit fea952e06a
4 changed files with 48 additions and 84 deletions
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coe/rf_control_map.coe
+10
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@@ -0,0 +1,10 @@
memory_initialization_radix=2;
memory_initialization_vector=
1000
0100
0001
1001
0101
1101
0111
1111;
hdl/phy_control.v
+7 -1
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@@ -74,7 +74,8 @@ module phy_control #(
output wire [31:0] tdma_tic_2_ps, output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg, output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid, output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id output wire [ 7:0] tdma_recv_cur_slot_id,
output wire [31:0] tdma_frame_sync_tic
//--- ADD YOUR OWN PORTS END //--- ADD YOUR OWN PORTS END
); );
@@ -344,6 +345,7 @@ module phy_control #(
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2; localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2; localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2; localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
// Register definitions // Register definitions
reg [31:0] phy_cr_reg = 32'h0; reg [31:0] phy_cr_reg = 32'h0;
@@ -352,6 +354,7 @@ module phy_control #(
reg [31:0] tdma_tic_2_ps_reg = 32'h0; reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0; reg [31:0] tdma_recv_id_reg = 32'h0;
reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
// Register Reading // Register Reading
always @(posedge local_clk) begin always @(posedge local_clk) begin
@@ -378,6 +381,7 @@ module phy_control #(
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s; TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s; TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s; TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
endcase endcase
end end
else begin else begin
@@ -403,6 +407,8 @@ module phy_control #(
// received mac frame // received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0]; assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8]; assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
// frame sync tic
assign tdma_frame_sync_tic = tdma_frame_sync_tic_reg;
vio_phy_param u_vio_phy_param ( vio_phy_param u_vio_phy_param (
.clk (local_clk), .clk (local_clk),
hdl/system_top.v
+22 -67
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@@ -125,6 +125,8 @@ module system_top (
wire [31:0] tdma_id_cfg; wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid; wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id; wire [ 7:0] tdma_recv_cur_slot_id;
wire [31:0] tdma_frame_sync_tic;
// tx signal // tx signal
wire frame_sync_pulse; wire frame_sync_pulse;
@@ -170,11 +172,12 @@ module system_top (
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i; assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q; assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// gpio rf control // gpio rf control
assign rf_io0_d3_18db = rf_gpio[0]; assign rf_gpio[0] = rf_io0_d3_18db;
assign rf_io1_d4_12db = rf_gpio[1]; assign rf_gpio[1] = rf_io1_d4_12db;
assign rf_io2_trx = rf_gpio[2]; assign rf_gpio[2] = rf_io2_trx;
assign rf_io3_d1_12db = rf_gpio[3]; assign rf_gpio[3] = rf_io3_d1_12db;
assign rf_io4_d2_6db = rf_gpio[4]; assign rf_gpio[4] = rf_io4_d2_6db;
assign rf_gpio[5] = 0;
// ******** Logic Block ******** // ******** Logic Block ********
@@ -266,6 +269,7 @@ module system_top (
.tdma_id_cfg (tdma_id_cfg), .tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid), .tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id), .tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
.tdma_frame_sync_tic (tdma_frame_sync_tic),
// uart // uart
.uart_rx (uart_rx), .uart_rx (uart_rx),
.uart_tx (uart_tx) .uart_tx (uart_tx)
@@ -278,6 +282,7 @@ module system_top (
.tdma_slot_len (tdma_slot_len[23:0]), .tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]), .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]), .tdma_slot_num (tdma_id_cfg[15:8]),
.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
.local_id (tdma_id_cfg[7:0]), .local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid), .recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id), .recevied_cur_slot_id (tdma_recv_cur_slot_id),
@@ -288,32 +293,6 @@ module system_top (
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start // ---- PHY layer logic start
enc_control u_enc_control ( enc_control u_enc_control (
@@ -374,11 +353,6 @@ module system_top (
.err_flag_pos (rx_err_flag_pos) .err_flag_pos (rx_err_flag_pos)
); );
// ---- PHY layer logic end // ---- PHY layer logic end
@@ -400,41 +374,22 @@ module system_top (
.tx_frame (ad9361_tx_frame) .tx_frame (ad9361_tx_frame)
); );
// // ******** CDC ******** // ******** CDC ********
// // ******** Debug ******** // ******** Debug ********
// // ila_ad9361_rx u_ila_ad9361_rx ( // ila_ad9361_rx u_ila_ad9361_rx (
// // .clk (ad9361_rx_clk), // .clk (ad9361_rx_clk),
// // .probe0(ad9361_rx_data_i), // .probe0(ad9361_rx_data_i),
// // .probe1(ad9361_rx_data_q), // .probe1(ad9361_rx_data_q),
// // .probe2(u_RecvTop.flag_mgc_done) // .probe2(u_RecvTop.flag_mgc_done)
// // ); // );
// // ila_ad9361_tx u_ila_ad9361_tx ( // ila_ad9361_tx u_ila_ad9361_tx (
// // .clk (ad9361_tx_clk), // input wire clk // .clk (ad9361_tx_clk), // input wire clk
// // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0 // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1 // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// // );
// // assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
// // always @(posedge clk_1x) begin
// // tx_start_vio_d1 <= tx_start_vio;
// // end
// // assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
// // always @(posedge clk_1x) begin
// // intr_2ps_vio_d1 <= intr_2ps_vio;
// // end
// vio_system_top u_vio_system_top (
// .clk (clk_1x),
// .probe_out0(node_id),
// .probe_out1(max_slot_num),
// .probe_out2(rst_manual)
// ); // );
vio_rf u_vio_rf ( vio_rf u_vio_rf (
hdl/tdma.v
+4 -11
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@@ -13,9 +13,7 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID // ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE // ! WHEN U INSTANTIATE THIS MODULE
module tdma #( module tdma (
parameter TIC_FRAME_SYNC = 44432
) (
input clk, input clk,
input rst, input rst,
// PHY parameter // PHY parameter
@@ -24,6 +22,7 @@ module tdma #(
input wire [23:0] tdma_slot_len, input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps, input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num, input wire [ 7:0] tdma_slot_num,
input wire [23:0] tdma_frame_sync_tic,
input wire [ 7:0] local_id, // ID number for this device input wire [ 7:0] local_id, // ID number for this device
// update while received valid // update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
@@ -102,15 +101,9 @@ module tdma #(
cnt_tdma_slot_len <= 0; cnt_tdma_slot_len <= 0;
end end
else if (flag_frame_sync) begin else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_tic_frame_sync_vio; cnt_tdma_slot_len <= tdma_frame_sync_tic;
end end
else begin else begin
// if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
// cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
// end
// else begin
// cnt_tdma_slot_len <= 0;
// end
if (flag_end_of_one_slot) begin if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0; cnt_tdma_slot_len <= 0;
end end
@@ -177,7 +170,7 @@ module tdma #(
.probe_in1(tdma_tic_2_ps), .probe_in1(tdma_tic_2_ps),
.probe_in2(tdma_slot_num), .probe_in2(tdma_slot_num),
.probe_in3(local_id), .probe_in3(local_id),
.probe_out0(tdma_tic_frame_sync_vio) .probe_in4(tdma_frame_sync_tic)
); );
ila_mac_layer u_ila_mac_layer ( ila_mac_layer u_ila_mac_layer (