feat(top): new (de)scrambler, crc16

coe/bram_scramble.coe

@@ -0,0 +1,11 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+01010101111100101000010011111111
+11111010011001101010001100000111
+00101001010100111011101100111101
+01100011110011100110001011010010
+01111101101111010111010001000011
+10010000010101101101011001011000
+00010010111000000110010010011011
+00000101111000110100000001000111
+;

contraint/mm7020_timing.xdc

@@ -2,3 +2,10 @@ set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*]
 # set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid]
 # set_false_path -through [get_nets u_Receiver/rst]
 # set_false_path -through [get_nets  u_RecvTop/SR[0]]
+set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rst]
+set_false_path -through [get_nets phy_tx_test_flag]
+set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_tx_iq_reverse]
+set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rx_iq_reverse]
+set_false_path -through [get_nets tdma_flag_is_master]
+set_false_path -through [get_nets tdma_slot_len*]
+set_false_path -through [get_nets tdma_tic_2_ps*]

hdl/RecvTop.v

@@ -41,7 +41,12 @@ module RecvTop (
     output      [16:0] addr_stop,                //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
     // mac frame header
     output      [63:0] recvNetData,
-    output             recvNetDataNd
+    output             recvNetDataNd,
+    // rx data src
+    output wire [31:0] rx_data_src_fifo_tdata,
+    output wire        rx_data_src_fifo_tlast,
+    input  wire        rx_data_src_fifo_tready,
+    output wire        rx_data_src_fifo_tvalid
 );
 
     wire        rst_TimeSync;
@@ -495,6 +500,17 @@ module RecvTop (
         .total_frames(total_frames)
     );
 
+    extract_mac_frame u_extract_mac_frame (
+        .clk                    (clk_2x),
+        .rst                    (rst2 || rst_frame_sync || ~flag_frame_sync),
+        .ldpc_dec_out_start     (LDPC_SyncOut),
+        .ldpc_dec_out_valid     (LDPC_Rdy),
+        .ldpc_dec_out_data      (LDPC_Dout),
+        .m_axis_mac_frame_tvalid(rx_data_src_fifo_tvalid),
+        .m_axis_mac_frame_tdata (rx_data_src_fifo_tdata),
+        .m_axis_mac_frame_tready(rx_data_src_fifo_tready),
+        .m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
+    );
 
 
 

hdl/descrambler.v

@@ -0,0 +1,161 @@
+// * Engineer: 
+// * *************************************************** *
+// * ███████╗ ██████╗ ██████╗  ██████╗  ██████╗ ██╗  ██╗ *
+// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║  ██║ *
+// *   ███╔╝ ██║   ██║██████╔╝██║   ██║██║  ███╗███████║ *
+// *  ███╔╝  ██║   ██║██╔══██╗██║   ██║██║   ██║██╔══██║ *
+// * ███████╗╚██████╔╝██║  ██║╚██████╔╝╚██████╔╝██║  ██║ *
+// * ╚══════╝ ╚═════╝ ╚═╝  ╚═╝ ╚═════╝  ╚═════╝ ╚═╝  ╚═╝ *
+// * *************************************************** *
+// * Update Date: 
+// * NOTE       : 
+module scrambler #(
+    parameter ILA_ON = 0
+) (
+    input             clk,
+    input             rst_n,
+    // s_axis_stream
+    input      [31:0] s_axis_tdata,
+    input             s_axis_tvalid,
+    output reg        s_axis_tready,
+    input             s_axis_tlast,
+    input      [31:0] s_axis_rd_data_count,
+    // m_axis_stream
+    output reg [31:0] m_axis_tdata,
+    output reg        m_axis_tvalid,
+    input             m_axis_tready,
+    output reg        m_axis_tlast
+);
+
+
+    // ******** Wire & Reg  ********
+
+    wire        rst;
+
+    reg  [ 2:0] addr_scramble = 0;
+    reg  [ 2:0] addr_scramble_d1 = 0;
+    reg  [ 2:0] addr_scramble_d2 = 0;
+    wire [31:0] data_scramble_mask;
+    reg  [ 3:0] cnt_in;
+
+    reg  [31:0] s_axis_tdata_d1;
+    reg  [31:0] s_axis_tdata_d2;
+
+    reg         s_axis_tready_d1;
+    reg         s_axis_tlast_d1;
+    // fsm
+    reg  [ 1:0] cs = 0;
+    reg  [ 1:0] ns = 0;
+    localparam S_IDLE = 0;
+    localparam S_WORKING = 1;
+
+
+    // ******** Assingment  ********
+
+    assign rst = ~rst_n;
+
+    // ******** Logic Block ********
+
+    always @(posedge clk) begin
+        cs <= ns;
+    end
+
+    always @(*) begin
+        ns = cs;
+        case (cs)
+            S_IDLE: begin
+                if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 16) begin
+                    ns = S_WORKING;
+                end
+            end
+            S_WORKING: begin
+                if (addr_scramble_d2 == 3'h7) begin
+                    ns = S_IDLE;
+                end
+            end
+            default: begin
+                ns = S_IDLE;
+            end
+        endcase
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_IDLE) begin
+            addr_scramble <= 0;
+        end
+        else begin
+            addr_scramble <= addr_scramble + 1;
+        end
+        addr_scramble_d1 <= addr_scramble;
+        addr_scramble_d2 <= addr_scramble_d1;
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_WORKING) begin
+            m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
+        end
+        else begin
+            m_axis_tdata <= 0;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
+            s_axis_tready <= 1;
+        end
+        else begin
+            s_axis_tready <= 0;
+        end
+    end
+
+
+    always @(posedge clk) begin
+        s_axis_tdata_d1  <= s_axis_tdata;
+
+        s_axis_tready_d1 <= s_axis_tready;
+        m_axis_tvalid    <= s_axis_tready_d1;
+
+        s_axis_tlast_d1  <= s_axis_tlast;
+        m_axis_tlast     <= s_axis_tlast_d1;
+
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_IDLE) begin
+            cnt_in <= 0;
+        end
+        else if (cs == S_WORKING && cnt_in < 4'd8) begin
+            cnt_in <= cnt_in + 1;
+        end
+    end
+
+
+    // ********    Inst     ********
+
+    bram_scramble u_bram_scramble (
+        .clka (clk),                // input wire clka
+        .addra(addr_scramble),      // input wire [2 : 0] addra
+        .douta(data_scramble_mask)  // output wire [31 : 0] douta
+    );
+
+    // ********    Debug    ********
+
+    generate
+        if (ILA_ON)
+            ila_scrambler u_ila_scrambler (
+                .clk   (clk),                // input wire clk
+                .probe0(s_axis_tvalid),      // input wire [0:0]  probe0  
+                .probe1(s_axis_tready),      // input wire [0:0]  probe1 
+                .probe2(s_axis_tdata),       // input wire [31:0]  probe2 
+                .probe3(s_axis_tlast),       // input wire [0:0]  probe3 
+                .probe4(m_axis_tvalid),      // input wire [0:0]  probe4 
+                .probe5(m_axis_tready),      // input wire [0:0]  probe5 
+                .probe6(m_axis_tdata),       // input wire [31:0]  probe6 
+                .probe7(m_axis_tlast),       // input wire [0:0]  probe7 
+                .probe8(data_scramble_mask)  // input wire [31:0]  probe8
+            );
+
+    endgenerate
+
+
+endmodule

hdl/enc_control.v

@@ -338,4 +338,18 @@ module enc_control #(
 
     // ********    Debug    ********
 
+    // ila_enc_control u_ila_enc_control (
+    //     .clk   (clk),
+    //     .probe0(s_axis_fifo_tvalid),        // width: 1
+    //     .probe1(s_axis_fifo_tready),        // width: 1
+    //     .probe2(s_axis_fifo_tdata),         // width: 32
+    //     .probe3(data_src_count),            // width: 32
+    //     .probe4(cs),                        // width: 4
+    //     .probe5(wc_data_in_ready),          // width: 1
+    //     .probe6(wc_data_in_valid),          // width: 1
+    //     .probe7(wc_data_out_valid),         // width: 1
+    //     .probe8(data_add_prefix_in_ready),  // width: 1
+    //     .probe9(data_add_prefix_out_valid)  // width: 1
+    // );
+
 endmodule

hdl/extract_mac_frame.v

@@ -0,0 +1,82 @@
+module extract_mac_frame (
+    input              clk,
+    input              rst,
+    // ldpc out
+    input              ldpc_dec_out_start,
+    input              ldpc_dec_out_valid,
+    input              ldpc_dec_out_data,
+    // axis
+    output wire        m_axis_mac_frame_tvalid,
+    output wire [31:0] m_axis_mac_frame_tdata,
+    input              m_axis_mac_frame_tready,
+    output reg         m_axis_mac_frame_tlast
+
+);
+    // NOTE: module 1bit --> 32bit
+    // transfer 1bit serial to 32bit and sent to axis fifo
+    // 
+
+    localparam MAC_FRAME_LEN_BIT = 107520;
+    localparam MAC_FRAME_LEN_BYTE = 13440;
+    localparam MAC_FRAME_LEN_QUAD_BYTE = 3360;
+
+
+    // ******** Wire & Reg  ********
+
+    reg  [15:0] cnt_axis_out;
+    wire        flag_handshake;
+    // serial input 
+    wire        ser;
+    wire        ser_valid;
+    wire [31:0] par;
+    wire        par_valid;
+
+
+    // ******** Assingment  ********
+
+    assign ser                     = ldpc_dec_out_data;
+    assign ser_valid               = ldpc_dec_out_valid;
+    assign m_axis_mac_frame_tvalid = par_valid;
+    assign m_axis_mac_frame_tdata  = par;
+
+    assign flag_handshake          = m_axis_mac_frame_tvalid & m_axis_mac_frame_tready;
+
+    // ******** Logic Block ********
+
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_axis_out <= 0;
+        end
+        else if (flag_handshake) begin
+            cnt_axis_out <= cnt_axis_out + 1;
+        end
+    end
+
+    always @(*) begin
+        if (cnt_axis_out == MAC_FRAME_LEN_QUAD_BYTE - 1 && flag_handshake) begin
+            m_axis_mac_frame_tlast = 1;
+        end
+        else begin
+            m_axis_mac_frame_tlast = 0;
+        end
+    end
+
+    // ********    Inst     ********
+
+    // serial 1bit --> 32bit
+    ser2par u_ser2par (
+        .clk      (clk),
+        .rst      (rst),
+        .ser      (ser),
+        .ser_valid(ser_valid),
+        .par      (par),
+        .par_valid(par_valid)
+    );
+
+
+
+    // ********    Debug    ********
+
+
+
+endmodule

hdl/phy_control.v

@@ -63,8 +63,16 @@ module phy_control #(
     // resetn (should synchronised with "clk")
     input rstn, // can be floating if ASYNC_CLK == 0
 
+    // control sigal
     output wire        phy_rst,
-    output wire phy_tx_test_flag
+    output wire        phy_tx_test_flag,
+    output wire        phy_tx_iq_reverse,
+    output wire        phy_rx_iq_reverse,
+    // tdma parameters
+    output wire        tdma_flag_is_master,
+    output wire [31:0] tdma_slot_len,
+    output wire [31:0] tdma_tic_2_ps
+
     //--- ADD YOUR OWN PORTS END
 );
 
@@ -329,10 +337,14 @@ module phy_control #(
 
     localparam integer PHY_CR = 'h00000000 >> 2;  // RW
     localparam integer PHY_SR = 'h00000004 >> 2;  // RW
+    localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
+    localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
 
     // Register definitions
     reg [31:0] phy_cr_reg = 32'h0;
     reg [31:0] phy_sr_reg = 32'h0;
+    reg [31:0] tdma_slot_len_reg = 32'h0;
+    reg [31:0] tdma_tic_2_ps_reg = 32'h0;
 
     // Register Reading
     always @(posedge local_clk) begin
@@ -355,6 +367,8 @@ module phy_control #(
                 case (up_waddr_s)
                     PHY_CR: phy_cr_reg <= up_wdata_s;
                     PHY_SR: phy_sr_reg <= up_wdata_s;
+                    TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
+                    TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
                 endcase
             end
             else begin
@@ -367,9 +381,18 @@ module phy_control #(
     // control reg definition
     assign phy_rst             = ~phy_cr_reg[0];
     assign phy_tx_test_flag    = phy_cr_reg[1];
+    assign phy_tx_iq_reverse   = phy_cr_reg[2];
+    assign phy_rx_iq_reverse   = phy_cr_reg[3];
+    assign tdma_flag_is_master = phy_cr_reg[4];
+    // tdma
+    assign tdma_slot_len       = tdma_slot_len_reg;
+    assign tdma_tic_2_ps       = tdma_tic_2_ps_reg;
 
 
-
+    vio_phy_param u_vio_phy_param (
+        .clk      (local_clk),
+        .probe_in0(phy_cr_reg)
+    );
 
     //--- ADD YOUR OWN LOGIC END
 

hdl/scrambler.v

@@ -0,0 +1,161 @@
+// * Engineer: 
+// * *************************************************** *
+// * ███████╗ ██████╗ ██████╗  ██████╗  ██████╗ ██╗  ██╗ *
+// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║  ██║ *
+// *   ███╔╝ ██║   ██║██████╔╝██║   ██║██║  ███╗███████║ *
+// *  ███╔╝  ██║   ██║██╔══██╗██║   ██║██║   ██║██╔══██║ *
+// * ███████╗╚██████╔╝██║  ██║╚██████╔╝╚██████╔╝██║  ██║ *
+// * ╚══════╝ ╚═════╝ ╚═╝  ╚═╝ ╚═════╝  ╚═════╝ ╚═╝  ╚═╝ *
+// * *************************************************** *
+// * Update Date: 
+// * NOTE       : 
+module scrambler #(
+    parameter ILA_ON = 0
+) (
+    input             clk,
+    input             rst_n,
+    // s_axis_stream
+    input      [31:0] s_axis_tdata,
+    input             s_axis_tvalid,
+    output reg        s_axis_tready,
+    input             s_axis_tlast,
+    input      [31:0] s_axis_rd_data_count,
+    // m_axis_stream
+    output reg [31:0] m_axis_tdata,
+    output reg        m_axis_tvalid,
+    input             m_axis_tready,
+    output reg        m_axis_tlast
+);
+
+
+    // ******** Wire & Reg  ********
+
+    wire        rst;
+
+    reg  [ 2:0] addr_scramble = 0;
+    reg  [ 2:0] addr_scramble_d1 = 0;
+    reg  [ 2:0] addr_scramble_d2 = 0;
+    wire [31:0] data_scramble_mask;
+    reg  [ 3:0] cnt_in;
+
+    reg  [31:0] s_axis_tdata_d1;
+    reg  [31:0] s_axis_tdata_d2;
+
+    reg         s_axis_tready_d1;
+    reg         s_axis_tlast_d1;
+    // fsm
+    reg  [ 1:0] cs = 0;
+    reg  [ 1:0] ns = 0;
+    localparam S_IDLE = 0;
+    localparam S_WORKING = 1;
+
+
+    // ******** Assingment  ********
+
+    assign rst = ~rst_n;
+
+    // ******** Logic Block ********
+
+    always @(posedge clk) begin
+        cs <= ns;
+    end
+
+    always @(*) begin
+        ns = cs;
+        case (cs)
+            S_IDLE: begin
+                if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 8) begin
+                    ns = S_WORKING;
+                end
+            end
+            S_WORKING: begin
+                if (addr_scramble_d2 == 3'h7) begin
+                    ns = S_IDLE;
+                end
+            end
+            default: begin
+                ns = S_IDLE;
+            end
+        endcase
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_IDLE) begin
+            addr_scramble <= 0;
+        end
+        else begin
+            addr_scramble <= addr_scramble + 1;
+        end
+        addr_scramble_d1 <= addr_scramble;
+        addr_scramble_d2 <= addr_scramble_d1;
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_WORKING) begin
+            m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
+        end
+        else begin
+            m_axis_tdata <= 0;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
+            s_axis_tready <= 1;
+        end
+        else begin
+            s_axis_tready <= 0;
+        end
+    end
+
+
+    always @(posedge clk) begin
+        s_axis_tdata_d1  <= s_axis_tdata;
+
+        s_axis_tready_d1 <= s_axis_tready;
+        m_axis_tvalid    <= s_axis_tready_d1;
+
+        s_axis_tlast_d1  <= s_axis_tlast;
+        m_axis_tlast     <= s_axis_tlast_d1;
+
+    end
+
+    always @(posedge clk) begin
+        if (cs == S_IDLE) begin
+            cnt_in <= 0;
+        end
+        else if (cs == S_WORKING && cnt_in < 4'd8) begin
+            cnt_in <= cnt_in + 1;
+        end
+    end
+
+
+    // ********    Inst     ********
+
+    bram_scramble u_bram_scramble (
+        .clka (clk),                // input wire clka
+        .addra(addr_scramble),      // input wire [2 : 0] addra
+        .douta(data_scramble_mask)  // output wire [31 : 0] douta
+    );
+
+    // ********    Debug    ********
+
+    generate
+        if (ILA_ON)
+            ila_scrambler u_ila_scrambler (
+                .clk   (clk),                // input wire clk
+                .probe0(s_axis_tvalid),      // input wire [0:0]  probe0  
+                .probe1(s_axis_tready),      // input wire [0:0]  probe1 
+                .probe2(s_axis_tdata),       // input wire [31:0]  probe2 
+                .probe3(s_axis_tlast),       // input wire [0:0]  probe3 
+                .probe4(m_axis_tvalid),      // input wire [0:0]  probe4 
+                .probe5(m_axis_tready),      // input wire [0:0]  probe5 
+                .probe6(m_axis_tdata),       // input wire [31:0]  probe6 
+                .probe7(m_axis_tlast),       // input wire [0:0]  probe7 
+                .probe8(data_scramble_mask)  // input wire [31:0]  probe8
+            );
+
+    endgenerate
+
+
+endmodule

hdl/ser2par.v

@@ -0,0 +1,61 @@
+module ser2par #(
+    parameter PAR_WIDTH = 32
+) (
+    input                        clk,
+    input                        rst,
+    input  wire                  ser,
+    input  wire                  ser_valid,
+    output reg  [PAR_WIDTH -1:0] par,
+    output reg                   par_valid
+);
+
+    // ******** Wire & Reg  ********
+    reg [$clog2(PAR_WIDTH):0] cnt_idx;
+
+    // ******** Assingment  ********
+
+    // ******** Logic Block ********
+
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_idx <= 0;
+        end
+        else if (ser_valid) begin
+            if (cnt_idx == PAR_WIDTH - 1) begin  // force it return to 0
+                cnt_idx <= 0;
+            end
+            else begin
+                cnt_idx <= cnt_idx + 1;
+            end
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            par <= 0;
+        end
+        else if (ser_valid) begin
+            par[cnt_idx] <= ser;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (cnt_idx == PAR_WIDTH - 1) begin
+            par_valid <= 1;
+        end
+        else begin
+            par_valid <= 0;
+        end
+    end
+
+
+    // ********    Inst     ********
+
+    // ********    Debug    ********
+
+
+
+
+
+
+endmodule

hdl/system_top.v

@@ -90,6 +90,11 @@ module system_top (
     // tx signal 
     wire        tx_test_flag;
     wire        flag_mgc_done_pulse;
+    // rx bus
+    wire [31:0] rx_data_src_fifo_tdata;
+    wire        rx_data_src_fifo_tlast;
+    wire        rx_data_src_fifo_tready;
+    wire        rx_data_src_fifo_tvalid;
 
     // baseband signal
     wire [11:0] ad9361_rx_data_i;
@@ -109,10 +114,14 @@ module system_top (
 
     // phy control signal
     wire        phy_rst_vio;
-    wire        phy_rst_ps;
     wire        phy_rst;
     wire        phy_tx_test_flag_vio;
     wire        phy_tx_test_flag;
+    wire        phy_tx_iq_reverse;
+    wire        phy_rx_iq_reverse;
+    wire        tdma_flag_is_master;
+    wire [31:0] tdma_slot_len;
+    wire [31:0] tdma_tic_2_ps;
 
     // tx signal
     wire        frame_sync_pulse;
@@ -128,6 +137,7 @@ module system_top (
 
     // vio
     wire        rst_manual;
+    wire        rx_rst_vio;
     wire [ 7:0] node_id;
     wire        intr_2ps;
     wire [ 7:0] max_slot_num;
@@ -143,10 +153,10 @@ module system_top (
     assign ad9361_txnrx     = gpio_o[3];  // ad9361 txnrx
 
 
-    assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i;
+    assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i;
-    assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q;
+    assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
-    assign bb_rx_i          = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
+    assign bb_rx_i          = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
-    assign bb_rx_q          = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
+    assign bb_rx_q          = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
 
     // ******** Logic Block ********
 
@@ -208,38 +218,46 @@ module system_top (
         .gpio_o                 (gpio_o),
         .gpio_t                 (gpio_t),
         // intr  pl to ps
-        .pl2ps_intr2       (intr_2ps),
+        .pl_tx_intr             (intr_2ps | intr_2ps_vio_pos),
-        .pl2ps_intr3       (flag_mgc_done_pulse),
+        .pl_rx_intr             (rx_data_src_fifo_tlast),
         // tx fifo
         .tx_data_src_count      (tx_data_src_count),
         .tx_data_src_tdata      (tx_data_src_tdata),
-        .tx_data_src_tready(tx_data_src_tready),
+        .tx_data_src_tready     (tx_data_src_tready),
-        .tx_data_src_tvalid(tx_data_src_tvalid),
+        .tx_data_src_tvalid     (tx_data_src_tvalid),
-        //phy control signal
+        // rx fifo
-        .phy_rst           (phy_rst_ps),
+        .clk_rx_data_src_fifo   (clk_2x),
+        .rst_rx_data_src_fifo   (rx_rst),
+        .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
+        .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
+        .rx_data_src_fifo_tready(rx_data_src_fifo_tready),
+        .rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
+        // phy control signal
+        .phy_rst                (phy_rst),
         .phy_tx_test_flag       (phy_tx_test_flag),
+        .phy_tx_iq_reverse      (phy_tx_iq_reverse),
+        .phy_rx_iq_reverse      (phy_rx_iq_reverse),
+        .tdma_flag_is_master    (tdma_flag_is_master),
+        .tdma_slot_len          (tdma_slot_len),
+        .tdma_tic_2_ps          (tdma_tic_2_ps),
         // uart 
         .uart_rx                (uart_rx),
         .uart_tx                (uart_tx)
     );
 
+    // tdma u_tdma (
+    //     .clk            (clk_1x),
+    //     .rst            (rst_sys),
+    //     .flag_is_master (tdma_flag_is_master),
+    //     .flag_frame_sync(frame_sync_pulse),
+    //     .tdma_slot_len  (tdma_slot_len[23:0]),
+    //     .tdma_tic_2_ps  (tdma_tic_2_ps[23:0]),
+    //     .intr_2ps       (intr_2ps),
+    //     .tx_start       (tx_start),
+    //     .rx_rst         (rx_rst)
+    // );
+
 
-    tdma #(
-        .SLOT_LEN      (750000),  // 50MHz--> 15ms
-        .TIC_TO_PS_LEN (700000),
-        .TIC_FRAME_SYNC(42344)
-        // .SLOT_LEN      (625001),  // 50MHz--> 15ms
-        // .TIC_TO_PS_LEN (575000),
-        // .TIC_FRAME_SYNC(42344)
-    ) u_tdma (
-        .clk            (clk_1x),
-        .rst            (rst_sys),
-        .flag_is_master (flag_is_master),
-        .flag_frame_sync(frame_sync_pulse),
-        .intr_2ps       (intr_2ps),
-        .tx_start       (tx_start),
-        .rx_rst         (rx_rst)
-    );
 
     // net_city u_net_city (
     //     .clk             (clk_1x),
@@ -270,7 +288,7 @@ module system_top (
 
     enc_control u_enc_control (
         .clk                  (clk_poweron),
-        .rst                  (rst_sys | phy_rst_ps),
+        .rst                  (rst_sys | phy_rst),
         .s_axis_fifo_tvalid   (tx_data_src_tvalid),
         .s_axis_fifo_tready   (tx_data_src_tready),
         .s_axis_fifo_tdata    (tx_data_src_tdata),
@@ -287,7 +305,7 @@ module system_top (
         .rst               (rst_sys | phy_rst),
         .speed_mode        (2),
         .send_data_ready   (send_data_ready),
-        .send_start        (tx_start),
+        .send_start        (tx_start | tx_start_vio_pos),
         .send_over         (tx_done),
         .clk_data_src      (clk_data_src),
         .tx_data_src_tdata (enc_fifo_dout_map),
@@ -296,7 +314,7 @@ module system_top (
         .hopping_freq      (),
         .ad9361_tx_data_i  (bb_tx_i),
         .ad9361_tx_data_q  (bb_tx_q),
-        .test              (tx_test_flag | phy_tx_test_flag_vio),
+        .test              (phy_tx_test_flag),
         .hop_wait          (100)
     );
 
@@ -304,12 +322,12 @@ module system_top (
         .clk                    (clk_1x),
         .clk_2x                 (clk_2x),
         .clk_4x                 (clk_4x),
-        .rst                (rst_sys | rx_rst | phy_rst),
+        .rst                    (rst_sys | rx_rst | phy_rst | rx_rst_vio),
         .rst2                   (rst_sys | phy_rst),
         .dini                   (bb_rx_i),
         .dinq                   (bb_rx_q),
         .ad9361_ctrl_in         (ad9361_ctrl_in),
-        .flag_mgc_done_pulse(flag_mgc_done_pulse),
+        .flag_mgc_done_pulse    (flag_mgc_done_pulse),
         .frame_sync_pulse       (frame_sync_pulse),
         .vio_tsync_inter16      (1),
         .EQUenable_vio          (1),
@@ -318,7 +336,11 @@ module system_top (
         .flag_stop              (flag_stop),
         .addr_stop              (addr_stop),
         .recvNetData            (recvNetData),
-        .recvNetDataNd      (recvNetDataNd)
+        .recvNetDataNd          (recvNetDataNd),
+        .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
+        .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
+        .rx_data_src_fifo_tready(rx_data_src_fifo_tready),
+        .rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
     );
 
 
@@ -349,28 +371,6 @@ module system_top (
 
     // ********     CDC     ********
 
-    xpm_cdc_single #(
-        .DEST_SYNC_FF  (4),  // DECIMAL; range: 2-10
-        .INIT_SYNC_FF  (0),  // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-        .SIM_ASSERT_CHK(0),  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
-        .SRC_INPUT_REG (1)   // DECIMAL; 0=do not register input, 1=register input
-    ) xpm_cdc_single_tx_test_flag_ps_inst (
-        .dest_out(tx_test_flag),     // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
-        .dest_clk(clk_1x),           // 1-bit input: Clock signal for the destination clock domain.
-        .src_clk (clk_poweron),      // 1-bit input: optional; required when SRC_INPUT_REG = 1
-        .src_in  (phy_tx_test_flag)  // 1-bit input: Input signal to be synchronized to dest_clk domain.
-    );
-
-    xpm_cdc_sync_rst #(
-        .DEST_SYNC_FF  (4),  // DECIMAL; range: 2-10
-        .INIT          (1),  // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
-        .INIT_SYNC_FF  (0),  // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-        .SIM_ASSERT_CHK(0)   // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
-    ) xpm_cdc_sync_rst_phy_rst_inst (
-        .dest_rst(phy_rst),    // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered.
-        .dest_clk(clk_1x),     // 1-bit input: Destination clock.
-        .src_rst (phy_rst_ps)  // 1-bit input: Source reset signal.
-    );
 
     // ********    Debug    ********
 
@@ -399,13 +399,11 @@ module system_top (
     end
 
 
-
+    vio_system_top u_vio_system_top (
-    vio_phy_control u_vio_phy_control (
+        .clk       (clk_1x),
-        .clk       (clk_1x),            // input wire clk
+        .probe_out0(rx_rst_vio),
-        .probe_out0(flag_is_master),    // output wire [0 : 0]
+        .probe_out1(tx_start_vio),
-        .probe_out1(bb_tx_iq_reverse),  // output wire [0 : 0]
+        .probe_out2(intr_2ps_vio)
-        .probe_out2(bb_rx_iq_reverse)   // output wire [0 : 0]
     );
 
-
 endmodule

hdl/tdma.v

@@ -14,14 +14,14 @@
 // ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
 // ! WHEN U INSTANTIATE THIS MODULE
 module tdma #(
-    parameter SLOT_LEN = 750000,
-    parameter TIC_TO_PS_LEN = 700000,
     parameter TIC_FRAME_SYNC = 42344
 ) (
     input              clk,
     input              rst,
-    input      flag_is_master,   // TODO: refactor it to parameters
+    input              flag_is_master,
     input              flag_frame_sync,
+    input  wire [23:0] tdma_slot_len,
+    input  wire [23:0] tdma_tic_2_ps,
     output             intr_2ps,
     output             tx_start,
     output reg         rx_rst
@@ -38,7 +38,7 @@ module tdma #(
     // ******** Assingment  ********
 
     assign tx_start = flag_is_master & (cnt == 16'd10);
-    assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1);
+    assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1);
 
     // ******** Logic Block ********
 
@@ -55,7 +55,7 @@ module tdma #(
             end
             else begin
                 // master
-                if (cnt < SLOT_LEN - 1) begin
+                if (cnt < tdma_slot_len - 1) begin
                     cnt <= cnt + 1;
                 end
                 else begin
@@ -75,26 +75,16 @@ module tdma #(
         end
     end
 
-    // always @(posedge clk) begin
-    //     if (rst) begin
-    //         flag_is_tx_slot <= 0;
-    //     end
-    //     else if (!flag_is_master && flag_frame_sync) begin
-    //         flag_is_tx_slot <= 0;
-    //     end
-    //     else if (cnt == 16'd1) begin
-    //         flag_is_tx_slot <= ~flag_is_tx_slot;
-    //     end
-    // end
-
-
-
-
-
     // ********    Inst     ********
 
     // ********    Debug    ********
 
+    vio_tdma u_vio_tdma (
+        .clk      (clk),
+        .probe_in0(tdma_slot_len),
+        .probe_in1(tdma_tic_2_ps),
+        .probe_in2(flag_is_master)
+    );
 
     ila_mac_layer u_ila_mac_layer (
         .clk   (clk),

hdl/width_convert.v

@@ -12,13 +12,13 @@
 // * NOTE       : this is the first version convert from wider bitwidth to narrower bitwidth 
 
 module width_convert #(
-    parameter INPUT_WIDTH  = 16,
+    parameter INPUT_WIDTH  = 32,
-    parameter OUTPUT_WIDTH = 2
+    parameter OUTPUT_WIDTH = 1
 ) (
     input                             clk,
     input                             rst,
     input                             data_in_valid,
-    input  wire                       data_in_ready,
+    output wire                       data_in_ready,
     input  wire [INPUT_WIDTH - 1 : 0] data_in,
     output reg                        data_out_valid,
     output reg  [OUTPUT_WIDTH -1 : 0] data_out

sim/tb_extract_mac_frame.v

@@ -0,0 +1,82 @@
+`timescale 1ns / 1ns
+
+module tb_extract_mac_frame ();
+
+    reg clk = 0;
+    always #1 clk <= ~clk;
+
+    reg  [ 3:0] cnt_startup = 0;
+    reg         rst;
+
+    reg         ldpc_in;
+    reg  [31:0] cnt_in = 0;
+    reg  [ 4:0] cnt_sleep = 0;
+    reg         sleep = 0;
+    reg         cnt_in_valid = 0;
+
+
+    wire        m_axis_mac_frame_tvalid;
+    wire [31:0] m_axis_mac_frame_tdata;
+    wire        m_axis_mac_frame_tlast;
+
+    always @(posedge clk) begin
+
+        if (m_axis_mac_frame_tlast == 1) begin
+            cnt_startup <= 0;
+        end
+        else if (cnt_startup < 4'hF) begin
+            cnt_startup <= cnt_startup + 1;
+        end
+        rst <= cnt_startup <= 4'hC;
+
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_in <= 0;
+        end
+
+        ldpc_in <= $random();
+
+        if (cnt_startup == 4'hF) begin
+            if (sleep) begin
+                cnt_in       <= 0;
+                cnt_in_valid <= 0;
+                cnt_sleep    <= cnt_sleep + 1;
+                if (cnt_sleep == 5'b11111) begin
+                    sleep <= 0;
+                end
+            end
+            else begin
+                cnt_sleep <= 0;
+                if (cnt_in < 1024) begin
+                    cnt_in <= cnt_in + 1;
+                end
+
+                if (cnt_in == 1023) begin
+                    sleep <= 1;
+                end
+
+                cnt_in_valid <= 1;
+            end
+        end
+    end
+
+    extract_mac_frame u_extract_mac_frame (
+        .clk                    (clk),
+        .rst                    (rst),
+        .ldpc_dec_out_start     (cnt_startup == 4'hD),
+        .ldpc_dec_out_valid     (cnt_in_valid),
+        .ldpc_dec_out_data      (ldpc_in),
+        .m_axis_mac_frame_tvalid(m_axis_mac_frame_tvalid),
+        .m_axis_mac_frame_tdata (m_axis_mac_frame_tdata),
+        .m_axis_mac_frame_tready(1),
+        .m_axis_mac_frame_tlast (m_axis_mac_frame_tlast)
+    );
+
+
+
+
+
+
+endmodule

sim/tb_scrambler.v

@@ -0,0 +1,53 @@
+`timescale 1ns / 1ns
+module tb_scrambler ();
+
+
+    reg clk = 0;
+    always #1 clk <= ~clk;
+    reg [3:0] cnt_startup = 0;
+    reg       rst;
+
+    always @(posedge clk) begin
+        if (cnt_startup < 4'hF) begin
+            cnt_startup <= cnt_startup + 1;
+        end
+        rst <= cnt_startup <= 4'hC;
+    end
+
+
+    reg  [31:0] s_axis_tdata;
+    reg         s_axis_tvalid;
+    wire        s_axis_tready;
+    reg         s_axis_tlast;
+    wire [31:0] m_axis_tdata;
+    wire        m_axis_tvalid;
+    // wire        m_axis_tvalid;
+    wire        m_axis_tlast;
+    reg  [31:0] cnt = 0;
+
+    always @(posedge clk) begin
+        s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32);
+        if (rst) begin
+            s_axis_tdata <= 0;
+        end
+        else if (s_axis_tready && cnt < 32) begin
+            s_axis_tdata <= cnt;
+            cnt          <= cnt + 1;
+        end
+    end
+
+    scrambler u_scrambler (
+        .clk          (clk),
+        .rst          (rst),
+        .s_axis_tdata (s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tready(s_axis_tready),
+        .s_axis_tlast (s_axis_tlast),
+        .m_axis_tdata (m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tready(1),
+        .m_axis_tlast (m_axis_tlast)
+    );
+
+
+endmodule